The document discusses the implementation of the Advanced Encryption Standard (AES) using the Rijndael algorithm, detailing its structure, including the AES cipher and inverse cipher core. It highlights the key expansion for a 128-bit key and reports on the synthesis and simulation processes using various tools like ModelSim and FPGA compiler. The document concludes with a mention of layout generation for ASIC using TSMC technology.

1. AES – Advanced Encryption Standard
ECE 652
AES Core
Rishi Raj Srivastava
Nitin Tiwari

2. AES – Advanced Encryption Std
Rijndael is AES. AES is the latest Federal Information
Processing Standard (FIPS).
Rijndael designed by Joan Daemen and Vincent Rijmen
(Belgium)
Rijndael is Block Cipher. The current versions can have 128,
192 or 256 bit key to cipher blocks of 128, 192 or 256 bits with
all nine combinations possible.
Rijndael's combination of security, performance, efficiency,
ease of implementation and flexibility make it an appropriate
selection for the AES. Its Round Permutation Module can be
looped 10, 12 0r 14 rounds.

3. Introduction
AES/Rijndael IP core is being implemented This
implementation is with a 128 bit key expansion
module
The AES /Rijndael core consists of two blocks:
AES Cipher Core
AES Inverse Cipher Core

4. AES Cipher Core
The Round permutation module loops 10 times
This Block can perform complete sequence in 12 cycles

5. AES Inverse Cipher Core
The Round permutation module loops 10 times
This block can perform decrypt sequence in 12 cycles.

6. Work Done
Pre-synthesis simulation done using modelsim
Synthesis and PAR completed on the AES cipher
core for Virtex 1000e using FPGA compiler and ngd
build.
Since the cipher core had 128 Bit Key and Text
I/p, a top was made to take 32 bits at a time to get
the desired input key and text.
Synthesis for TSMC 18 done using design compiler
and PAR done using Seultra. The gds2 file was
imported to ICFB and a layout was achieved.

7. Pre Layout simulation

8. Pre layout simulation

9. Layout ASIC tsmc 0.18