This document discusses binary and BCD adders and subtractors, including half-adders, full-adders, 4-bit binary adders, BCD adders, half/full subtractors, and multiplexers. It also discusses instruction set architecture (ISA), comparing RISC and CISC architectures, and the Intel x86 programming model.

1. BINARY / BCD ADDERS AND SUBTRACTORS
When two bits x and y are added, a sum and a carry are generated

2. HALF-ADDER
Block Diagram
Truth Table
Combinational Circuit
S = x’y + xy’ = x  y
C = xy

3. FULL-ADDER
Block Diagram

4. Truth Table
FULL-ADDER
S = x'y'z + x'yz' + xy'z' + xyz
= (x'y + xy')z' + (xy + x'y')z
Let w = x'y + xy' = x  y
w' = (x'y + xy')'
= (x'y)'(xy')'
= (x+y')(x'+y)
= xy + x'y'
S = wz' + w'z
= w  z
= x  y  z
C = x'yz + xy'z + xyz' + xyz
= (x'y + xy')z + xy(z + z')
= wz + xy
= (x  y)z + xy

5. Combinational Circuit
FULL-ADDER

6. 4 – BIT BINARY ADDER (Ripple Carry Adder)
1 half-adder, 3 full-adders
4 full-adders

7. EXAMPLE
x = 310 (00112), y = 5 (01012)
11100100
0101011
0

8. BCD ADDER

9. HALF / FULL SUBTRACTOR

10. MULTIPLEXER
A multiplexer (MUX) is a combinational circuit that selects one of n input
lines and provides it on the output.
It has several inputs and only one output. The select lines identify or address one of several
inputs and provides it on the output line.
2-to-1 multiplexer block diagram
K-map of 2-to-1 MUX
Logic circuit of 2-to-1 MUXZ = S'd0 + Sd1

11. A large multiplexer can be implemented using a small multiplexer as the building block
4-to-1 multiplexer block diagram

12. Example: Implement Boolean equation f(x,y,z) = xz’ + yz using multiplexers
Step 1: Express the equation as sum of products (minterms)
f (x,y,z) = xz’ (y + y’) + yz (x + x’) = xyz’ + xy’z’ + xyz + x’yz
Step 2: Choose 2 of the 3 variables as select inputs, e.g. y and z.
f (x,y,z) = xz’ (y + y’) + yz (x + x’) = xyz’ + xy’z’ + xyz + x’yz
Step 3: Factor out all combinations of the chosen variables as select inputs in the minterm.
(y’z’, y’z, yz’, yz)
f (x,y,z) = xyz’ + xy’z’ + xyz + x’yz
= y’z’(x) + y’z (0) + yz’ (x) + yz (x + x’)
= y’z’(x) + y’z (0) + yz’ (x) + yz (1)

13. INSTRUCTION SET ARCHITECTURE (ISA)
What Is An ISA?
A well-define hardware/software interface that defines the functional operations, modes,
and storage locations supported by hardware through precise description of how to
invoke, and access them
Functionalities in designing ISA
• Allows communication of the capabilities of the hardware through software
• Common operations:
- memory addressing
- data movement
- arithmetic and logic
- program flow control
Instruction set architecture(ISA) is the set of processor design techniques used to
implement the instruction work flow on hardware.

14. What Makes a Good ISA?
• Programmability
Easy to express programs efficiently?
• Implementability
Easy to design high-performance implementations?
Easy to design low-power implementations?
Easy to design high-reliability implementations?
Easy to design low-cost implementations?
Compatibility
Easy to maintain programmability (implementability) as languages and
programs (technology) evolves?
x86 (IA32) generations: 8086, 286, 386, 486, Pentium, PentiumII, PentiumIII,
Pentium4,…

15. RISC AND CISC
RISC: reduced-instruction set computer
RISC processors only use simple instructions that can be executed within one clock
cycle.
Single-cycle execution
Fixed instruction format
Load/Store architecture
Examples: PowerPC, ARM, SPARC, Alpha, PA-RISC
Advantage:
1. Each instruction requires only one clock cycle to execute, the entire program will
execute in approximately the same amount of time as the multi-cycle “MULT”
command.
2. These RISC “reduced instructions” require less transistors of hardware space than
the complex instructions, leaving more room for general purpose registers.
Because all of the instructions execute in a uniform amount of time (i.e. one clock)
3. Pipelining is possible.

16. CISC: complex-instruction set computer
The primary goal of CISC architecture is to complete a task in as few lines of assembly as
possible. This is achieved by building processor hardware that is capable of
understanding & executing a series of operations, this is where our CISC architecture
introduced .
Variable-length instructions (1-16 bytes)
Support different addressing modes
Examples: x86, VAX, Motorola 68000, etc.
Advantage:
1. Compiler has to do very little work to translate a high-level language statement into
assembly
2. Length of the code is relatively short
3. Very little RAM is required to store instructions
4. The emphasis is put on building complex instructions directly into the hardware.

17. THE INTEL X86 PROGRAMMING MODEL