Loading Multiple Versions of an ASDF System in the Same Lisp ImageVsevolod Dyomkin
This document outlines an approach to loading multiple versions of an ASDF system in the same Lisp image by resolving name conflicts between dependencies. It discusses the "dependency hell" problem, solutions used in other languages, and limitations of the Common Lisp package and ASDF systems. The proposed algorithm assembles a dependency tree, determines a load order while resolving conflicts, loads systems one by one while renaming packages as needed, and caches already loaded systems. This approach allows loading a system's components without reloading dependencies but has limitations such as not handling implicit transitive dependencies or interactive workflows. The goal is to build on ASDF to create a more complete and reusable "ASDFx" system loading framework.
Extracting Linux kernel feature model changes with FMDiff NicoDintzner
Presentation of the research work of Nicolas Dintzner, Arie van Deursen and Martin Pinzger on the evolution of feature models. This presentation was given at the VaMoS 2014 workshop.
The e820 trap of Linux kernel hibernationjoeylikernel
The document discusses the e820 trap that can occur during Linux kernel hibernation (suspend to disk) restoration. It describes how the BIOS memory map reported via e820 can shift between boot and resume, causing pages saved in the hibernation image to be located in reserved memory regions upon restoration. This leads to page faults and failure to resume. Other challenges discussed include EFI memory mapping issues, memory size mismatches, and identification of non-saveable regions.
PCI Express support has been added to Qemu to allow for emulation of PCI Express devices and functionality like hotplug. This includes a Q35 chipset emulator, PCI Express port emulators, and the ability to inject errors into guest systems. Further work is still needed to integrate these features with Xen for full PCI Express and hotplug support virtualization.
This document discusses configuring and troubleshooting display devices, I/O devices, and ACPI in Windows XP. It covers setting up multiple displays, ensuring secondary displays meet requirements, and addressing common multiple display issues. Troubleshooting tips are provided for displays, input devices like keyboards and mice, as well as printers, scanners and other peripherals. The document also discusses Windows XP's support for ACPI which allows the operating system to control power consumption in computers.
Comp tia flashcards set 1 (15 cards) acpi cmosSue Long Smith
This document contains flashcards defining various computer-related terms starting with letters A through C, including definitions for ACPI, ADSL, AGP, AMD, AMR, APIPA, ARP, BIOS, BRI, BTX, CD-ROM, CD-RW, CDFS, CGA, and CMOS. Each term is defined in 1-2 sentences explaining its purpose or function within computing systems.
Kernel Recipes 2015: Representing device-tree peripherals in ACPIAnne Nicolas
Platforms using ACPI firmware are becoming increasingly interesting to embedded developers. This presentation will demonstrate the new features in the ACPI 5.1 specification which make it possible for ACPI to transparently represent devices using existing device-tree bindings, and for Linux to use existing device drivers which should automatically work for both ACPI and device-tree.
David Woodhouse, Intel
This document proposes a standardized interface for collaborating on power management across operating systems on ARM devices. It suggests defining a set of APIs to handle powering down and up CPUs for idle states, hot plug, secondary boot, and CPU migration. These APIs would take parameters like the affinity level, resume address, and context ID to enable saving and restoring state across OS layers. Implementing this interface with calls like IdlePowerDown, CPUAdd, CPURemove, CPUSwitchIn, and CPUSwitchOut could facilitate collaboration between Linux, hypervisors, and trusted operating systems on power management.
Loading Multiple Versions of an ASDF System in the Same Lisp ImageVsevolod Dyomkin
This document outlines an approach to loading multiple versions of an ASDF system in the same Lisp image by resolving name conflicts between dependencies. It discusses the "dependency hell" problem, solutions used in other languages, and limitations of the Common Lisp package and ASDF systems. The proposed algorithm assembles a dependency tree, determines a load order while resolving conflicts, loads systems one by one while renaming packages as needed, and caches already loaded systems. This approach allows loading a system's components without reloading dependencies but has limitations such as not handling implicit transitive dependencies or interactive workflows. The goal is to build on ASDF to create a more complete and reusable "ASDFx" system loading framework.
Extracting Linux kernel feature model changes with FMDiff NicoDintzner
Presentation of the research work of Nicolas Dintzner, Arie van Deursen and Martin Pinzger on the evolution of feature models. This presentation was given at the VaMoS 2014 workshop.
The e820 trap of Linux kernel hibernationjoeylikernel
The document discusses the e820 trap that can occur during Linux kernel hibernation (suspend to disk) restoration. It describes how the BIOS memory map reported via e820 can shift between boot and resume, causing pages saved in the hibernation image to be located in reserved memory regions upon restoration. This leads to page faults and failure to resume. Other challenges discussed include EFI memory mapping issues, memory size mismatches, and identification of non-saveable regions.
PCI Express support has been added to Qemu to allow for emulation of PCI Express devices and functionality like hotplug. This includes a Q35 chipset emulator, PCI Express port emulators, and the ability to inject errors into guest systems. Further work is still needed to integrate these features with Xen for full PCI Express and hotplug support virtualization.
This document discusses configuring and troubleshooting display devices, I/O devices, and ACPI in Windows XP. It covers setting up multiple displays, ensuring secondary displays meet requirements, and addressing common multiple display issues. Troubleshooting tips are provided for displays, input devices like keyboards and mice, as well as printers, scanners and other peripherals. The document also discusses Windows XP's support for ACPI which allows the operating system to control power consumption in computers.
Comp tia flashcards set 1 (15 cards) acpi cmosSue Long Smith
This document contains flashcards defining various computer-related terms starting with letters A through C, including definitions for ACPI, ADSL, AGP, AMD, AMR, APIPA, ARP, BIOS, BRI, BTX, CD-ROM, CD-RW, CDFS, CGA, and CMOS. Each term is defined in 1-2 sentences explaining its purpose or function within computing systems.
Kernel Recipes 2015: Representing device-tree peripherals in ACPIAnne Nicolas
Platforms using ACPI firmware are becoming increasingly interesting to embedded developers. This presentation will demonstrate the new features in the ACPI 5.1 specification which make it possible for ACPI to transparently represent devices using existing device-tree bindings, and for Linux to use existing device drivers which should automatically work for both ACPI and device-tree.
David Woodhouse, Intel
This document proposes a standardized interface for collaborating on power management across operating systems on ARM devices. It suggests defining a set of APIs to handle powering down and up CPUs for idle states, hot plug, secondary boot, and CPU migration. These APIs would take parameters like the affinity level, resume address, and context ID to enable saving and restoring state across OS layers. Implementing this interface with calls like IdlePowerDown, CPUAdd, CPURemove, CPUSwitchIn, and CPUSwitchOut could facilitate collaboration between Linux, hypervisors, and trusted operating systems on power management.
Note - (EDK2) Acpi Tables Compile and Installboyw165
This document summarizes the process for compiling and installing ACPI tables. It describes three main components: 1) ACPI table files (.aml and .aslc/.act) that are compiled, 2) A DXE driver that finds the ACPI tables and installs them to memory, and 3) A DXE driver that provides the ACPI table and SDT protocols. The document also provides examples of different ACPI table file types and describes the drivers involved in compiling, installing, and exposing the ACPI tables.
BIOS, Linux and Firmware Test Suite in-betweenAlex Hung
The document discusses BIOS, UEFI, ACPI and the Firmware Test Suite (FWTS). It defines BIOS as the Basic Input/Output System that handles hardware initialization and boot processes. UEFI intends to replace BIOS with standardized boot services. ACPI establishes interfaces for hardware configuration and power management. FWTS is a Linux tool that automates firmware testing through a suite of tests for aspects like ACPI, UEFI and power management.
Las16 200 - firmware summit - ras what is it- why do we need itLinaro
Title: RAS What is it? Why do we need it?
A 101 style introduction to RAS, its purpose and how we use it on ARM64. Covering current status of implementation in ASWG specs and Linux kernel. Plans for future features that are essential for ARM64. Followed by a discussion period.
Speaker: Yazen Ghannam, Fu Wei
The document provides an overview of the initialization phase of the Linux kernel. It discusses how the kernel enables paging to transition from physical to virtual memory addresses. It then describes the various initialization functions that are called by start_kernel to initialize kernel features and architecture-specific code. Some key initialization tasks discussed include creating an identity page table, clearing BSS, and reserving BIOS memory.
The document discusses different approaches used by operating systems to detect hardware components during system boot. It describes methods like hardcoding details, using static configuration, device trees, and dynamic configuration via ACPI and bus-based detection. ACPI is covered in depth, including its components, tables, and complexity. Platform and PCI devices are also briefly explained.
High Performance Storage Devices in the Linux KernelKernel TLV
Agenda:
In this talk we will present the Linux kernel storage layers and dive into blk-mq, a scalable, parallel block layer for high performance block devices, and how it is used to unleash the performance of NVMe, flash and beyond.
Speaker:
Evgeny Budilovsky, Kernel Developer at E8 Storage
https://www.linkedin.com/company/e8-storage
The document provides an overview of the initialization process in the Linux kernel from start_kernel to rest_init. It lists the functions called during this process organized by category including functions for initialization of multiprocessor support (SMP), memory management (MM), scheduling, timers, interrupts, and architecture specific setup. The setup_arch section focuses on x86 architecture specific initialization functions such as reserving memory regions, parsing boot parameters, initializing memory mapping and MTRRs.
This document provides an overview of UEFI and HP's transition to UEFI for ProLiant servers. Some key points:
- UEFI was created by HP and Intel in the late 1990s to overcome BIOS limitations and support new technologies like large disks and 64-bit processors. It has since become an industry standard supported by all major operating systems.
- HP drove adoption of UEFI and helped establish the UEFI Forum to develop and promote the standard. ProLiant Gen9 servers were the first to default to UEFI boot, moving HP to UEFI Class 2 compliance. Future servers aim for Class 3 (UEFI-only).
- UEFI provides advantages over legacy BIOS like large
The document discusses designing a power-aware operating system. It describes reducing power consumption at both the hardware and software levels. The key areas covered are power consumption scenarios for devices like memory, Linux power management standards like ACPI, implementing ACPI in Linux, tools for power monitoring, and a proposed project to discover ACPI devices and read status information like battery levels and thermal data.
This document discusses hibernation and suspend states in Linux 2.6.29. It covers the ACPI specification which defines system power states like S1, S3, S4 and device power states like D0, D1, D2, D3. It explains the hibernation and resume algorithms, and how tasks are frozen and thawed. It also describes the sysfs interface for controlling hibernation and resume, including writing to /sys/power/state to transition power states and /sys/power/disk to select operating modes.
The document discusses power management in Linux and its usage in embedded systems. It provides an overview of power management on PCs including Advanced Power Management (APM) and Advanced Configuration and Power Interface (ACPI). It describes the different ACPI system power states like S0, S1-S4, and S5. It also discusses suspend to RAM (STR) and suspend to disk (hibernation) states in Linux and how STR works by saving the system context to memory and powering down devices to save power before resuming.
The respective talk was held by Oleksandr Shevchenko (Senior Engineering Consultant, GlobalLogic) at GlobalLogic Lviv Embedded TechTalk #2 on May 23, 2018.
Oleksandr presentation is about features of software architecture, which provides parallel work of Linux and operating system real-time on different cores of a single processor. The talk is also about the Linux mechanism, which allows to connect the processor cores after the boot process has finished, the so-called "CPU Hotplug".
The document discusses stack-based buffer overflows in C programs. It explains that processes have a text, data, and stack region in memory. The stack grows downwards and contains stack frames for function calls, including parameters, local variables with negative offsets from the frame pointer, and a return address. Buffer overflows can corrupt the return address on the stack and allow code to be executed arbitrarily when the function returns.
This presentation is about such well-known vulnerabilities as Meltdown and Spectre and the way they use imperfections of modern processors on an architectural level. In this regard, ARM architecture, which is now a standard in embedded system, is discussed.
The talk was delivered by Andrii Lukin (Senior Software Engineer, Consultant, GlobalLogic) at GlobalLogic Embedded Career Day #2 on February 10, 2018.
More about GlobalLogic Embedded Career Day #2: https://www.globallogic.com/ua/events/globallogic-kyiv-embedded-career-day-2-materials
The document provides information about SCSI (Small Computer System Interface) domains, components, protocols, and concepts. It describes the SCSI bus model including initiators, targets, logical units, and phases like arbitration, selection, command, data transfer, status, and message. It explains SCSI commands, CDBs, status values, sense data, and error recovery. It also covers logical unit resets, unit attention conditions, contingent allegiance, auto contingent allegiance, and task management functions. The document is a technical reference for SCSI specifications, protocols, and error handling.
The document discusses Cassandra's data model and how it replaces HDFS services. It describes:
1) Two column families - "inode" and "sblocks" - that replace the HDFS NameNode and DataNode services respectively, with "inode" storing metadata and "sblocks" storing file blocks.
2) CFS reads involve reading the "inode" info to find the block and subblock, then directly accessing the data from the Cassandra SSTable file on the node where it is stored.
3) Keyspaces are containers for column families in Cassandra, and the NetworkTopologyStrategy places replicas across data centers to enable local reads and survive failures.
This document provides an introduction to protected mode memory management in x86 microprocessors. It discusses key concepts like memory segmentation, privilege levels, and descriptor tables which the processor uses to implement protection between processes and enable virtual memory. Segmentation allows logically separating code, data, and stack segments to prevent processes from interfering with each other's memory.
The document discusses the CAP theorem and related concepts like PACELC, ACID, and BASE. It analyzes how different database systems like PostgreSQL, MongoDB, and a hybrid PostgreSQL/Salesforce/Heroku Connect system fit within these models. While CAP classifications can be imprecise, the key aspects to understand are the consistency, availability, and partition tolerance tradeoffs that distributed systems must make.
Note - (EDK2) Acpi Tables Compile and Installboyw165
This document summarizes the process for compiling and installing ACPI tables. It describes three main components: 1) ACPI table files (.aml and .aslc/.act) that are compiled, 2) A DXE driver that finds the ACPI tables and installs them to memory, and 3) A DXE driver that provides the ACPI table and SDT protocols. The document also provides examples of different ACPI table file types and describes the drivers involved in compiling, installing, and exposing the ACPI tables.
BIOS, Linux and Firmware Test Suite in-betweenAlex Hung
The document discusses BIOS, UEFI, ACPI and the Firmware Test Suite (FWTS). It defines BIOS as the Basic Input/Output System that handles hardware initialization and boot processes. UEFI intends to replace BIOS with standardized boot services. ACPI establishes interfaces for hardware configuration and power management. FWTS is a Linux tool that automates firmware testing through a suite of tests for aspects like ACPI, UEFI and power management.
Las16 200 - firmware summit - ras what is it- why do we need itLinaro
Title: RAS What is it? Why do we need it?
A 101 style introduction to RAS, its purpose and how we use it on ARM64. Covering current status of implementation in ASWG specs and Linux kernel. Plans for future features that are essential for ARM64. Followed by a discussion period.
Speaker: Yazen Ghannam, Fu Wei
The document provides an overview of the initialization phase of the Linux kernel. It discusses how the kernel enables paging to transition from physical to virtual memory addresses. It then describes the various initialization functions that are called by start_kernel to initialize kernel features and architecture-specific code. Some key initialization tasks discussed include creating an identity page table, clearing BSS, and reserving BIOS memory.
The document discusses different approaches used by operating systems to detect hardware components during system boot. It describes methods like hardcoding details, using static configuration, device trees, and dynamic configuration via ACPI and bus-based detection. ACPI is covered in depth, including its components, tables, and complexity. Platform and PCI devices are also briefly explained.
High Performance Storage Devices in the Linux KernelKernel TLV
Agenda:
In this talk we will present the Linux kernel storage layers and dive into blk-mq, a scalable, parallel block layer for high performance block devices, and how it is used to unleash the performance of NVMe, flash and beyond.
Speaker:
Evgeny Budilovsky, Kernel Developer at E8 Storage
https://www.linkedin.com/company/e8-storage
The document provides an overview of the initialization process in the Linux kernel from start_kernel to rest_init. It lists the functions called during this process organized by category including functions for initialization of multiprocessor support (SMP), memory management (MM), scheduling, timers, interrupts, and architecture specific setup. The setup_arch section focuses on x86 architecture specific initialization functions such as reserving memory regions, parsing boot parameters, initializing memory mapping and MTRRs.
This document provides an overview of UEFI and HP's transition to UEFI for ProLiant servers. Some key points:
- UEFI was created by HP and Intel in the late 1990s to overcome BIOS limitations and support new technologies like large disks and 64-bit processors. It has since become an industry standard supported by all major operating systems.
- HP drove adoption of UEFI and helped establish the UEFI Forum to develop and promote the standard. ProLiant Gen9 servers were the first to default to UEFI boot, moving HP to UEFI Class 2 compliance. Future servers aim for Class 3 (UEFI-only).
- UEFI provides advantages over legacy BIOS like large
The document discusses designing a power-aware operating system. It describes reducing power consumption at both the hardware and software levels. The key areas covered are power consumption scenarios for devices like memory, Linux power management standards like ACPI, implementing ACPI in Linux, tools for power monitoring, and a proposed project to discover ACPI devices and read status information like battery levels and thermal data.
This document discusses hibernation and suspend states in Linux 2.6.29. It covers the ACPI specification which defines system power states like S1, S3, S4 and device power states like D0, D1, D2, D3. It explains the hibernation and resume algorithms, and how tasks are frozen and thawed. It also describes the sysfs interface for controlling hibernation and resume, including writing to /sys/power/state to transition power states and /sys/power/disk to select operating modes.
The document discusses power management in Linux and its usage in embedded systems. It provides an overview of power management on PCs including Advanced Power Management (APM) and Advanced Configuration and Power Interface (ACPI). It describes the different ACPI system power states like S0, S1-S4, and S5. It also discusses suspend to RAM (STR) and suspend to disk (hibernation) states in Linux and how STR works by saving the system context to memory and powering down devices to save power before resuming.
The respective talk was held by Oleksandr Shevchenko (Senior Engineering Consultant, GlobalLogic) at GlobalLogic Lviv Embedded TechTalk #2 on May 23, 2018.
Oleksandr presentation is about features of software architecture, which provides parallel work of Linux and operating system real-time on different cores of a single processor. The talk is also about the Linux mechanism, which allows to connect the processor cores after the boot process has finished, the so-called "CPU Hotplug".
The document discusses stack-based buffer overflows in C programs. It explains that processes have a text, data, and stack region in memory. The stack grows downwards and contains stack frames for function calls, including parameters, local variables with negative offsets from the frame pointer, and a return address. Buffer overflows can corrupt the return address on the stack and allow code to be executed arbitrarily when the function returns.
This presentation is about such well-known vulnerabilities as Meltdown and Spectre and the way they use imperfections of modern processors on an architectural level. In this regard, ARM architecture, which is now a standard in embedded system, is discussed.
The talk was delivered by Andrii Lukin (Senior Software Engineer, Consultant, GlobalLogic) at GlobalLogic Embedded Career Day #2 on February 10, 2018.
More about GlobalLogic Embedded Career Day #2: https://www.globallogic.com/ua/events/globallogic-kyiv-embedded-career-day-2-materials
The document provides information about SCSI (Small Computer System Interface) domains, components, protocols, and concepts. It describes the SCSI bus model including initiators, targets, logical units, and phases like arbitration, selection, command, data transfer, status, and message. It explains SCSI commands, CDBs, status values, sense data, and error recovery. It also covers logical unit resets, unit attention conditions, contingent allegiance, auto contingent allegiance, and task management functions. The document is a technical reference for SCSI specifications, protocols, and error handling.
The document discusses Cassandra's data model and how it replaces HDFS services. It describes:
1) Two column families - "inode" and "sblocks" - that replace the HDFS NameNode and DataNode services respectively, with "inode" storing metadata and "sblocks" storing file blocks.
2) CFS reads involve reading the "inode" info to find the block and subblock, then directly accessing the data from the Cassandra SSTable file on the node where it is stored.
3) Keyspaces are containers for column families in Cassandra, and the NetworkTopologyStrategy places replicas across data centers to enable local reads and survive failures.
This document provides an introduction to protected mode memory management in x86 microprocessors. It discusses key concepts like memory segmentation, privilege levels, and descriptor tables which the processor uses to implement protection between processes and enable virtual memory. Segmentation allows logically separating code, data, and stack segments to prevent processes from interfering with each other's memory.
The document discusses the CAP theorem and related concepts like PACELC, ACID, and BASE. It analyzes how different database systems like PostgreSQL, MongoDB, and a hybrid PostgreSQL/Salesforce/Heroku Connect system fit within these models. While CAP classifications can be imprecise, the key aspects to understand are the consistency, availability, and partition tolerance tradeoffs that distributed systems must make.
The document discusses various topics related to Juniper networking devices including:
1. It describes the control and forwarding plane synchronization between the Routing Engine (RE) and Packet Forwarding Engine (PFE) using Ethernet links.
2. It compares the differences between the M7i and M10i platforms, specifically regarding redundant RE support and built-in adaptive services.
3. It provides examples of commands for viewing logs, configuration, interfaces and other operational aspects of Juniper devices.
- Apache Cassandra is a linearly scalable and fault tolerant NoSQL database that increases throughput linearly with additional machines
- It is an AP system that is eventually consistent according to the CAP theorem, sacrificing consistency in favor of availability and partition tolerance
- Cassandra uses replication and consistency levels to control fault tolerance at the server and client levels respectively
- Its data model and use of SSTables allows for fast writes and queries along clustering columns
High availability clusters use redundant systems and components to minimize downtime from failures. An SRX cluster provides redundancy by grouping two SRX devices to act as a single device. Key components include the control plane, data plane, and redundancy groups. The control plane ensures only one configuration between nodes. Redundancy groups contain objects that fail over together if monitoring detects failures.
This document presents benchmarks to analyze the memory subsystem performance of multicore processors from AMD and Intel. The benchmarks measure latency and bandwidth for different cache coherence states and locations in the memory hierarchy. Testing was done on dual-socket systems using AMD Opteron 2300 (Shanghai) and Intel Xeon 5500 (Nehalem-EP) quad-core processors. Results show significant performance differences driven by each processor's distinct cache architecture and coherence protocol implementations.
Chassis clustering provides redundancy by grouping two SRX devices into a cluster. The cluster represents the devices as a single device. The basic chassis cluster consists of one active device providing services and one passive device maintaining state for failover. To create a chassis cluster, two SRX devices must be physically connected via control and fabric links, then clustering must be enabled by assigning cluster IDs and node IDs to each device.
This document provides an overview of the Intel x86 architecture, including its registers, instructions, memory management, interrupts and exceptions, task management, and input/output capabilities. It describes the basic execution environment including memory management registers and control registers. It explains the operation modes of protected mode and real mode, and the memory models. It also summarizes the general purpose instructions, system instructions, privilege levels, basic program execution registers, and memory addressing in the x86 architecture.
The ARM11 architecture uses a RISC design with 32-bit ARM and 16-bit Thumb instruction sets. It has a pipeline with stages for instruction fetch, decode, register access, shift, ALU operations, and write back. The ARM11 uses branch prediction including a branch target address cache and static prediction rules. It has a memory hierarchy including separate instruction and data caches, a TLB for virtual to physical address translation, and an optional L2 cache. Vector floating-point operations can be performed in parallel by a coprocessor.
Deep Learning Neural Network Acceleration at the Edge - Andrea GalloLinaro
Short
The growing amount of data captured by sensors and the real time constraints imply that not only big data analytics but also Machine Learning (ML) inference shall be executed at the edge. The multiple options for neural network acceleration in Arm-based platforms provide an unprecedented opportunity for new intelligent devices. It also raises the risk of fragmentation and duplication of efforts when multiple frameworks shall support multiple accelerators.
Andrea Gallo, Linaro VP of Segment Groups, will summarise the existing NN frameworks, accelerator solutions, and will describe the efforts underway in the Arm ecosystem.
Abstract
The dramatically growing amount of data captured by sensors and the ever more stringent requirements for latency and real time constraints are paving the way for edge computing, and this implies that not only big data analytics but also Machine Learning (ML) inference shall be executed at the edge. The multiple options for neural network acceleration in recent Arm-based platforms provides an unprecedented opportunity for new intelligent devices with ML inference. It also raises the risk of fragmentation and duplication of efforts when multiple frameworks shall support multiple accelerators.
Andrea Gallo, Linaro VP of Segment Groups, will summarise the existing NN frameworks, model description formats, accelerator solutions, low cost development boards and will describe the efforts underway to identify the best technologies to improve the consolidation and enable the competitive innovative advantage from all vendors.
Audience
The session will be useful for executives to engineers. Executives will gain a deeper understanding of the issues and opportunities. Engineers at NN acceleration IP design houses will take away ideas for how to collaborate in the open source community on their area of expertise, how to evaluate the performance and accelerate multiple NN frameworks without modifying them for each new IP, whether it be targeting edge computing gateways, smart devices or simple microcontrollers.
Benefits to the Ecosystem
The AI deep learning neural network ecosystem is starting just now and it has similar implications with open source as GPU and video accelerators had in the early days with user space drivers, binary blobs, proprietary APIs and all possible ways to protect their IPs. The session will outline a proposal for a collaborative ecosystem effort to create a common framework to manage multiple NN accelerators while at the same time avoiding to modify deep learning frameworks with multiple forks.
Arm Architecture HPC Workshop Santa Clara 2018 - Kanta VekariaLinaro
The document summarizes an Arm Architecture HPC Workshop held by Linaro. It discusses Linaro's work in open source software development for Arm architecture, including efforts in HPC, tools, libraries, and machine learning. It also mentions Linaro's Developer Cloud which provides access to Arm hardware for developers.
Huawei’s requirements for the ARM based HPC solution readiness - Joshua MoraLinaro
Huawei outlines requirements for developing a competitive ARM-based HPC solution. They plan a two-phase strategy using existing Hi1616 platforms followed by more powerful Hi1620 platforms. Requirements include high-performance CPUs, optimized software stack, support for applications and ISVs, and cloud deployment. Huawei aims to demonstrate ARM's value in HPC by 2018-2020 through partnerships and turnkey solutions.
Bud17 113: distribution ci using qemu and open qaLinaro
“Delivering a well working distribution is hard. There are a lot of different hardware platforms that need to be verified and the software stack is in a big flux during development phases. In rolling releases, this gets even worse, as nothing ever stands still. The only sane answer to that problem are working Continuous Integration tests. The SUSE way to check whether any change breaks normal distribution behavior is OpenQA. Using OpenQA we can automatically run tests that hard working QA people did manually in the old days. That way we have fast enough turnaround times to find and reject breaking changes This session shows how OpenQA works, what pitfalls we had to make ARM work with OpenQA and what we’re doing to improve it for ARM specific use cases.”
OpenHPC Automation with Ansible - Renato Golin - Linaro Arm HPC Workshop 2018Linaro
Speaker: Renato Golin
Speaker Bio:
He started programming in the late 80's in C for PCs after a few years playing with 8-bit computers, but he only started programming professionally in the late 90's during the .com bubble. After many years working on Internet's back-end, he moved to UK and worked a few years on bioinformatics at EBI before joining ARM, where he worked on the DS-5 debugger and on the EDG-to-LLVM bridge, where he became the LLVM Tech Lead. Recently, he worked with large clusters and big data at HPCC before moving to Linaro.
Talk Title: OpenHPC Automation with Ansible
Talk Abstract: "In order to test OpenHPC packages and components and to use it as a
platform to benchmark HPC applications, Linaro is developing an automated deployment strategy, using Ansible, Mr-Provisioner and Jenkins, to install the
OS, OpenHPC and prepare the environment on varied architectures (Arm, x86). This work is meant to replace the existing ageing Bash-based recipes upstream while still keeping the documents intact. Our aim is to make it easier to vary hardware configuration, allow for different provisioning techniques and mix internal infrastructure logic to different labs, while still using the same recipes. We hope this will help more people use OpenHPC with a better out-of-the-box experience and with more robust results"
HPC network stack on ARM - Linaro HPC Workshop 2018Linaro
Speaker: Pavel Shamis
Company: Arm
Speaker Bio:
"Pavel is a Principal Research Engineer at ARM with over 16 years of experience in development HPC solutions. His work is focused on co-design software and hardware building blocks for high-performance interconnect technologies, development communication middleware and novel programming models. Prior to joining ARM, he spent five years at Oak Ridge National Laboratory (ORNL) as a research scientist at Computer Science and Math Division (CSMD). In this role, Pavel was responsible for research and development multiple projects in high-performance communication domain including: Collective Communication Offload (CORE-Direct & Cheetah), OpenSHMEM, and OpenUCX. Before joining ORNL, Pavel spent ten years at Mellanox Technologies, where he led Mellanox HPC team and was one of the key driver in enablement Mellanox HPC software stack, including OFA software stack, OpenMPI, MVAPICH, OpenSHMEM, and other.
Pavel is a recipient of prestigious R&D100 award for his contribution in development of the CORE-Direct collective offload technology and he published in excess of 20 research papers.
"
Talk Title: HPC network stack on ARM
Talk Abstract:
Applications, programming languages, and libraries that leverage sophisticated network hardware capabilities have a natural advantage when used in today¹s and tomorrow's high-performance and data center computer environments. Modern RDMA based network interconnects provides incredibly rich functionality (RDMA, Atomics, OS-bypass, etc.) that enable low-latency and high-bandwidth communication services. The functionality is supported by a variety of interconnect technologies such as InfiniBand, RoCE, iWARP, Intel OPA, Cray¹s Aries/Gemini, and others. Over the last decade, the HPC community has developed variety user/kernel level protocols and libraries that enable a variety of high-performance applications over RDMA interconnects including MPI, SHMEM, UPC, etc. With the emerging availability HPC solutions based on ARM CPU architecture it is important to understand how ARM integrates with the RDMA hardware and HPC network software stack. In this talk, we will overview ARM architecture and system software stack, including MPI runtimes, OpenSHMEM, and OpenUCX.
It just keeps getting better - SUSE enablement for Arm - Linaro HPC Workshop ...Linaro
Speaker: Jay Kruemcke
Speaker Company: SUSE
Bio:
"Jay is responsible for the SUSE Linux server products for High Performance Computing, 64-bit ARM systems, and SUSE Linux for IBM Power servers.
Jay has built an extensive career in product management including using social media for client collaboration, product positioning, driving future product directions, and evangelizing the capabilities and future directions for dozens of enterprise products.
"
Talk Title: It just keeps getting better - SUSE enablement for Arm
Talk Abstract:
SUSE has been delivering commercial Linux support for Arm based servers since 2016. Initially the focus was on high end servers for HPC and Ceph based software defined storage. But we have enabled a number of other Arm SoCs and are even supporting the Raspberry Pi. This session will cover the SUSE products that are available for the Arm platform and view to the future.
Intelligent Interconnect Architecture to Enable Next Generation HPC - Linaro ...Linaro
Speakers: Gilad Shainer and Scot Schultz
Company: Mellanox Technologies
Talk Title: Intelligent Interconnect Architecture to Enable Next
Generation HPC
Talk Abstract:
The latest revolution in HPC interconnect architecture is the development of In-Network Computing, a technology that enables handling and accelerating application workloads at the network level. By placing data-related algorithms on an intelligent network, we can overcome the new performance bottlenecks and improve the data center and applications performance. The combination of In-Network Computing and ARM based processors offer a rich set of capabilities and opportunities to build the next generation of HPC platforms.
Gilad Shainer Bio:
Gilad Shainer has served as Mellanox's vice president of marketing since March 2013. Previously, Mr. Shainer was Mellanox's vice president of marketing development from March 2012 to March 2013. Mr. Shainer joined Mellanox in 2001 as a design engineer and later served in senior marketing management roles between July 2005 and February 2012. Mr. Shainer holds several patents in the field of high-speed networking and contributed to the PCI-SIG PCI-X and PCIe specifications. Gilad Shainer holds a MSc degree (2001, Cum Laude) and a BSc degree (1998, Cum Laude) in Electrical Engineering from the Technion Institute of Technology in Israel.
Scot Schultz Bio:
Scot Schultz is a HPC technology specialist with broad knowledge in operating systems, high speed interconnects and processor technologies. Joining the Mellanox team in 2013, Schultz is 30-year veteran of the computing industry. Prior to joining Mellanox, he spent the past 17 years at AMD in various engineering and leadership roles in the area of high performance computing. Scot has also been instrumental with the growth and development of various industry organizations including the Open Fabrics Alliance, and continues to serve as a founding board-member of the OpenPOWER Foundation and Director of Educational Outreach and founding member of the HPC-AI Advisory Council.
Yutaka Ishikawa - Post-K and Arm HPC Ecosystem - Linaro Arm HPC Workshop Sant...Linaro
Yutaka Ishikawa - Post-K and Arm HPC Ecosystem - Linaro Arm HPC Workshop Santa Clara 2018
Bio: "Yutaka Ishikawa is the project leader of developing the post K
supercomputer. From 1987 to 2001, he was a member of AIST (former
Electrotechnical Laboratory), METI. From 1993 to 2001, he was the
chief of Parallel and Distributed System Software Laboratory at Real
World Computing Partnership. He led development of cluster system
software called SCore, which was used in several large PC cluster
systems around 2004. From 2002 to 2014, he was a professor at the
University Tokyo. He led a project to design a commodity-based
supercomputer called T2K open supercomputer. As a result, three
universities, Tsukuba, Tokyo, and Kyoto, obtained each supercomputer
based on the specification in 2008. He was also involved with the
design of the Oakleaf-PACS, the successor of T2K supercomputer in both
Tsukuba and Tokyo, whose peak performance is 25PF."
Session Title: Post-K and Arm HPC Ecosystem
Session Description:
"Post-K, a flagship supercomputer in Japan, is being developed by Riken
and Fujitsu. It will be the first supercomputer with Armv8-A+SVE.
This talk will give an overview of Post-K and how RIKEN and Fujitsu
are currently working on software stack for an Arm architecture."
Andrew J Younge - Vanguard Astra - Petascale Arm Platform for U.S. DOE/ASC Su...Linaro
Event: Arm Architecture HPC Workshop by Linaro and HiSilicon
Location: Santa Clara, CA
Speaker: Andrew J Younge
Talk Title: Vanguard Astra - Petascale Arm Platform for U.S. DOE/ASC Supercomputing
Talk Desc: The Vanguard program looks to expand the potential technology choices for leadership-class High Performance Computing (HPC) platforms, not only for the National Nuclear Security Administration (NNSA) but for the Department of Energy (DOE) and wider HPC community. Specifically, there is a need to expand the supercomputing ecosystem by investing and developing emerging, yet-to-be-proven technologies and address both hardware and software challenges together, as well as to prove-out the viability of such novel platforms for production HPC workloads.
The first deployment of the Vanguard program will be Astra, a prototype Petascale Arm supercomputer to be sited at Sandia National Laboratories during 2018. This talk will focus on the arthictecural details of Astra and the significant investments being made towards the maturing the Arm software ecosystem. Furthermore, we will share initial performance results based on our pre-general availability testbed system and outline several planned research activities for the machine.
Bio: Andrew Younge is a R&D Computer Scientist at Sandia National Laboratories with the Scalable System Software group. His research interests include Cloud Computing, Virtualization, Distributed Systems, and energy efficient computing. Andrew has a Ph.D in Computer Science from Indiana University, where he was the Persistent Systems fellow and a member of the FutureGrid project, an NSF-funded experimental cyberinfrastructure test-bed. Over the years, Andrew has held visiting positions at the MITRE Corporation, the University of Southern California / Information Sciences Institute, and the University of Maryland, College Park. He received his Bachelors and Masters of Science from the Computer Science Department at Rochester Institute of Technology (RIT) in 2008 and 2010, respectively.
HKG18-501 - EAS on Common Kernel 4.14 and getting (much) closer to mainlineLinaro
Session ID: HKG18-501
Session Name: HKG18-501 - EAS on Common Kernel 4.14 and getting (much) closer to mainline
Speaker: Chris Redpath
Track: Mobile, Kernel
★ Session Summary ★
This session will introduce the changes to EAS planned for 4.14 kernel, and how Arm hopes that EAS will develop in future. EAS has already evolved from an Arm/Linaro joint project to involving a much wider community of SoC vendors, Google and interested device manufacturers. We will highlight the product-specific pieces remaining in the Android Common Kernel EAS implementation, and our plans to provide an upstreaming plan for each product feature. In particular, the new 'simplified energy model' is designed to provide mainline-friendliness and comparable performance using a simple DT expression of cpu power/performance.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/hkg18/hkg18-501/
Presentation: http://connect.linaro.org.s3.amazonaws.com/hkg18/presentations/hkg18-501.pdf
Video: http://connect.linaro.org.s3.amazonaws.com/hkg18/videos/hkg18-501.mp4
---------------------------------------------------
★ Event Details ★
Linaro Connect Hong Kong 2018 (HKG18)
19-23 March 2018
Regal Airport Hotel Hong Kong
---------------------------------------------------
Keyword: Mobile, Kernel
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961
HKG18-501 - EAS on Common Kernel 4.14 and getting (much) closer to mainlineLinaro
"Session ID: HKG18-501
Session Name: HKG18-501 - EAS on Common Kernel 4.14 and getting (much) closer to mainline
Speaker: Chris Redpath
Track: Mobile, Kernel
★ Session Summary ★
This session will introduce the changes to EAS planned for 4.14 kernel, and how Arm hopes that EAS will develop in future. EAS has already evolved from an Arm/Linaro joint project to involving a much wider community of SoC vendors, Google and interested device manufacturers. We will highlight the product-specific pieces remaining in the Android Common Kernel EAS implementation, and our plans to provide an upstreaming plan for each product feature. In particular, the new 'simplified energy model' is designed to provide mainline-friendliness and comparable performance using a simple DT expression of cpu power/performance.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/hkg18/hkg18-501/
Presentation: http://connect.linaro.org.s3.amazonaws.com/hkg18/presentations/hkg18-501.pdf
Video: http://connect.linaro.org.s3.amazonaws.com/hkg18/videos/hkg18-501.mp4
---------------------------------------------------
★ Event Details ★
Linaro Connect Hong Kong 2018 (HKG18)
19-23 March 2018
Regal Airport Hotel Hong Kong
---------------------------------------------------
Keyword: Mobile, Kernel
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961"
HKG18-315 - Why the ecosystem is a wonderful thing, warts and allLinaro
"Session ID: HKG18-315
Session Name: HKG18-315 - Why the ecosystem is a wonderful thing warts and all
Speaker: Andrew Wafaa
Track: Ecosystem Day
★ Session Summary ★
The Arm ecosystem is a vibrant place, but it's not always smooth sailing. This presentation will go through the highs and lows of getting the ecosystem fully Arm enabled.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/hkg18/hkg18-315/
Presentation: http://connect.linaro.org.s3.amazonaws.com/hkg18/presentations/hkg18-315.pdf
Video: http://connect.linaro.org.s3.amazonaws.com/hkg18/videos/hkg18-315.mp4
---------------------------------------------------
★ Event Details ★
Linaro Connect Hong Kong 2018 (HKG18)
19-23 March 2018
Regal Airport Hotel Hong Kong
---------------------------------------------------
Keyword: Ecosystem Day
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961"
HKG18- 115 - Partitioning ARM Systems with the Jailhouse HypervisorLinaro
"Session ID: HKG18-115
Session Name: HKG18-115 - Partitioning ARM Systems with the Jailhouse Hypervisor
Speaker: Jan Kiszka
Track: Security
★ Session Summary ★
The open source hypervisor Jailhouse provides hard partitioning of multicore systems to co-locate multiple Linux or RTOS instances side by side. It aims at low complexity and minimal footprint to achieve deterministic behavior and enable certifications according to safety or security standards. In this session, we would like to look at the ARM-specific status of Jailhouse and discuss applications, to-dos and possible collaborations around it with the ARM community. The session is intended to be half presentation, half Q&A / discussion.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/hkg18/hkg18-115/
Presentation: http://connect.linaro.org.s3.amazonaws.com/hkg18/presentations/hkg18-115.pdf
Video: http://connect.linaro.org.s3.amazonaws.com/hkg18/videos/hkg18-115.mp4
---------------------------------------------------
★ Event Details ★
Linaro Connect Hong Kong 2018 (HKG18)
19-23 March 2018
Regal Airport Hotel Hong Kong
---------------------------------------------------
Keyword: Security
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961"
"Session ID: HKG18-TR08
Session Name: HKG18-TR08 - Upstreaming SVE in QEMU
Speaker: Alex Bennée,Richard Henderson
Track: Enterprise
★ Session Summary ★
ARM's Scalable Vector Extensions is an innovative solution to processing highly data parallel workloads. While several out-of-tree attempts at implementing SVE support for QEMU existed, we took a fundamentally different approach to solving key challenges and therefore pursued a from-scratch QEMU SVE implementation in Linaro. Our strategic choice was driven by several factors. First as an ""upstream first"" organisation we were focused on a solution that would be readily accepted by the upstream project. This entailed doing our development in the open on the project mailing lists where early feedback and community consensus can be reached.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/hkg18/hkg18-tr08/
Presentation: http://connect.linaro.org.s3.amazonaws.com/hkg18/presentations/hkg18-tr08.pdf
Video: http://connect.linaro.org.s3.amazonaws.com/hkg18/videos/hkg18-tr08.mp4
---------------------------------------------------
★ Event Details ★
Linaro Connect Hong Kong 2018 (HKG18)
19-23 March 2018
Regal Airport Hotel Hong Kong
---------------------------------------------------
Keyword: Enterprise
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961"
HKG18-113- Secure Data Path work with i.MX8MLinaro
"Session ID: HKG18-113
Session Name: HKG18-113 - Secure Data Path work with i.MX8M
Speaker: Cyrille Fleury
Track: Digital Home
★ Session Summary ★
NXP presentation on Secure Data Path work with i.MX8M Soc. Demonstrate 4K PlayReady playback with Android 8.1 running on i.MX8M. Focus on security (MS SL3000 and Widevine level 1)
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/hkg18/hkg18-113/
Presentation: http://connect.linaro.org.s3.amazonaws.com/hkg18/presentations/hkg18-113.pdf
Video: http://connect.linaro.org.s3.amazonaws.com/hkg18/videos/hkg18-113.mp4
---------------------------------------------------
★ Event Details ★
Linaro Connect Hong Kong 2018 (HKG18)
19-23 March 2018
Regal Airport Hotel Hong Kong
---------------------------------------------------
Keyword: Digital Home
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961"
HKG18-120 - Devicetree Schema Documentation and Validation Linaro
"Session ID: HKG18-120
Session Name: HKG18-120 - Structured Documentation and Validation for Device Tree
Speaker: Grant Likely
Track: Kernel
★ Session Summary ★
Devicetree has become the dominant hardware configuration language used when building embedded systems. Projects using Devicetree now include Linux, U-Boot, Android, FreeBSD, and Zephyr. However, it is notoriously difficult to write correct Devicetree data files. The dtc tools perform limited tests for valid data, and there there is not yet a way to add validity test for specific hardware descriptions. Neither is there a good way to document requirements for specific bindings. Work is underway to solve these problems. This session will present a proposal for adding Devicetree schema files to the Devicetree toolchain that can be used to both validate data and produce usable documentation.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/hkg18/hkg18-120/
Presentation: http://connect.linaro.org.s3.amazonaws.com/hkg18/presentations/hkg18-120.pdf
Video: http://connect.linaro.org.s3.amazonaws.com/hkg18/videos/hkg18-120.mp4
---------------------------------------------------
★ Event Details ★
Linaro Connect Hong Kong 2018 (HKG18)
19-23 March 2018
Regal Airport Hotel Hong Kong
---------------------------------------------------
Keyword: Kernel
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961"
"Session ID: HKG18-223
Session Name: HKG18-223 - Trusted Firmware M : Trusted Boot
Speaker: Tamas Ban
Track: LITE
★ Session Summary ★
An overview of the trusted boot concept and firmware update on the ARMv8-M based platform and how MCUBoot acts as a BL2 bootloader for TF-M.
Trusted Firmware M
In October 2017, Arm announced the vision of Platform Security Architecture (PSA) - a common framework to allow everyone in the IoT ecosystem to move forward with stronger, scalable security and greater confidence. There are three key stages to the Platform Security Architecture: Analysis, Architecture and Implementation which are described at https://developer.arm.com/products/architecture/platform-security-architecture.
_Trusted Firmware M, i.e. TF-M, is the Arm project to provide an open source reference implementation firmware that will conform to the PSA specification for M-Class devices. Early access to TF-M was released in December 2017 and it is being made public during Linaro Connect. The implementation should be considered a prototype until the PSA specifications reach release state and the code aligns._
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/hkg18/hkg18-223/
Presentation: http://connect.linaro.org.s3.amazonaws.com/hkg18/presentations/hkg18-223.pdf
Video: http://connect.linaro.org.s3.amazonaws.com/hkg18/videos/hkg18-223.mp4
---------------------------------------------------
★ Event Details ★
Linaro Connect Hong Kong 2018 (HKG18)
19-23 March 2018
Regal Airport Hotel Hong Kong
---------------------------------------------------
Keyword: LITE
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961"
Taking AI to the Next Level in Manufacturing.pdfssuserfac0301
Read Taking AI to the Next Level in Manufacturing to gain insights on AI adoption in the manufacturing industry, such as:
1. How quickly AI is being implemented in manufacturing.
2. Which barriers stand in the way of AI adoption.
3. How data quality and governance form the backbone of AI.
4. Organizational processes and structures that may inhibit effective AI adoption.
6. Ideas and approaches to help build your organization's AI strategy.
In the rapidly evolving landscape of technologies, XML continues to play a vital role in structuring, storing, and transporting data across diverse systems. The recent advancements in artificial intelligence (AI) present new methodologies for enhancing XML development workflows, introducing efficiency, automation, and intelligent capabilities. This presentation will outline the scope and perspective of utilizing AI in XML development. The potential benefits and the possible pitfalls will be highlighted, providing a balanced view of the subject.
We will explore the capabilities of AI in understanding XML markup languages and autonomously creating structured XML content. Additionally, we will examine the capacity of AI to enrich plain text with appropriate XML markup. Practical examples and methodological guidelines will be provided to elucidate how AI can be effectively prompted to interpret and generate accurate XML markup.
Further emphasis will be placed on the role of AI in developing XSLT, or schemas such as XSD and Schematron. We will address the techniques and strategies adopted to create prompts for generating code, explaining code, or refactoring the code, and the results achieved.
The discussion will extend to how AI can be used to transform XML content. In particular, the focus will be on the use of AI XPath extension functions in XSLT, Schematron, Schematron Quick Fixes, or for XML content refactoring.
The presentation aims to deliver a comprehensive overview of AI usage in XML development, providing attendees with the necessary knowledge to make informed decisions. Whether you’re at the early stages of adopting AI or considering integrating it in advanced XML development, this presentation will cover all levels of expertise.
By highlighting the potential advantages and challenges of integrating AI with XML development tools and languages, the presentation seeks to inspire thoughtful conversation around the future of XML development. We’ll not only delve into the technical aspects of AI-powered XML development but also discuss practical implications and possible future directions.
Driving Business Innovation: Latest Generative AI Advancements & Success StorySafe Software
Are you ready to revolutionize how you handle data? Join us for a webinar where we’ll bring you up to speed with the latest advancements in Generative AI technology and discover how leveraging FME with tools from giants like Google Gemini, Amazon, and Microsoft OpenAI can supercharge your workflow efficiency.
During the hour, we’ll take you through:
Guest Speaker Segment with Hannah Barrington: Dive into the world of dynamic real estate marketing with Hannah, the Marketing Manager at Workspace Group. Hear firsthand how their team generates engaging descriptions for thousands of office units by integrating diverse data sources—from PDF floorplans to web pages—using FME transformers, like OpenAIVisionConnector and AnthropicVisionConnector. This use case will show you how GenAI can streamline content creation for marketing across the board.
Ollama Use Case: Learn how Scenario Specialist Dmitri Bagh has utilized Ollama within FME to input data, create custom models, and enhance security protocols. This segment will include demos to illustrate the full capabilities of FME in AI-driven processes.
Custom AI Models: Discover how to leverage FME to build personalized AI models using your data. Whether it’s populating a model with local data for added security or integrating public AI tools, find out how FME facilitates a versatile and secure approach to AI.
We’ll wrap up with a live Q&A session where you can engage with our experts on your specific use cases, and learn more about optimizing your data workflows with AI.
This webinar is ideal for professionals seeking to harness the power of AI within their data management systems while ensuring high levels of customization and security. Whether you're a novice or an expert, gain actionable insights and strategies to elevate your data processes. Join us to see how FME and AI can revolutionize how you work with data!
Ivanti’s Patch Tuesday breakdown goes beyond patching your applications and brings you the intelligence and guidance needed to prioritize where to focus your attention first. Catch early analysis on our Ivanti blog, then join industry expert Chris Goettl for the Patch Tuesday Webinar Event. There we’ll do a deep dive into each of the bulletins and give guidance on the risks associated with the newly-identified vulnerabilities.
AI 101: An Introduction to the Basics and Impact of Artificial IntelligenceIndexBug
Imagine a world where machines not only perform tasks but also learn, adapt, and make decisions. This is the promise of Artificial Intelligence (AI), a technology that's not just enhancing our lives but revolutionizing entire industries.
Unlock the Future of Search with MongoDB Atlas_ Vector Search Unleashed.pdfMalak Abu Hammad
Discover how MongoDB Atlas and vector search technology can revolutionize your application's search capabilities. This comprehensive presentation covers:
* What is Vector Search?
* Importance and benefits of vector search
* Practical use cases across various industries
* Step-by-step implementation guide
* Live demos with code snippets
* Enhancing LLM capabilities with vector search
* Best practices and optimization strategies
Perfect for developers, AI enthusiasts, and tech leaders. Learn how to leverage MongoDB Atlas to deliver highly relevant, context-aware search results, transforming your data retrieval process. Stay ahead in tech innovation and maximize the potential of your applications.
#MongoDB #VectorSearch #AI #SemanticSearch #TechInnovation #DataScience #LLM #MachineLearning #SearchTechnology
Generating privacy-protected synthetic data using Secludy and MilvusZilliz
During this demo, the founders of Secludy will demonstrate how their system utilizes Milvus to store and manipulate embeddings for generating privacy-protected synthetic data. Their approach not only maintains the confidentiality of the original data but also enhances the utility and scalability of LLMs under privacy constraints. Attendees, including machine learning engineers, data scientists, and data managers, will witness first-hand how Secludy's integration with Milvus empowers organizations to harness the power of LLMs securely and efficiently.
How to Interpret Trends in the Kalyan Rajdhani Mix Chart.pdfChart Kalyan
A Mix Chart displays historical data of numbers in a graphical or tabular form. The Kalyan Rajdhani Mix Chart specifically shows the results of a sequence of numbers over different periods.
HCL Notes und Domino Lizenzkostenreduzierung in der Welt von DLAUpanagenda
Webinar Recording: https://www.panagenda.com/webinars/hcl-notes-und-domino-lizenzkostenreduzierung-in-der-welt-von-dlau/
DLAU und die Lizenzen nach dem CCB- und CCX-Modell sind für viele in der HCL-Community seit letztem Jahr ein heißes Thema. Als Notes- oder Domino-Kunde haben Sie vielleicht mit unerwartet hohen Benutzerzahlen und Lizenzgebühren zu kämpfen. Sie fragen sich vielleicht, wie diese neue Art der Lizenzierung funktioniert und welchen Nutzen sie Ihnen bringt. Vor allem wollen Sie sicherlich Ihr Budget einhalten und Kosten sparen, wo immer möglich. Das verstehen wir und wir möchten Ihnen dabei helfen!
Wir erklären Ihnen, wie Sie häufige Konfigurationsprobleme lösen können, die dazu führen können, dass mehr Benutzer gezählt werden als nötig, und wie Sie überflüssige oder ungenutzte Konten identifizieren und entfernen können, um Geld zu sparen. Es gibt auch einige Ansätze, die zu unnötigen Ausgaben führen können, z. B. wenn ein Personendokument anstelle eines Mail-Ins für geteilte Mailboxen verwendet wird. Wir zeigen Ihnen solche Fälle und deren Lösungen. Und natürlich erklären wir Ihnen das neue Lizenzmodell.
Nehmen Sie an diesem Webinar teil, bei dem HCL-Ambassador Marc Thomas und Gastredner Franz Walder Ihnen diese neue Welt näherbringen. Es vermittelt Ihnen die Tools und das Know-how, um den Überblick zu bewahren. Sie werden in der Lage sein, Ihre Kosten durch eine optimierte Domino-Konfiguration zu reduzieren und auch in Zukunft gering zu halten.
Diese Themen werden behandelt
- Reduzierung der Lizenzkosten durch Auffinden und Beheben von Fehlkonfigurationen und überflüssigen Konten
- Wie funktionieren CCB- und CCX-Lizenzen wirklich?
- Verstehen des DLAU-Tools und wie man es am besten nutzt
- Tipps für häufige Problembereiche, wie z. B. Team-Postfächer, Funktions-/Testbenutzer usw.
- Praxisbeispiele und Best Practices zum sofortigen Umsetzen
For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2024/06/building-and-scaling-ai-applications-with-the-nx-ai-manager-a-presentation-from-network-optix/
Robin van Emden, Senior Director of Data Science at Network Optix, presents the “Building and Scaling AI Applications with the Nx AI Manager,” tutorial at the May 2024 Embedded Vision Summit.
In this presentation, van Emden covers the basics of scaling edge AI solutions using the Nx tool kit. He emphasizes the process of developing AI models and deploying them globally. He also showcases the conversion of AI models and the creation of effective edge AI pipelines, with a focus on pre-processing, model conversion, selecting the appropriate inference engine for the target hardware and post-processing.
van Emden shows how Nx can simplify the developer’s life and facilitate a rapid transition from concept to production-ready applications.He provides valuable insights into developing scalable and efficient edge AI solutions, with a strong focus on practical implementation.
Building Production Ready Search Pipelines with Spark and MilvusZilliz
Spark is the widely used ETL tool for processing, indexing and ingesting data to serving stack for search. Milvus is the production-ready open-source vector database. In this talk we will show how to use Spark to process unstructured data to extract vector representations, and push the vectors to Milvus vector database for search serving.
Have you ever been confused by the myriad of choices offered by AWS for hosting a website or an API?
Lambda, Elastic Beanstalk, Lightsail, Amplify, S3 (and more!) can each host websites + APIs. But which one should we choose?
Which one is cheapest? Which one is fastest? Which one will scale to meet our needs?
Join me in this session as we dive into each AWS hosting service to determine which one is best for your scenario and explain why!
Let's Integrate MuleSoft RPA, COMPOSER, APM with AWS IDP along with Slackshyamraj55
Discover the seamless integration of RPA (Robotic Process Automation), COMPOSER, and APM with AWS IDP enhanced with Slack notifications. Explore how these technologies converge to streamline workflows, optimize performance, and ensure secure access, all while leveraging the power of AWS IDP and real-time communication via Slack notifications.
Threats to mobile devices are more prevalent and increasing in scope and complexity. Users of mobile devices desire to take full advantage of the features
available on those devices, but many of the features provide convenience and capability but sacrifice security. This best practices guide outlines steps the users can take to better protect personal devices and information.
2. 2
ACPI-Next C-states
Numerical non-equivalency – Types of states
Topology awareness
Additional Information: Version, BreakEven, S/R, Cache
Device, Power Resource, and Interrupt dependencies
PSCI
3. 3
Standardise types of State for ARM
ARM Linux community uses ACPI derived terminology:
C-State, P-state
But it’s not done in a very standard way. Some “general
rules”
C1 tend to be WFI
Larger numbers mean deeper states
Hard to compare systems
ACPI has strong definitions for C0-C3 states
Allows more states, but they are of type C1,C2 or C3
But are not defined in ARM terms
4. 4
Types of State
Run
Hierarchy is running fully operational
Idle
Hierarchy is not executing, but has preserved all
context, will wake up through an interrupt
Sleep
Hierarchy is not executing, context is lost and must be
saved/restored, will wake up through an interrupt.
Caches in the hierarchy are off
Off
Hierarchy is not executing, context is lost and wake up
will only occur by an explicit software command or By
physical hardware reset
zzz
RIP
5. 5
Types of State
Run
Hierarchy is running fully operational
Idle
Hierarchy is not executing, but has preserved all
context, will wake up through an interrupt
Sleep
Hierarchy is not executing, context is lost and must be
saved/restored, will wake up through an interrupt
Caches in the hierarchy are off
Off
Hierarchy is not executing, context is lost and wake up
will only occur by an explicit software command or By
physical hardware reset
zzz
RIP
C0
C3
C1
6. 6
Types of State
Propose updating language for C1,C2,C3 so that for ARM
based systems:
C1 is state (WFI) and also a type of state Idle
C2 not used on ARM systems (as type of state)
C3 as a type of state has the semantics of Sleep
7. 7
Topology
ACPI uses _CSD to express coupled C-states
_CSD relies on the notion of symmetry : Same states for all
processors
This doesn’t bode well for heterogeneous systems that might
have different number of states per processor
Feedback from OSVs, is that _CSD is not a very nice object
to work with in kernel
8. 8
Topology
ACPI has a tree like name space
We can use that to represent topology directly
Modules : Structure that can contain other modules or
devices
We can declare individual CPU states
We can declare cluster/system states
Can represent any arbitrary topology
10. 10
Additional Information
_CST doesn’t have enough information for an OSPM to
manage an ARM system’s power states
No representation of what context may be lost
No representation of what caches may be lost/if they need
management or not
Last core?
Break Even Latency missing
No easy way to link C-states with device states or power resource
states
No easy way to describe wake capability of an interrupt
Not every interrupt can wake you from every state
No versioning
11. 11
Additional Information
Proposal is to replace _CST with new object method _CSX
Package {
Version, // Integer (WORD)
Count, // Integer (WORD)
CStatesX[0], // Package
…
CStatesX[N-1] // Package
}
Version is self explanatory. It would start at 0
13. 13
Additional Information
BreakEven:
How long do I have to be in this state compared to WFI to save power
GenStateFlags:
OSPM_MANAGE_CACHE:
Set if OSPM has to manage caches,
CACHES_CONTENTS_LOST
Set if caches up to current topology level are lost with this power state
(More on this later)
PLATFORM_COORDINATED:
If set, platform coordinates and does last man standing.
If state is requested it will be entered when last CPU requests that state
or deeper
If clear if state is requested it will be entered. OSPM has to coordinate
ArchStateFlags:
Architecture specific flags. For ARM: what context needs to be saved/restored
Generic Registers, VFP, Debug context, Timer, CPU Interface, GICD
14. 14
Additional Information
PowerDepth:
Identifier describing how deep a power state is
Bigger number -> Bigger power savings -> Bigger latencies
Defaults to 0
Used to describe dependencies
PowerResources: if ON States of depth X or higher are not available
Requires augmenting PowerResource Definition
Device state D0, D1, D2, D3hot then:
States of depth X=FunctionOfDState or higher are not available
Requires new methods
IRQ X can wake up power states of PowerDepth Y or lower
Required augmenting IRQ descriptions
15. 15
Additional Information
LastMan:
Allows for cases where only one specific CPU can enter a coupled
State
If Plaform Coordinated (PLATFORM_COORDINATED flag
set) this should be undefined
If CPU only power state this should be undefined
If it is a coupled C state:
If state can be initiated on any CPU (doesn’t matter who last man is) it
must be undefined
Otherwise reference to processor node that must initiate the power
state transition
16. 16
Cache
Propose that each level of topology has a Cache object,
_CLV
Describes Caches that are private to that part of the topology
Simplest instance could be simply a list of caches:
_CLV return package of integers
eg: Core has L1 cache = {L1}
Cluster has L2 cache = {L2}
Combines with flags, CACHES_CONTENTS_LOST and
OSPM_MANAGE_CACHE
17. 17
Cache
When not all CPUs have
entered a coupled state:
Caches in sub-hierarchies
will be lost
CPUx: L1 Module Cluster 0 {
_CSX(…
CStateX : CACHES_CONTENTS_LOST
…)
_CLV( L2 )
Processor CPU0 {
CSX(…)
_CLV( L1)
}
Processor CPU0 {
CSX(…)
_CLV( L1)
}}
L1
CPU1
L1
CPU0
Cluster 0
L2
18. 18
Cache
When not all CPUs have
entered a coupled state:
Caches in sub-hierarchies
will be lost
CPUx: L1
When last CPU enters
cluster state:
All caches up to topology
level are lost
L2, all L1s
Module Cluster 0 {
_CSX(…
CStateX : CACHES_CONTENTS_LOST
…)
_CLV( L2 )
Processor CPU0 {
CSX(…)
_CLV( L1)
}
Processor CPU0 {
CSX(…)
_CLV( L1)
}}
L1
CPU1
L1
CPU0
Cluster 0
L2
19. 19
PSCI
Two flags in FADT Flags field:
PSCI_PRESENT: 1 if PSCI is implemented
USE_HVC: 1 if HVC is should be used in preference to SMC as
PSCI conduit
Note no override or function IDs
20. 20
PSCI
CStateX uses Register to denote how to enter a C-state
Registers represented GAS: Generic Address Structure
GAS is very flexible and allows encapsulating “Software as
Hardware” in very specific cirmcunstance. This is called
Function Fixed Hardware
Power State Parameter of CPU_SUSPEND is the Registers
Address
Equivalent to method used for Intel today
21. 21
PSCI
GAS Register format for a C-State
Field Description
Address Space ID 0x7f (FFH identifier)
Register Bit Width 32
Register Bit Offset 0
Access Size 3 (DWORD)
Address Upper DWORD must be zero
Lower DWORD must denote the PSCI power_state
parameter for the CPU_SUSPEND call
Address: 0xF000000_00000000 is reserved for WFI
this would not result in a PSCI call