This document proposes a robust dynamic watermarking scheme to embed a signature in the finite state machine (FSM) of a sequential circuit design at the behavioral level for intellectual property protection. The watermark is embedded by modifying state transitions of the FSM based on a pseudorandom sequence generated from the signature. During detection, the ownership can be verified by extracting the watermark embedded in the state transitions by running the FSM or making it part of a test kernel. This scheme aims to make the watermark robust against attacks like state reduction compared to existing static watermarking techniques.

1. A ROBUST FSM WATERMARKING
SCHEME FOR IP PROTECTION OF
SEQUENTIAL CIRCUIT DESIGN
PROJECT GUIDE SUBMITTED BY
MR.DEVARAJ B.E ., D.MOHAN RAJ
D.RAJA
A.THANGAPANDI

2. AREA OF PROJECT
• Very Large Scale Integration

3. ABSTRACT
• To protect a VLSI design against IP infringement is
by embedding a signature
• Direct and convenient detection scheme to allow
allow the watermark on the FSM be publicly
detectable

4. INTRODUCTION
• The signature can be recovered from the
misappropriated IP
• Dynamic watermarking scheme is proposed
• Embedding the watermark at the behavioral level

5. EXISTING SYSTEM AND DRAWBACKS
EXISTING SYSTEM
• Static watermarking
• To detect the output without protected design
• Embedding the information at the architecture level
design
DRAWBACKS
• Embedding capacity is limited
• Not suitable for large design

6. DRAWBACKS
• Embedding capacity is limited
• Not suitable for large design

7. PROPOSED SYSTEM
• Dynamic watermarking
• The watermark is embedded in the state transitions of
FSM at the behavioral level
• Robust against state reduction attacks.

8. ADVANTAGES AND APPLICATIONS
ADVANTAGES
• Reduced vulnerability
• Robust architecture
• Attacker harder to erase or hide the watermark
APPLICATIONS
• Manufacture of IC‟s
• communication

9. PSEUDORANDOM NUMBER
GENERATOR
• To generate a sequence
• The encrypted message is too long, a Message Digest
(MD) algorithm
• The possibility that the same group of numbers is
generated by coincidence is low

10. GENERATION OF WATERMARK
SEQUENCE
• Message, is first encoded into a binary string and then
encrypted by a provable cryptographic algorithm with
the secret key of the IP owner
• message digest (MD) algorithm can be used to reduce
its length

11. WATERMARKED TRANSITION
• Pseudo codes for the determination of watermarked
transitions in state transition algorithm

12. WATERMARK INSERTION PROCESS
• Pseudo input variable 2n−1 potential free input
combinations are created in every state transition
• Value „0‟ for existing transition
• Value „1‟ for waetrmarked transition
• Don‟t care inputs in transitions to optimize the design
of next state and output decoders

13. WATERMARK DETECTION PROCESS
• The ownership can be authenticated directly by
running the watermarked FSM
• the authorship of the watermarked FSM can be
verified off chip by making it a part of the test kernel

14. BLOCK DIAGRAM

15. BLOCK DIAGRAM EXPLANATION
• Input variable “0” for existing transition
• Input variable is assigned “1”for added transition
• n=1(input variable),k=3(output variable) is applied to
8 bit embed watermark seqence
“10101000” (m/k)=3

16. TIME STAMPED SIGNATURE

17. SOFTWARE REQUIREMENT
• Modelsim 6.4c
• Xilinx ISE 10.1i

18. REFERENCES
• Intellectual Property Protection Development
Working Group, Intellec-tual Property Protection:
Schemes, Alternatives and Discussion. VSI Alliance,
Aug. 2001, white paper, version 1.1
• I. Hong and M. Potkonjak, “Techniques for
intellectual property protection of DSP designs,” in
Proc. IEEE Int. Conf. Acoust. Speech Signal Process.,
vol. 5. May 1998, pp