chaitra-1.pptx fake news detection using machine learning
A PUF-FSM Binding Scheme for FPGA IP PROTECTION
1. 8 July 2017
1
A PUF-FSM Binding Scheme for FPGA IP
Protection and Pay-Per Device licensing
Submitted by;
ELIZABETH MATHEW
S1 M.Tech EC
Guide:
Er. NIA ACHU ISSAC
Assistant professor
ECE Department
CKC Manoor
CKC MANOOR MTECH EC
3. INTRODUCTION
Novel IP protection
Restrict IP’S execution only on Specific FPGA devices.
Protect IP’S from cloning/copying.
Counterfeits avoided.
First non encryption based HWIP binding
method
3CKC MANOOR MTECH EC
8 July 2017
4. TRADITIONAL BINDING SCHEME
Secret key in on-chip memory.
Cryptography used to authenticate an IC.
4
IC with
a secret key
Sends a random number
Sign the number with a secret key
Only the IC’s key can generate
a valid signature
CKC MANOOR MTECH EC
8 July 2017
5. EXISTING METHODS
Bit-stream encryption.
Advanced encryption standard (AES) core.
Keyed-hash message authentication code (HMAC) core.
Triple data encryption standard (3DES).
5
CKC MANOOR MTECH EC
8 July 2017
6. LIMITATIONS OF EXISTING METHODS
No solution-: pay-per-device licensing requirement.
Security vulnerabilities.
On-chip modules needed.
Not appropriate for resource-limited environments
Allows attackers to attack at any time.
Expensive and insecure.
Damage brand reputation.
6
CKC MANOOR MTECH EC
8 July 2017
7. PROPOSED SYSTEM
Binds FSM with PUF.
Unique ID for each device.
Secure.
No secret key storage.
7CKC MANOOR MTECH EC
8 July 2017
10. FIELD PROGRAMMABLE GATE
ARRAY
Popular design platform
Low NRE cost
Shorter time to market
Reprogrammable
High flexibility
Can implement any digital system
Faster and cheaper design.
10
CKC MANOOR MTECH EC
8 July 2017
11. INTELLECTUAL PROPERTY(IP)
Creations of the intellect.
Monopoly is assigned to designated
owners by law.
Law includes copyright, patent.
Layout design, trade secrets.
11
CKC MANOOR MTECH EC
8 July 2017
12. FINITE STATE MACHINE (FSM)
Popular model.
Bind HWIPs to the FPGAs with PUFs
Outputs depend on present input & history of the input.
Finite number of states.
12
CKC MANOOR MTECH EC
8 July 2017
13. THE BINDING FSM STRUCTURE
13
CKC MANOOR MTECH EC
8 July 2017
15. PARTIES INVOLVED IN HWIP BINDING
FPGA Vendor (FV)
System Developer (SD)
IP Core Vendor (CV)
End User (EU)
15
CKC MANOOR MTECH EC
8 July 2017
16. WORKING
FPGA Device Enrollment.
Hardware IP Core Enrollment and Distribution
Hardware IP Core Licensing.
Product Licensing.
16
CKC MANOOR MTECH EC
8 July 2017
21. ADVANTAGES
Protect both single FPGA configurations and third-party
FPGA IP cores.
Supports the pay-per-device licensing mechanism.
No permanent storage for secret keys in the FPGA.
21
CKC MANOOR MTECH EC
8 July 2017
22. DISADVANTAGES
Design components without bound FSMs will
still be vulnerable to tamping attacks.
Vulnerable to side channel attacks
22
CKC MANOOR MTECH EC
8 July 2017
23. FUTURE SCOPE
Can introduce more secure protection mechanism
Combined with anti-tamper methods.
Appropriate countermeasures for side channel effects.
Make applicable to high-speed designs that do not have
FSMs
23
CKC MANOOR MTECH EC
8 July 2017
24. CONCLUSION
Enables binding hardware IPs to specific FPGAs utilizing the
PUF and the FSM.
Protect the third-party FPGA IP cores
Supports the pay-per-device licensing mechanism.
Low hardware cost.
24
CKC MANOOR MTECH EC
8 July 2017
25. REFERENCE
Jiliang zhang, Yaping Lin ”A PUF-FSM binding scheme for FPGA IP
Protection and pay-per-device licensing”IEEE Transactions on information
forensics and security, vol. 10, no. 6, june 2015 1137
J. Guajardo, S. S. Kumar, G.-J. Schrijen, and P. Tuyls, “Physical
unclonable functions and public-key crypto for FPGA IP protection,”in
Proc. Int. Conf. Field Program. Logic Appl. (FPL), Aug. 2007,pp. 189–
195.
Z. Paral and S. Devadas, “Reliable and efficient PUF-based key
generationusing pattern matching,” in Proc. IEEE Int. Symp. Hardw.-
Oriented Secur. Trust (HOST), Jun. 2011, pp. 128–133.
25
CKC MANOOR MTECH EC
8 July 2017
