Digital                                   	Baseband 		  		Transceiver <br />
Digital communication system<br />
Digital communication system<br />
Digital communication system<br />
Digital communication system<br />
Digital communication system<br />
Digital communication system<br />
Digital communication system<br />
Digital communication system<br />
Audio compression is a form of data compression designed to reduce the size of audio files.<br />Speech coding is the appl...
Mixed Excitation Linear Predictive(MELP)<br />A MELP vocoder uses a mixed-excitation model based on a traditional LPC para...
MELP Characteristics <br />Sampling rate     8000Hz<br />Frame size          180 samples<br />Bits/Sample        16bits<br...
Project is about speech compression using MELP codec<br />MELP is developed for extremely low bit data rate<br />Optimizat...
Features of the SigC55x MELP System include<br />Multichannel real-time performance.<br />Flexible audio interface.<br />S...
CPU architecture consists of the following four units.<br />Instruction buffer unit<br />Program flow unit <br />Address d...
Instruction buffer unit<br />Decodes instruction<br />Decode logic unit<br />Maintains constant stream of tasks for comput...
Program flow unit <br />keeps track of the execution point within the program<br />Hardware loop control<br />Pipeline pro...
Address data flow unit <br />Provides the address pointers for data accesses<br />Dedicated hardware for managing the five...
Data computation unit <br />Heart of the DSP<br />Performs the arithmetic computations <br />It includes <br /><ul><li>The...
The main ALU
The accumulator registers
Barrel shifter
Rounding & saturation control</li></li></ul><li>TMS320C55x Tabular Description<br />
Overview of the CPU Architecture<br />
Using intrinsic<br />Optimization level of compiler<br />Assembly language tools<br />Parallelism<br />  Pipelining<br /> ...
Using intrinsic<br />ETSI functions <br />		Predefined functions by TEXAS instruments<br />GSM.h<br /> 		Replacement for E...
Three levels of optimization <br /> O0<br /> O1<br /> O2<br /> O3<br />Optimization level of compiler<br />
<ul><li>Allocates variables to registers
Eliminates unused code
Simplifies expressions and statements
Expands calls to functions declared inline</li></ul>-O0 Optimization level<br />
-O1 Optimization level<br />Performs all -O0 optimizations<br />Performs local copy/constant propagation<br />Removes unus...
-O2 Optimization level<br />Performs all -O1 optimizations<br />Performs loop optimizations<br />Eliminates global unused ...
Performs all -O2 optimizations<br />Removes all functions that are never called<br />Inline calls to small functions.<br /...
Create loops that efficiently use C55x hardware loops, MAC hardware, and dual-MAC hardware.<br />Use intrinsics to replace...
Parallelism<br />Built in parallelism  <br />Example <br />     Dual Mac<br />		MAC *AR2+, *CDP+, AC0<br />:: MAC *AR3+, *...
Efficient looping<br />Loop unrolling<br />Single repeat: repeat(CSR/k8/k16)<br />Local block repeat: localrepeat{}<br />B...
Efficient looping<br />Loop unrolling<br />            Loop unrolling involves structuring computations to exploit the reu...
Single repeat<br />       There are advantages to using CSR for the repeat count:<br /><ul><li>The repeat count can be dyn...
	Using CSR saves outer loop cycles when the single-repeat loop is an inner loop.
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Melp codec optimization using DSP kit

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Because of bandwidth constraint, low bit-rate vocoders have gained increasing prominence in many digital voice communications systems including the Internet. The requirement of secure voice transmission by appropriate encryption and decryption has also prompted the widespread use of digital speech coding techniques in various military applications.
This project is about speech compression using MELP codec, stands for Mixed Excitation Linear Predictive encoding. It is based on a new communication standard developed for extremely low bit data rate. The processing time required for MELP is very large limiting its use in real time applications such as handheld radio transceiver, etc. The theme of the project is to reduce MELP processing time using different optimization techniques. Texas instrument also launched a special DSP processor TMS320C55x series which is well suited for MELP codec processing.

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Melp codec optimization using DSP kit

  1. 1.
  2. 2. Digital Baseband Transceiver <br />
  3. 3. Digital communication system<br />
  4. 4. Digital communication system<br />
  5. 5. Digital communication system<br />
  6. 6. Digital communication system<br />
  7. 7. Digital communication system<br />
  8. 8. Digital communication system<br />
  9. 9. Digital communication system<br />
  10. 10. Digital communication system<br />
  11. 11. Audio compression is a form of data compression designed to reduce the size of audio files.<br />Speech coding is the application of data compressionof digital audio signals containing speech. <br /> Source Encoder<br />
  12. 12. Mixed Excitation Linear Predictive(MELP)<br />A MELP vocoder uses a mixed-excitation model based on a traditional LPC parametric model, but includes the additional features of mixed-excitation, periodic pulses, pulse dispersion and adaptive spectral enhancement.<br />
  13. 13. MELP Characteristics <br />Sampling rate 8000Hz<br />Frame size 180 samples<br />Bits/Sample 16bits<br />Frame duration 22.5 ms<br />Bit Rate 2.4Kbps<br />
  14. 14. Project is about speech compression using MELP codec<br />MELP is developed for extremely low bit data rate<br />Optimization of MELP to reduce its processing time <br />The project is designed for HF range communication<br />THEME OF PROJECT<br />
  15. 15. Features of the SigC55x MELP System include<br />Multichannel real-time performance.<br />Flexible audio interface.<br />Small form-factor for MELP production systems<br />
  16. 16. CPU architecture consists of the following four units.<br />Instruction buffer unit<br />Program flow unit <br />Address data flow unit<br />Data computation unit <br />DSP TMS320C55x CPU ARCHITECTURE<br />
  17. 17. Instruction buffer unit<br />Decodes instruction<br />Decode logic unit<br />Maintains constant stream of tasks for computational units<br />
  18. 18. Program flow unit <br />keeps track of the execution point within the program<br />Hardware loop control<br />Pipeline protection<br />
  19. 19. Address data flow unit <br />Provides the address pointers for data accesses<br />Dedicated hardware for managing the five data buses<br />Increases the instruction level parallelism<br />
  20. 20. Data computation unit <br />Heart of the DSP<br />Performs the arithmetic computations <br />It includes <br /><ul><li>The MACs
  21. 21. The main ALU
  22. 22. The accumulator registers
  23. 23. Barrel shifter
  24. 24. Rounding & saturation control</li></li></ul><li>TMS320C55x Tabular Description<br />
  25. 25. Overview of the CPU Architecture<br />
  26. 26. Using intrinsic<br />Optimization level of compiler<br />Assembly language tools<br />Parallelism<br /> Pipelining<br /> Efficient looping<br />Optimization Techniques <br />
  27. 27. Using intrinsic<br />ETSI functions <br /> Predefined functions by TEXAS instruments<br />GSM.h<br /> Replacement for ETSI function <br />
  28. 28. Three levels of optimization <br /> O0<br /> O1<br /> O2<br /> O3<br />Optimization level of compiler<br />
  29. 29. <ul><li>Allocates variables to registers
  30. 30. Eliminates unused code
  31. 31. Simplifies expressions and statements
  32. 32. Expands calls to functions declared inline</li></ul>-O0 Optimization level<br />
  33. 33. -O1 Optimization level<br />Performs all -O0 optimizations<br />Performs local copy/constant propagation<br />Removes unused assignments<br />
  34. 34. -O2 Optimization level<br />Performs all -O1 optimizations<br />Performs loop optimizations<br />Eliminates global unused assignments<br />Performs loop unrolling<br />
  35. 35. Performs all -O2 optimizations<br />Removes all functions that are never called<br />Inline calls to small functions.<br />Reorders function declarations so that the attributes of called functions are known when the caller is optimized<br />-O3 Optimization level<br />
  36. 36. Create loops that efficiently use C55x hardware loops, MAC hardware, and dual-MAC hardware.<br />Use intrinsics to replace complicated C/C++ code<br />Use long accesses to reference 16-bit data in memory<br /> Refining the C/C++ Code:<br />
  37. 37. Parallelism<br />Built in parallelism <br />Example <br /> Dual Mac<br /> MAC *AR2+, *CDP+, AC0<br />:: MAC *AR3+, *CDP+, AC1<br />User defined parallel<br /> AC1 = AC1 + (*AR4+ * coef (*CDP+))<br /> || repeat (CSR)<br />ASSEMBLY LANGUAGE TOOLS<br />
  38. 38. Efficient looping<br />Loop unrolling<br />Single repeat: repeat(CSR/k8/k16)<br />Local block repeat: localrepeat{}<br />Block repeat: blockrepeat{}<br />Branch on auxiliary register not zero<br />ASSEMBLY LANGUAGE TOOLS<br />
  39. 39. Efficient looping<br />Loop unrolling<br /> Loop unrolling involves structuring computations to exploit the reuse of data among different time or geometric iterations of the algorithm<br />
  40. 40. Single repeat<br /> There are advantages to using CSR for the repeat count:<br /><ul><li>The repeat count can be dynamically computed during runtime and stored to CSR.
  41. 41. Using CSR saves outer loop cycles when the single-repeat loop is an inner loop.
  42. 42. An optional syntax extension enables the repeat instruction to modify the CSR after copying the content of CSR to RPTC.</li></ul>Efficient looping<br />
  43. 43. Local block repeat<br /> Its mechanism provides a way to repeat a block from the instruction buffer queue.<br />Advantages<br /><ul><li>Fewer program-memory access pipeline conflicts
  44. 44. Overall lower power consumption
  45. 45. No repetition of wait-state and access penalties when executing loop code from external RAM</li></ul>Efficient looping<br />
  46. 46. Block repeat<br /> Its mechanism always refetches the loop code from memory.<br />When you nest a block-repeat loop inside another block-repeat loop, initialize the block-repeat counters (BRC0 and BRC1) in the code outside of both loops. <br />Efficient looping<br />
  47. 47. Branch on auxiliary register not zero<br />This instruction performs a conditional branch (selected auxiliary register content not equal to 0) of the program counter (PC).<br />Efficient looping<br />
  48. 48. Pipelining<br />The C55x CPU uses instruction pipelining. <br />Pipeline Phases<br /> The C55x instruction pipeline is a protected pipeline that has two decoupled segments:<br /><ul><li>   The first segment, referred to as the fetch pipeline, fetches 32-bit instruction packets from memory, places them in the instruction buffer queue (IBQ), and then feeds the second pipeline segment with 48-bit instruction packets.
  49. 49. The second segment, referred to as the execution pipeline, decodes instructions and performs data accesses and computations.</li></ul> <br /> <br />Assembly language tools<br />
  50. 50. Results<br />
  51. 51. Muhammad SohaibAslam<br />Presented By<br />
  52. 52. Special Thanks<br />Our special thanks to all those who cooperate and guide. Under there supervision I am able to complete this project.<br />

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