A new framework for design and simulation of complex hardware/software systems
Summary Sections Contents Introduction to hw/sw design methodologies Features and limitations of methodologies for the des...
Introduction to hw/sw methodologies <ul><li>Present scenario for the development of digital systems:  </li></ul><ul><ul><l...
Introduction to hw/sw methodologies <ul><li>Raise of the abstraction level: </li></ul><ul><ul><li>Could solve some problem...
Introduction to hw/sw methodologies <ul><li>Raise of the abstraction level </li></ul><ul><ul><li>Examples: </li></ul></ul>...
Introduction to hw/sw methodologies <ul><li>Mix of hw/sw solutions: </li></ul><ul><ul><li>These approaches improve perform...
The proposed flow <ul><li>The proposed methodology: </li></ul><ul><ul><li>Raises the abstraction level in order to allow: ...
The proposed flow
The proposed flow <ul><li>Entry point: high-level structural description </li></ul><ul><ul><li>The designer specifies whic...
The present framework <ul><li>Development of the hardware part of the proposed flow </li></ul><ul><li>Simplified flow: </l...
The present framework <ul><li>Modules composing the library </li></ul><ul><ul><li>Atomic IP  or  atom : very simple module...
The present framework <ul><li>When structuring the system the designer must: </li></ul><ul><ul><li>Instantiate atoms and m...
Parametric cores <ul><li>Parameters and values properties </li></ul>X Top-level X Module Variable X X Top-level X X Module...
The present framework <ul><li>Three actions are related to the core usage: </li></ul><ul><ul><li>Core development: impleme...
The present framework <ul><li>Modules have different views: </li></ul><ul><ul><li>A coarse view that is exploited during t...
The present framework <ul><li>Simple example: computation of  </li></ul><ul><li>F(A, B, K) = sin (A+B) · 2 k </li></ul><ul...
The present framework <ul><li>The choice of the concrete modules is performed exploiting an estimation engine that relies ...
Work in progress <ul><li>Development of new core generators: </li></ul><ul><ul><li>The library is actually based on about ...
Work in progress <ul><li>Definition of the graphical interface  </li></ul><ul><ul><li>Based on QT libraries </li></ul></ul...
Future work <ul><li>Future work </li></ul><ul><ul><li>Extension to the sw domain </li></ul></ul><ul><ul><ul><li>Managing o...
People <ul><li>Some references: </li></ul><ul><ul><li>Laura Frigerio </li></ul></ul><ul><ul><ul><li>[email_address] </li><...
Upcoming SlideShare
Loading in …5
×

3DD 1e Laura

396 views

Published on

Published in: Business, Technology
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
396
On SlideShare
0
From Embeds
0
Number of Embeds
46
Actions
Shares
0
Downloads
9
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide
  • 3DD 1e Laura

    1. 1. A new framework for design and simulation of complex hardware/software systems
    2. 2. Summary Sections Contents Introduction to hw/sw design methodologies Features and limitations of methodologies for the design of mixed systems The proposed flow Overview of a proposal for a new framework for hw/sw co-designs The present framework Work in progress and future works Some details about the present hardware framework: the RoadRunner project Some details about recent projects and ideas for future developments
    3. 3. Introduction to hw/sw methodologies <ul><li>Present scenario for the development of digital systems: </li></ul><ul><ul><li>Growing complexity </li></ul></ul><ul><ul><li>Increase of available silicon area </li></ul></ul><ul><ul><li>Stringent market requirements </li></ul></ul><ul><li>Design flows should </li></ul><ul><ul><li>Manage the complexity </li></ul></ul><ul><ul><li>Exploit the resources </li></ul></ul><ul><ul><li>Short the development time </li></ul></ul><ul><li>Among the possible solutions: </li></ul><ul><ul><li>Raise of the abstraction level </li></ul></ul><ul><ul><li>Mix of solutions targeted to hardware and software domains </li></ul></ul><ul><ul><li>Reuse of IPs </li></ul></ul><ul><ul><li>Development of new methodologies </li></ul></ul>Efficiently fill the productivity gap
    4. 4. Introduction to hw/sw methodologies <ul><li>Raise of the abstraction level: </li></ul><ul><ul><li>Could solve some problems of the classical flow </li></ul></ul><ul><ul><li>Pros: </li></ul></ul><ul><ul><ul><li>Uniform description </li></ul></ul></ul><ul><ul><ul><li>Quicker simulations </li></ul></ul></ul><ul><ul><ul><li>Possible exploration of the solution space </li></ul></ul></ul>Specification Partitioning HW descript. SW descript. Integration Co-simulation HW synth. SW gen. Specification HW/SW desc. HW synth. SW gen. Integration Simulation Partitioning Co-simulation
    5. 5. Introduction to hw/sw methodologies <ul><li>Raise of the abstraction level </li></ul><ul><ul><li>Examples: </li></ul></ul><ul><ul><ul><li>SystemC </li></ul></ul></ul><ul><ul><ul><ul><li>Homogeneous environment for the description of software algorithms, hardware architectures and interfaces </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Different abstraction levels available </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Increase of the simulation speed </li></ul></ul></ul></ul><ul><ul><ul><li>Matlab </li></ul></ul></ul><ul><ul><ul><ul><li>Reliable and-well known environment for algorithmic descriptions </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Several proposals for the use of Matlab in the design of digital systems often based on Simulink toolset (e.g., Sinplify DSP) </li></ul></ul></ul></ul><ul><ul><li>Drawbacks: </li></ul></ul><ul><ul><ul><ul><li>Poor results of high level synthesis </li></ul></ul></ul></ul>
    6. 6. Introduction to hw/sw methodologies <ul><li>Mix of hw/sw solutions: </li></ul><ul><ul><li>These approaches improve performance of the classical flow </li></ul></ul><ul><ul><li>Are based on: </li></ul></ul><ul><ul><ul><li>Integration of different languages </li></ul></ul></ul><ul><ul><ul><li>Integration of simulation environments </li></ul></ul></ul><ul><ul><li>Drawbacks: </li></ul></ul><ul><ul><ul><li>Mixed simulations are still several order of magnitude slower than those of single language approaches </li></ul></ul></ul><ul><ul><ul><li>Impose early system partitioning between hardware and software </li></ul></ul></ul><ul><li>Reuse of IPs: </li></ul><ul><ul><li>Change the granularity at which a design is described </li></ul></ul><ul><ul><li>Drawbacks: </li></ul></ul><ul><ul><ul><li>Integration of complex blocks increases the complexity of system verification </li></ul></ul></ul><ul><ul><ul><li>Mostly linked to hardware domain </li></ul></ul></ul><ul><li>New methodologies… </li></ul>
    7. 7. The proposed flow <ul><li>The proposed methodology: </li></ul><ul><ul><li>Raises the abstraction level in order to allow: </li></ul></ul><ul><ul><ul><li>A uniform description of the system </li></ul></ul></ul><ul><ul><ul><li>The exploration of the solution space </li></ul></ul></ul><ul><ul><ul><li>Faster simulations </li></ul></ul></ul><ul><ul><li>Obtains good synthesis results through a tight connection to hardware and software domains </li></ul></ul><ul><ul><li>Uses back-annotations to allow faster design-loops and a closer control on the underlying architecture </li></ul></ul>
    8. 8. The proposed flow
    9. 9. The proposed flow <ul><li>Entry point: high-level structural description </li></ul><ul><ul><li>The designer specifies which blocks compose the system and how they are interconnected. Modules are only characterized in terms of their functionality. </li></ul></ul><ul><li>The space analysis is performed exploiting a DB of figures for area, time and power consumption values of the blocks </li></ul><ul><li>To perform the simulation into a uniform environment, a SystemC model is built </li></ul><ul><ul><li>Software encapsulation </li></ul></ul><ul><ul><li>VHDL translation </li></ul></ul><ul><ul><li>Interface generation </li></ul></ul><ul><li>If the timing simulation is not satisfactory a new iteration is performed </li></ul>
    10. 10. The present framework <ul><li>Development of the hardware part of the proposed flow </li></ul><ul><li>Simplified flow: </li></ul><ul><li>The framework is based on the RoadRunner toolset composed by: </li></ul><ul><ul><li>RRCore: collection of parametric core generators </li></ul></ul><ul><ul><li>RRCache: database storing core characterization integrated with an estimation engine for uncharacterized modules. </li></ul></ul>
    11. 11. The present framework <ul><li>Modules composing the library </li></ul><ul><ul><li>Atomic IP or atom : very simple module with no internal hierarchy </li></ul></ul><ul><ul><li>Molecular IP or molecule : composite module constituted of Atoms of Molecules </li></ul></ul><ul><li>Hierarchy is obtained combining the generators and not the modules themselves </li></ul>
    12. 12. The present framework <ul><li>When structuring the system the designer must: </li></ul><ul><ul><li>Instantiate atoms and molecules, </li></ul></ul><ul><ul><li>Connect them and </li></ul></ul><ul><ul><li>Assign values to parameters </li></ul></ul><ul><li>A parameter can be explorable or non-explorable </li></ul><ul><ul><li>Explorable parameters can be left unassigned in the design phase and determined during exploration </li></ul></ul><ul><li>The value of a parameter can be fixed or variable </li></ul><ul><ul><li>A fixed value is assigned by the designer, a variable one is left free for the exploration </li></ul></ul><ul><li>A value can be defined at top level or at module level </li></ul><ul><ul><li>For example the reset value is defined at top level and inherited by all submodules </li></ul></ul>
    13. 13. Parametric cores <ul><li>Parameters and values properties </li></ul>X Top-level X Module Variable X X Top-level X X Module Fixed VALUE Non-explorable Explorable PARAMETERS
    14. 14. The present framework <ul><li>Three actions are related to the core usage: </li></ul><ul><ul><li>Core development: implementation of a C++ class that generates the VHDL code for the core </li></ul></ul><ul><ul><li>Core instantiation: selection of a core into the design. An initial coarse definition is accepted in order to perform the exploration phase </li></ul></ul><ul><ul><li>Core encapsulation: a core is instantiated in order to create a molecule </li></ul></ul><ul><li>Cores are characterized by: </li></ul><ul><ul><li>Parameters </li></ul></ul><ul><ul><li>Pins </li></ul></ul><ul><ul><li>Architectures </li></ul></ul>
    15. 15. The present framework <ul><li>Modules have different views: </li></ul><ul><ul><li>A coarse view that is exploited during the exploration </li></ul></ul><ul><ul><ul><li>Only the functionality is specified </li></ul></ul></ul><ul><ul><li>A fine view used for the implementation </li></ul></ul><ul><ul><ul><li>All the details are defined </li></ul></ul></ul><ul><li>A parameter is defined by: </li></ul><ul><ul><li>Name, Description, Type, Domain, Default value, Explorability, Generality, Pin Influence </li></ul></ul><ul><li>A pin is defined by: </li></ul><ul><ul><li>Name ,  Direction , V isibility , Msb , Lsb, Description </li></ul></ul><ul><li>Each META module has some CONCRETE modules that are implementations of a particular architecuture </li></ul>META module CONCRETE module
    16. 16. The present framework <ul><li>Simple example: computation of </li></ul><ul><li>F(A, B, K) = sin (A+B) · 2 k </li></ul><ul><li>The user specifies only module functionalities and interconnections </li></ul><ul><li>Each functionality is a META module that is linked to CONCRETE modules. </li></ul><ul><ul><li>ADDER : ripple-carry, carry look-ahead </li></ul></ul><ul><ul><li>SINE: LUT, CORDIC pipelined, CORDIC iterative </li></ul></ul><ul><ul><li>SHIFTER: arithmetic or logarithmic </li></ul></ul>
    17. 17. The present framework <ul><li>The choice of the concrete modules is performed exploiting an estimation engine that relies on a DB that contains module figures for: </li></ul><ul><ul><li>Area </li></ul></ul><ul><ul><li>Time </li></ul></ul><ul><ul><li>Power </li></ul></ul><ul><li>Possible solutions are obtained varying architectures and explorable-variable parameters </li></ul><ul><li>Finally the VHDL for the system is produced and could be simulated </li></ul>Several technologies are available
    18. 18. Work in progress <ul><li>Development of new core generators: </li></ul><ul><ul><li>The library is actually based on about 50 generators: </li></ul></ul><ul><ul><ul><li>Adders </li></ul></ul></ul><ul><ul><ul><li>Encoders/Decoders </li></ul></ul></ul><ul><ul><ul><li>Cordic </li></ul></ul></ul><ul><ul><ul><li>Functions approximation </li></ul></ul></ul><ul><ul><ul><li>Memories </li></ul></ul></ul><ul><ul><ul><li>Multipliers </li></ul></ul></ul><ul><ul><ul><li>… </li></ul></ul></ul><ul><ul><li>The development of a new core requires to write a C++ generator for a VHDL module using the RR library. The VHDL is not parametric; parameters are managed by the C++ executable to produce a completely defined VHDL module. </li></ul></ul>
    19. 19. Work in progress <ul><li>Definition of the graphical interface </li></ul><ul><ul><li>Based on QT libraries </li></ul></ul><ul><ul><li>Allows the visualization of cores, the setting of parameters, the connection of cores </li></ul></ul><ul><li>Definition of the netlist </li></ul><ul><ul><li>Representation of the modules and their interconnection </li></ul></ul><ul><ul><li>Based on XML Schemas </li></ul></ul><ul><ul><li>Data stored in the netlist: </li></ul></ul><ul><ul><ul><li>Modules data: parameters and pinout </li></ul></ul></ul><ul><ul><ul><li>Topology data: connections </li></ul></ul></ul><ul><ul><ul><li>Geometry data: positions and colors </li></ul></ul></ul><ul><li>Definition of the cache: </li></ul><ul><ul><li>DB structure and estimation engine: neural networks and regression models to extract data for unknown configurations of parameters of technologies </li></ul></ul>
    20. 20. Future work <ul><li>Future work </li></ul><ul><ul><li>Extension to the sw domain </li></ul></ul><ul><ul><ul><li>Managing of hw/sw interface </li></ul></ul></ul><ul><ul><ul><li>Refinement of the SystemC simulation model </li></ul></ul></ul><ul><ul><ul><li>… </li></ul></ul></ul><ul><ul><li>Definition of constraints related to error propagation </li></ul></ul><ul><li>Any proposal? </li></ul><ul><ul><li>Is this framework suitable for FPGA reconfiguration? </li></ul></ul><ul><ul><li>Are generator exploitable for this purpose? </li></ul></ul><ul><ul><li>… </li></ul></ul><ul><ul><li>What do you think about it? </li></ul></ul>
    21. 21. People <ul><li>Some references: </li></ul><ul><ul><li>Laura Frigerio </li></ul></ul><ul><ul><ul><li>[email_address] </li></ul></ul></ul><ul><ul><li>Fabio Salice </li></ul></ul><ul><ul><ul><li>[email_address] </li></ul></ul></ul><ul><ul><li>Carlo Brandolese </li></ul></ul><ul><ul><ul><li>[email_address] </li></ul></ul></ul><ul><ul><li>Cristiana Bolchini </li></ul></ul><ul><ul><ul><li>[email_address] </li></ul></ul></ul>

    ×