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A COMBINED SDC-SDF ARCHITECTURE FOR NORMAL I/O PIPELINED RADIX-2
FFT
ABSTRACT:
We present an efficient combined single-path delay commutator-feedback (SDC-
SDF) radix-2 pipelined fast Fourier transform architecture, which includes log2 N − 1 SDC
stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware
resource utilization by sharing the common arithmetic resource in the time-multiplexed
approach, including both adders and multipliers. Thus, the required number of complex
multipliers is reduced to log4 N − 0.5, compared with log2 N − 1 for the other radix-2 SDC/SDF
architectures. In addition, the proposed architecture requires roughly minimum number of
complex adders log2 N + 1 and complex delay memory 2N + 1.5 log2 N − 1.5.

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A combined sdc sdf architecture for normal i-o pipelined radix-2 fft

  • 1. A COMBINED SDC-SDF ARCHITECTURE FOR NORMAL I/O PIPELINED RADIX-2 FFT ABSTRACT: We present an efficient combined single-path delay commutator-feedback (SDC- SDF) radix-2 pipelined fast Fourier transform architecture, which includes log2 N − 1 SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced to log4 N − 0.5, compared with log2 N − 1 for the other radix-2 SDC/SDF architectures. In addition, the proposed architecture requires roughly minimum number of complex adders log2 N + 1 and complex delay memory 2N + 1.5 log2 N − 1.5.