Residue Number System is generally supposed to use co-prime moduli set. Non-coprime moduli sets are a
field in RNS which is little studied. That's why this work was devoted to them. The resources that discuss
non-coprime in RNS are very limited. For the previous reasons, this paper analyses the RNS conversion
using suggested non-coprime moduli set.
This paper suggests a new non-coprime moduli set and investigates its performance. The suggested new
moduli set has the general representation as {2n
–2, 2n
, 2n+2}, where n ∈ {2,3,…..,∞}. The calculations
among the moduli are done with this n value. These moduli are 2 spaces apart on the numbers line from
each other. This range helps in the algorithm’s calculations as to be shown.
The proposed non-coprime moduli set is investigated. Conversion algorithm from Binary to Residue is
developed. Correctness of the algorithm was obtained through simulation program. Conversion algorithm
is implemented.
A BINARY TO RESIDUE CONVERSION USING NEW PROPOSED NON-COPRIME MODULI SETcsandit
Residue Number System is generally supposed to use co-prime moduli set. Non-coprime moduli sets are a field in RNS which is little studied. That's why this work was devoted to them. The resources that discuss non-coprime in RNS are very limited. For the previous reasons, this paper analyses the RNS conversion using suggested non-coprime moduli set.
Fpga based efficient multiplier for image processing applications using recur...VLSICS Design
The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images
etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by
introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers
using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
compared to existing architectures.
An Area Efficient Vedic-Wallace based Variable Precision Hardware Multiplier ...IDES Editor
The complete architecture with the necessary blocks
and their internal structures are proposed in this paper. In
this algorithm the complete variable precision format is
utilized for the multiplication of the two numbers with a size
of nxn bits. The internal multiplier is choosen for m bit size
and is implemented using vedic-wallace structure for high
speed implementation. The architecture includes the
calculation of all the fields in the format for complete output.
The exponent of the final result is obtained by using carry
save adder for fast computations with less area utilization.
This multiplier uses the concept of MAC unit, giving rise to
more accurate results having a bits size of the final result will
be 2n2.
In this paper, a novel architecture of RNS based 1D Lifting Integer Wavelet Transform (IWT) has been introduced. Advantage of Residue Number System (RNS) based Lifting Scheme over RNS based Filter Bank and non-binary IWT has been discussed. The performance of traditional predicts and updates stage of binary Lifting Scheme (LS) for Discrete Wavelet Transform (DWT) generates huge carry propagation
delay, power and complexity. As a result non binary number system is becoming popular in the field of Digital Signal Processing (DSP) due to its efficient performance. In this paper also a new fixed number ROM based RNS division circuit has been proposed. The proposed architecture has been validated on Xilinx Vertex5 FPGA platform and the corresponding result and reports are shown in here.
Hardware/software co-design for a parallel three-dimensional bresenham’s algo...IJECEIAES
Line plotting is the one of the basic operations in the scan conversion. Bresenham’s line drawing algorithm is an efficient and high popular algorithm utilized for this purpose. This algorithm starts from one end-point of the line to the other end-point by calculating one point at each step. As a result, the calculation time for all the points depends on the length of the line thereby the number of the total points presented. In this paper, we developed an approach to speed up the Bresenham algorithm by partitioning each line into number of segments, find the points belong to those segments and drawing them simultaneously to formulate the main line. As a result, the higher number of segments generated, the faster the points are calculated. By employing 32 cores in the Field Programmable Gate Array, a line of length 992 points is formulated in 0.31μs only. The complete system is implemented using Zybo board that contains the Xilinx Zynq-7000 chip (Z-7010).
FAST AND EFFICIENT IMAGE COMPRESSION BASED ON PARALLEL COMPUTING USING MATLABJournal For Research
Image compression technique is used in many applications for example, satellite imaging, medical imaging, video where the size of the iamge requires more space to store, in such application image compression effectively can be used. There are two types in image compression techniques Lossy and Lossless comression. Both these techniques are used for compression of images, but these techniques are not fast. The image compression techniques both lossy and lossless image compression techniques are not fast, they take more time for compression and decompression. For fast and efficient image compression a parallel computing technique is used in matlab. Matlab is used in this project for parallel computing of images. In this paper we will discuss Regular image compression technique, three alternatives of parallel computing using matlab, comparison of image compression with and without parallel computing.
A High Speed Transposed Form FIR Filter Using Floating Point Dadda MultiplierIJRES Journal
There is a huge demand in high speed area efficient parallel FIR filter using floating point dadda algorithm, due to increase performance of processing units. Area and spped are usually confictiong constraints so that improving speed results mostly in large areas. In our research we will try to determine the best solution to this problem by comparing the results of different multipliers. Different sized of two algorithm for high speed hardware multipliers were studied and implemented ie.dadda and booth multipliers. The working of these two multipliers were studied and implementing each of them separately in VHDL. The results of this research will help us to choose the better option between multipliers for floating point multiplier for fabricating different system.
A BINARY TO RESIDUE CONVERSION USING NEW PROPOSED NON-COPRIME MODULI SETcsandit
Residue Number System is generally supposed to use co-prime moduli set. Non-coprime moduli sets are a field in RNS which is little studied. That's why this work was devoted to them. The resources that discuss non-coprime in RNS are very limited. For the previous reasons, this paper analyses the RNS conversion using suggested non-coprime moduli set.
Fpga based efficient multiplier for image processing applications using recur...VLSICS Design
The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images
etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by
introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers
using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
compared to existing architectures.
An Area Efficient Vedic-Wallace based Variable Precision Hardware Multiplier ...IDES Editor
The complete architecture with the necessary blocks
and their internal structures are proposed in this paper. In
this algorithm the complete variable precision format is
utilized for the multiplication of the two numbers with a size
of nxn bits. The internal multiplier is choosen for m bit size
and is implemented using vedic-wallace structure for high
speed implementation. The architecture includes the
calculation of all the fields in the format for complete output.
The exponent of the final result is obtained by using carry
save adder for fast computations with less area utilization.
This multiplier uses the concept of MAC unit, giving rise to
more accurate results having a bits size of the final result will
be 2n2.
In this paper, a novel architecture of RNS based 1D Lifting Integer Wavelet Transform (IWT) has been introduced. Advantage of Residue Number System (RNS) based Lifting Scheme over RNS based Filter Bank and non-binary IWT has been discussed. The performance of traditional predicts and updates stage of binary Lifting Scheme (LS) for Discrete Wavelet Transform (DWT) generates huge carry propagation
delay, power and complexity. As a result non binary number system is becoming popular in the field of Digital Signal Processing (DSP) due to its efficient performance. In this paper also a new fixed number ROM based RNS division circuit has been proposed. The proposed architecture has been validated on Xilinx Vertex5 FPGA platform and the corresponding result and reports are shown in here.
Hardware/software co-design for a parallel three-dimensional bresenham’s algo...IJECEIAES
Line plotting is the one of the basic operations in the scan conversion. Bresenham’s line drawing algorithm is an efficient and high popular algorithm utilized for this purpose. This algorithm starts from one end-point of the line to the other end-point by calculating one point at each step. As a result, the calculation time for all the points depends on the length of the line thereby the number of the total points presented. In this paper, we developed an approach to speed up the Bresenham algorithm by partitioning each line into number of segments, find the points belong to those segments and drawing them simultaneously to formulate the main line. As a result, the higher number of segments generated, the faster the points are calculated. By employing 32 cores in the Field Programmable Gate Array, a line of length 992 points is formulated in 0.31μs only. The complete system is implemented using Zybo board that contains the Xilinx Zynq-7000 chip (Z-7010).
FAST AND EFFICIENT IMAGE COMPRESSION BASED ON PARALLEL COMPUTING USING MATLABJournal For Research
Image compression technique is used in many applications for example, satellite imaging, medical imaging, video where the size of the iamge requires more space to store, in such application image compression effectively can be used. There are two types in image compression techniques Lossy and Lossless comression. Both these techniques are used for compression of images, but these techniques are not fast. The image compression techniques both lossy and lossless image compression techniques are not fast, they take more time for compression and decompression. For fast and efficient image compression a parallel computing technique is used in matlab. Matlab is used in this project for parallel computing of images. In this paper we will discuss Regular image compression technique, three alternatives of parallel computing using matlab, comparison of image compression with and without parallel computing.
A High Speed Transposed Form FIR Filter Using Floating Point Dadda MultiplierIJRES Journal
There is a huge demand in high speed area efficient parallel FIR filter using floating point dadda algorithm, due to increase performance of processing units. Area and spped are usually confictiong constraints so that improving speed results mostly in large areas. In our research we will try to determine the best solution to this problem by comparing the results of different multipliers. Different sized of two algorithm for high speed hardware multipliers were studied and implemented ie.dadda and booth multipliers. The working of these two multipliers were studied and implementing each of them separately in VHDL. The results of this research will help us to choose the better option between multipliers for floating point multiplier for fabricating different system.
Review and comparison of tasks scheduling in cloud computingijfcstjournal
Recently, there has been a dramatic increase in the popularity of cloud computing systems that rent
computing resources on-demand, bill on a pay-as-you-go basis, and multiplex many users on the same
physical infrastructure. It is a virtual pool of resources which are provided to users via Internet. It gives
users virtually unlimited pay-per-use computing resources without the burden of managing the underlying
infrastructure. One of the goals is to use the resources efficiently and gain maximum profit. Scheduling is a
critical problem in Cloud computing, because a cloud provider has to serve many users in Cloud
computing system. So scheduling is the major issue in establishing Cloud computing systems. The
scheduling algorithms should order the jobs in a way where balance between improving the performance
and quality of service and at the same time maintaining the efficiency and fairness among the jobs. This
paper introduces and explores some of the methods provided for in cloud computing has been scheduled.
Finally the waiting time and time to implement some of the proposed algorithm is evaluated
Design of High Speed and Low Power Veterbi Decoder for Trellis Coded Modulati...ijsrd.com
It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.
Evaluation of Huffman and Arithmetic Algorithms for Multimedia Compression St...IJCSEA Journal
Compression is a technique to reduce the quantity of data without excessively reducing the quality of the multimedia data.The transition and storing of compressed multimedia data is much faster and more efficient than original uncompressed multimedia data. There are various techniques and standards for multimedia data compression, especially for image compression such as the JPEG and JPEG2000 standards. These standards consist of different functions such as color space conversion and entropy coding. Arithmetic and Huffman coding are normally used in the entropy coding phase. In this paper we try to answer the following question. Which entropy coding, arithmetic or Huffman, is more suitable compared to other from the compression ratio, performance, and implementation points of view? We have implemented and tested Huffman and arithmetic algorithms. Our implemented results show that compression ratio of arithmetic coding is better than Huffman coding, while the performance of the Huffman coding is higher than arithmetic coding. In addition, implementation of Huffman coding is much easier than the arithmetic coding.
Implementation of an arithmetic logic using area efficient carry lookahead adderVLSICS Design
An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer.
And it is a digital circuit comprised of the basic electronics components, which is used to perform various
function of arithmetic and logic and integral operations further the purpose of this work is to propose the
design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this
study consist of following main functions like addition also subtraction, increment, decrement, AND, OR,
NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the
airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach.
The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU
can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
A Study of BFLOAT16 for Deep Learning TrainingSubhajit Sahu
Highlighted notes of:
A Study of BFLOAT16 for Deep Learning Training
This paper presents the first comprehensive empirical study demonstrating the efficacy of the Brain Floating Point (BFLOAT16) half-precision format for DeepLearning training across image classification, speech recognition, language model-ing, generative networks, and industrial recommendation systems. BFLOAT16 is attractive for Deep Learning training for two reasons: the range of values it can represent is the same as that of IEEE 754 floating-point format (FP32) and conversion to/from FP32 is simple. Maintaining the same range as FP32 is important to ensure that no hyper-parameter tuning is required for convergence; e.g., IEEE 754compliant half-precision floating point (FP16) requires hyper-parameter tuning. In this paper, we discuss the flow of tensors and various key operations in mixed-precision training and delve into details of operations, such as the rounding modes for converting FP32 tensors to BFLOAT16. We have implemented a method to emulate BFLOAT16 operations in Tensorflow, Caffe2, IntelCaffe, and Neon for our experiments. Our results show that deep learning training using BFLOAT16tensors achieves the same state-of-the-art (SOTA) results across domains as FP32tensors in the same number of iterations and with no changes to hyper-parameters.
Optimized Biometric System Based on Combination of Face Images and Log Transf...sipij
The biometrics are used to identify a person effectively. In this paper, we propose optimised Face
recognition system based on log transformation and combination of face image features vectors. The face
images are preprocessed using Gaussian filter to enhance the quality of an image. The log transformation
is applied on enhanced image to generate features. The feature vectors of many images of a single person
image are converted into single vector using average arithmetic addition. The Euclidian distance(ED) is
used to compare test image feature vector with database feature vectors to identify a person. It is
experimented that, the performance of proposed algorithm is better compared to existing algorithms.
TARGET LOCALIZATION IN WIRELESS SENSOR NETWORKS BASED ON RECEIVED SIGNAL STRE...sipij
We consider the problem of localizing a target taking the help of a set of anchor beacon nodes. A small
number of beacon nodes are deployed at known locations in the area. The target can detect a beacon
provided it happens to lie within the beacon’s transmission range. Thus, the target obtains a measurement
vector containing the readings of the beacons: ‘1’ corresponding to a beacon if it is able to detect the
target, and ‘0’ if the beacon is not able to detect the target. The goal is twofold: to determine the location
of the target based on the binary measurement vector at the target; and to study the behaviour of the
localization uncertainty as a function of the beacon transmission range (sensing radius) and the number of
beacons deployed. Beacon transmission range means signal strength of the beacon to transmit and receive
the signals which is called as Received Signal Strength (RSS). To localize the target, we propose a gridmapping
based approach, where the readings corresponding to locations on a grid overlaid on the region
of interest are used to localize the target. To study the behaviour of the localization uncertainty as a
function of the sensing radius and number of beacons, extensive simulations and numerical experiments
are carried out. The results provide insights into the importance of optimally setting the sensing radius and
the improvement obtainable with increasing number of beacons.
Review and comparison of tasks scheduling in cloud computingijfcstjournal
Recently, there has been a dramatic increase in the popularity of cloud computing systems that rent
computing resources on-demand, bill on a pay-as-you-go basis, and multiplex many users on the same
physical infrastructure. It is a virtual pool of resources which are provided to users via Internet. It gives
users virtually unlimited pay-per-use computing resources without the burden of managing the underlying
infrastructure. One of the goals is to use the resources efficiently and gain maximum profit. Scheduling is a
critical problem in Cloud computing, because a cloud provider has to serve many users in Cloud
computing system. So scheduling is the major issue in establishing Cloud computing systems. The
scheduling algorithms should order the jobs in a way where balance between improving the performance
and quality of service and at the same time maintaining the efficiency and fairness among the jobs. This
paper introduces and explores some of the methods provided for in cloud computing has been scheduled.
Finally the waiting time and time to implement some of the proposed algorithm is evaluated
Design of High Speed and Low Power Veterbi Decoder for Trellis Coded Modulati...ijsrd.com
It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.
Evaluation of Huffman and Arithmetic Algorithms for Multimedia Compression St...IJCSEA Journal
Compression is a technique to reduce the quantity of data without excessively reducing the quality of the multimedia data.The transition and storing of compressed multimedia data is much faster and more efficient than original uncompressed multimedia data. There are various techniques and standards for multimedia data compression, especially for image compression such as the JPEG and JPEG2000 standards. These standards consist of different functions such as color space conversion and entropy coding. Arithmetic and Huffman coding are normally used in the entropy coding phase. In this paper we try to answer the following question. Which entropy coding, arithmetic or Huffman, is more suitable compared to other from the compression ratio, performance, and implementation points of view? We have implemented and tested Huffman and arithmetic algorithms. Our implemented results show that compression ratio of arithmetic coding is better than Huffman coding, while the performance of the Huffman coding is higher than arithmetic coding. In addition, implementation of Huffman coding is much easier than the arithmetic coding.
Implementation of an arithmetic logic using area efficient carry lookahead adderVLSICS Design
An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer.
And it is a digital circuit comprised of the basic electronics components, which is used to perform various
function of arithmetic and logic and integral operations further the purpose of this work is to propose the
design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this
study consist of following main functions like addition also subtraction, increment, decrement, AND, OR,
NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the
airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach.
The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU
can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
A Study of BFLOAT16 for Deep Learning TrainingSubhajit Sahu
Highlighted notes of:
A Study of BFLOAT16 for Deep Learning Training
This paper presents the first comprehensive empirical study demonstrating the efficacy of the Brain Floating Point (BFLOAT16) half-precision format for DeepLearning training across image classification, speech recognition, language model-ing, generative networks, and industrial recommendation systems. BFLOAT16 is attractive for Deep Learning training for two reasons: the range of values it can represent is the same as that of IEEE 754 floating-point format (FP32) and conversion to/from FP32 is simple. Maintaining the same range as FP32 is important to ensure that no hyper-parameter tuning is required for convergence; e.g., IEEE 754compliant half-precision floating point (FP16) requires hyper-parameter tuning. In this paper, we discuss the flow of tensors and various key operations in mixed-precision training and delve into details of operations, such as the rounding modes for converting FP32 tensors to BFLOAT16. We have implemented a method to emulate BFLOAT16 operations in Tensorflow, Caffe2, IntelCaffe, and Neon for our experiments. Our results show that deep learning training using BFLOAT16tensors achieves the same state-of-the-art (SOTA) results across domains as FP32tensors in the same number of iterations and with no changes to hyper-parameters.
Optimized Biometric System Based on Combination of Face Images and Log Transf...sipij
The biometrics are used to identify a person effectively. In this paper, we propose optimised Face
recognition system based on log transformation and combination of face image features vectors. The face
images are preprocessed using Gaussian filter to enhance the quality of an image. The log transformation
is applied on enhanced image to generate features. The feature vectors of many images of a single person
image are converted into single vector using average arithmetic addition. The Euclidian distance(ED) is
used to compare test image feature vector with database feature vectors to identify a person. It is
experimented that, the performance of proposed algorithm is better compared to existing algorithms.
TARGET LOCALIZATION IN WIRELESS SENSOR NETWORKS BASED ON RECEIVED SIGNAL STRE...sipij
We consider the problem of localizing a target taking the help of a set of anchor beacon nodes. A small
number of beacon nodes are deployed at known locations in the area. The target can detect a beacon
provided it happens to lie within the beacon’s transmission range. Thus, the target obtains a measurement
vector containing the readings of the beacons: ‘1’ corresponding to a beacon if it is able to detect the
target, and ‘0’ if the beacon is not able to detect the target. The goal is twofold: to determine the location
of the target based on the binary measurement vector at the target; and to study the behaviour of the
localization uncertainty as a function of the beacon transmission range (sensing radius) and the number of
beacons deployed. Beacon transmission range means signal strength of the beacon to transmit and receive
the signals which is called as Received Signal Strength (RSS). To localize the target, we propose a gridmapping
based approach, where the readings corresponding to locations on a grid overlaid on the region
of interest are used to localize the target. To study the behaviour of the localization uncertainty as a
function of the sensing radius and number of beacons, extensive simulations and numerical experiments
are carried out. The results provide insights into the importance of optimally setting the sensing radius and
the improvement obtainable with increasing number of beacons.
The paper addresses the automation of the task of an epigraphist in reading and deciphering inscriptions.
The automation steps include Pre-processing, Segmentation, Feature Extraction and Recognition. Preprocessing
involves, enhancement of degraded ancient document images which is achieved through Spatial
filtering methods, followed by binarization of the enhanced image. Segmentation is carried out using Drop
Fall and Water Reservoir approaches, to obtain sampled characters. Next Gabor and Zonal features are
extracted for the sampled characters, and stored as feature vectors for training. Artificial Neural Network
(ANN) is trained with these feature vectors and later used for classification of new test characters. Finally
the classified characters are mapped to characters of modern form. The system showed good results when
tested on the nearly 150 samples of ancient Kannada epigraphs from Ashoka and Hoysala periods. An
average Recognition accuracy of 80.2% for Ashoka period and 75.6% for Hoysala period is achieved.
Automatic meal inspection system using lbp hf feature for central kitchensipij
This paper proposes an intelligent and automatic meal inspection system which can be applied to the meal
inspection for the application of central kitchen automation. The diet specifically designed for the patients are required with providing personalized diet such as low sodium intake or some necessary food. Hence,
the proposed system can benefit the inspection process that is often performed manually. In the proposed
system, firstly, the meal box can be detected and located automatically with the vision-based method and
then all the food ingredients can be identified by using the color and LBP-HF texture features. Secondly,
the quantity for each of food ingredient is estimated by using the image depth information. The experimental results show that the meal inspection accuracy can approach 80%, meal inspection efficiency can reach1200ms, and the food quantity accuracy is about 90%. The proposed system is expected to increase the capacity of meal supply over 50% and be helpful to the dietician in the hospital for saving the time in the diet inspection process.
A Hybrid Architecture for Tracking People in Real-Time Using a Video Surveill...sipij
This paper describes a novel method for tracking customers using images taken from video-surveillance
cameras. This system analyzes the number of customers and their motions through the aisles of big-box
stores (supermarkets) in real-time. The originality of our approach is based on the study of the blobs
properties for managing the splitting/merging issues using a mathematical morphology operator. In the
order hand, in order to manage a high number of customers in real-time, we combine the advantage of two
tracking algorithms.
Objective Quality Assessment of Image Enhancement Methods in Digital Mammogra...sipij
Breast cancer is the most common cancer among women worldwide constituting more than 25%
of all cancer incidences occurring in the world [1]. Statistics show that US, India and China
account for more than one third of all breast cancer cases [2]. Also, there has been a steady
increase in the breast cancer incidence among young generation in the world. In India, one out of
two women die after being detected with breast cancer where as in China it is one in four and in
USA it is one in eight [2]. Therefore, the statistics show that cancer mortality is highest in India
among all other nations in the world. In US, though the number of women diagnosed with cancer
is more than that in India, their mortality
FUZZY CLUSTERING BASED GLAUCOMA DETECTION USING THE CDR sipij
Glaucoma is a serious eye disease, overtime it will result in gradual blindness. Early detection of thedisease will help prevent against developing a more serious condition. A vertical cup-to-disc ratio which isthe ratio of the vertical diameter of the optic cup to that of the optic disc, of the fundus eye image is an important clinical indicator for glaucoma diagnosis. This paper presents an automated method for the extraction of optic disc and optic cup using Fuzzy C Means clustering technique combined with
thresholding. Using the extracted optic disc and optic cup the vertical cup-to-disc ratio was calculated.
The validity of this new method has been tested on 365 colour fundus images from two different publicly
available databases DRION, DIARATDB0 and images from an ophthalmologist. The result of the method
seems to be promising and useful for clinical work.
MULTIPLE OBJECTS TRACKING IN SURVEILLANCE VIDEO USING COLOR AND HU MOMENTSsipij
Multiple objects tracking finds its applications in many high level vision analysis like object behaviour
interpretation and gait recognition. In this paper, a feature based method to track the multiple moving
objects in surveillance video sequence is proposed. Object tracking is done by extracting the color and Hu
moments features from the motion segmented object blob and establishing the association of objects in the
successive frames of the video sequence based on Chi-Square dissimilarity measure and nearest neighbor
classifier. The benchmark IEEE PETS and IEEE Change Detection datasets has been used to show the
robustness of the proposed method. The proposed method is assessed quantitatively using the precision and
recall accuracy metrics. Further, comparative evaluation with related works has been carried out to exhibit
the efficacy of the proposed method.
Ultrasound images and SAR i.e. synthetic aperture radar images are usually corrupted because of speckle
noise also called as granular noise. It is quite a tedious task to remove such noise and analyze those
corrupted images. Till now many researchers worked to remove speckle noise using frequency domain
methods, temporal methods, and adaptive methods. Different filters have been developed as Mean and
Median filters, Statistic Lee filter, Statistic Kuan filter, Frost filter, Srad filter. This paper reviews filters
used to remove speckle noise.
A R EVIEW P APER : N OISE M ODELS IN D IGITAL I MAGE P ROCESSINGsipij
Noise is always presents in digital images during
image acquisition, coding, transmission, and proces
sing
steps. Noise is very difficult to remove it from t
he digital images without the prior knowledge of no
ise
model. That is why, review of noise models are esse
ntial in the study of image denoising techniques. I
n this
paper, we express a brief overview of various noise
models. These noise models can be selected by anal
ysis
of their origin. In this way, we present a complete
and quantitative analysis of noise models availabl
e in
digital images.
An Innovative Moving Object Detection and Tracking System by Using Modified R...sipij
The ultimate goal of this study is to afford enhanced video object detection and tracking by eliminating the
limitations which are existing nowadays. Although high performance ratio for video object detection and
tracking is achieved in the earlier work it takes more time for computation. Consequently we are in need to
propose a novel video object detection and tracking technique so as to minimize the computational
complexity. Our proposed technique covers five stages they are preprocessing, segmentation, feature
extraction, background subtraction and hole filling. Originally the video clip in the database is split into
frames. Then preprocessing is performed so as to get rid of noise, an adaptive median filter is used in this
stage to eliminate the noise. The preprocessed image then undergoes segmentation by means of modified
region growing algorithm. The segmented image is subjected to feature extraction phase so as to extract
the multi features from the segmented image and the background image, the feature value thus obtained
are compared so as to attain optimal value, consequently a foreground image is attained in this stage. The
foreground image is then subjected to morphological operations of erosion and dilation so as to fill the
holes and to get the object accurately as these foreground image contains holes and discontinuities. Thus
the moving object is tracked in this stage. This method will be employed in MATLAB platform and the
outcomes will be studied and compared with the existing techniques so as to reveal the performance of the
novel video object detection and tracking technique.
Efficient pu mode decision and motion estimation for h.264 avc to hevc transc...sipij
H.264/AVC has been widely applied to various applications. However, a new video compression standard,
High Efficient Video Coding (HEVC), had been finalized in 2013. In this work, a fast transcoder from
H.264/AVC to HEVC is proposed. The proposed algorithm includes the fast prediction unit (PU) decision
and the fast motion estimation. With the strong relation between H.264/AVC and HEVC, the modes,
residuals, and variance of motion vectors (MVs) extracted from H.264/AVC can be reused to predict the
current encoding PU of HEVC. Furthermore, the MVs from H.264/AVC are used to decide the search
range of PU during motion estimation. Simulation results show that the proposed algorithm can save up to
53% of the encoding time and maintains the rate-distortion (R-D) performance for HEVC.
A FLUXGATE SENSOR APPLICATION: COIN IDENTIFICATIONsipij
Today, coins are used to operate many electric devices that are open to the public service. Washing machines, play stations, computers, auto brooms, foam machines, beverage machines, telephone chargers, hair dryers and water heaters are some examples of these devices These devices include coin recognition systems. In these systems, there are coils at two different radius, which become electromagnets when the
current is passed through them. The AC current supplied to the coils creates a variable magnetic field, which induces the eddy current on the coil during the passing of money. The magnetic field generated by the Eddy current reduces the current passing through the coil. The amount of change of current in the coil gives information about the coin; the type of metal (element) and the amount of metal (element). In this
study, a new coin identification system (magnetic measurement system) is designed. In this system, the
magnetic anomaly generated by the coin as a result of applying direct current to the coils is tried to be
detected by fluxgate sensor. In this study, sensor voltages are acquired in computer environment by using
developed electronic unit and LabVIEW based software. In the paper, experimental results have been
discussed in detail.
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Nowadays, in the field of communications, AEC (acoustic echo cancellation) is truly essential with respect
to the quality of multimedia transmission. In this paper, we designed and developed an efficient AEC based
on adaptive filters to improve quality of service in telecommunications against the phenomena of acoustic
echo, which is indeed a problem in hands-free communications.The main advantage of the proposed algorithm is its capacity of tracking non-stationary signals such as acoustic echo. In this work the acoustic echo cancellation (AEC) is modeled using a digital signal
processing technique especially Simulink Blocksets. The algorithm’s code is generated in Matlab Simulink
programming environment. At simulation level, results of simulink implementation prove that module
behavior is realistic when it comes to cancellation of echo in hands free communication using adaptive algorithm.Results obtained with our algorithm in terms of ERLE criteria are confronted to IUT-T recommendation
G.168.
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routing (MRPR) algorithm selects most reliable routes and assign wavelengths to connections in a manner that utilizes the light path(LP) established efficiently considering all possible requests.
Stem calyx recognition of an apple using shape descriptorssipij
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drawback of existing apple grading techniques is that stem - calyx part of an apple is treated as defects,
this leads to poor grading of apples. In order to overcome this drawback, we proposed an approach to
recognize stem-calyx and differentiated from true defects based on shape features. Our method comprises
of steps such as segmentation of apple using grow-cut method, candidate objects such as stem-calyx and
small defects are detected using multi-threshold segmentation. The shape features are extracted from
detected objects using Multifractal, Fourier and Radon descriptor and finally stem-calyx regions are
recognized and differentiated from true defects using SVM classifier. The proposed algorithm is evaluated
using experiments conducted on apple image dataset and results exhibit considerable improvement in
recognition of stem-calyx region compared to other techniques.
INHIBITION AND SET-SHIFTING TASKS IN CENTRAL EXECUTIVE FUNCTION OF WORKING ME...sipij
Understanding of neuro-dynamics of a complex higher cognitive process, Working Memory (WM) is
challenging. In WM, information processing occurs through four subsystems: phonological loop, visual
sketch pad, memory buffer and central executive function (CEF). CEF plays a principal role in WM. In this
study, our objective was to understand the neurospatial correlates of CEF during inhibition and set-shifting
processes. Thirty healthy educated subjects were selected. Event-Related Potential (ERP) related to visual
inhibition and set-shifting task was collected using 32 channel EEG system. Activation of those ERPs
components was analyzed using amplitudes of positive and negative peaks. Experiment was controlled
using certain parametric constraints to judge behavior, based on average responses in order to establish
relationship between ERP and local area of brain activation and represented using standardized low
resolution brain electromagnetic tomography. The average score of correct responses was higher for
inhibition task (87.5%) as compared to set-shifting task (59.5%). The peak amplitude of neuronal activity
for inhibition task was lower compared to set-shifting task in fronto-parieto-central regions. Hence this
proposed paradigm and technique can be used to measure inhibition and set-shifting neuronal processes in
understanding pathological central executive functioning in patients with neuro-psychiatric disorders.
DETERMINATION OF BURIED MAGNETIC MATERIAL’S GEOMETRIC DIMENSIONSsipij
It is important to find buried magnetic material’s geometric features that are parallel to the soil surface in
order to determine anti-tank and anti-personnel mine compatible to standards. So that it is possible to
decrease the number of false alarms by separating the samples that have got non-standard geometries. For
this purpose, in this study the anomalies occurred at horizontal component of the earth’s magnetic field by
buried samples are determined with magnetic sensor. In the study, KMZ51 AMR is used as the magnetic
sensor. The position-controlled movement of the sensor along x-y axis is provided with 2D scanning system.
Trigger values of sensor output are evaluated with respect to the scanning field. The experiments are
redone for the samples at different geometries and variables are defined for geometric analysis. The
experimental conclusions obtained from this paper will be discussed in detail.
Comprehensive Performance Evaluation on Multiplication of Matrices using MPIijtsrd
In Matrix multiplication we refer to a concept that is used in technology applications such as digital image processing, digital signal processing and graph problem solving. Multiplication of huge matrices requires a lot of computing time as its complexity is O n3 . Because most engineering science applications require higher computational throughput with minimum time, many sequential and analogue algorithms are developed. In this paper, methods of matrix multiplication are elect, implemented, and analyzed. A performance analysis is evaluated, and some recommendations are given when using open MP and MPI methods of parallel of latitude computing. Adamu Abubakar I | Oyku A | Mehmet K | Amina M. Tako ""Comprehensive Performance Evaluation on Multiplication of Matrices using MPI""
Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-4 | Issue-2 , February 2020,
URL: https://www.ijtsrd.com/papers/ijtsrd30015.pdf
Paper Url : https://www.ijtsrd.com/engineering/electrical-engineering/30015/comprehensive-performance-evaluation-on-multiplication-of-matrices-using-mpi/adamu-abubakar-i
The use of reversible logic gates in the design of residue number systems IJECEIAES
Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2 k p , 2 -1}. Modulo 2 n -1, 2 n , and 2 n +1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2 n -1, 2 n+k n , 2 +1} have been designed. The proposed RNS- based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.
CONFIGURABLE TASK MAPPING FOR MULTIPLE OBJECTIVES IN MACRO-PROGRAMMING OF WIR...ijassn
Macro-programming is the new generation advanced method of using Wireless Sensor Network (WSNs), where application developers can extract data from sensor nodes through a high level abstraction of the system. Instead of developing the entire application, task graph representation of the WSN model presents simplified approach of data collection. However, mapping of tasks onto sensor nodes highlights several problems in energy consumption and routing delay. In this paper, we present an efficient hybrid approach of task mapping for WSN – Hybrid Genetic Algorithm, considering multiple objectives of optimization – energy consumption, routing delay and soft real time requirement. We also present a method to configure the algorithm as per user's need by changing the heuristics used for optimization. The trade-off analysis between energy consumption and delivery delay was performed and simulation results are presented. The algorithm is applicable during macro-programming enabling developers to choose a better mapping according to their application requirements.
CONFIGURABLE TASK MAPPING FOR MULTIPLE OBJECTIVES IN MACRO-PROGRAMMING OF WIR...ijassn
Macro-programming is the new generation advanced method of using Wireless Sensor Network (WSNs),
where application developers can extract data from sensor nodes through a high level abstraction of the
system. Instead of developing the entire application, task graph representation of the WSN model presents
simplified approach of data collection.
Faster Interleaved Modular Multiplier Based on Sign DetectionVLSICS Design
Data Security is the most important issue nowadays. A lot of cryptosystems are introduced to provide security. Public key cryptosystems are the most common cryptosystems used for securing data communication. The common drawback of applying such cryptosystems is the heavy computations which degrade performance of a system. Modular multiplication is the basic operation of common public key cryptosystems such as RSA, Diffie-Hellman key agreement (DH), ElGamal and ECC. Much research is now
directed to reduce overall time consumed by modular multiplication operation. Abd-el-fatah et al. introduced an enhanced architecture for computing modular ultiplication of two large numbers X and Y modulo given M. In this paper, a modification on that architecture is introduced. The proposed design computes modular multiplication by scanning two bits per iteration instead of one bit. The proposed design for 1024-bit precision reduced overall time by 38% compared to the design of Abd-el-fatah et al.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Manifold Blurring Mean Shift algorithms for manifold denoising, report, 2012Florent Renucci
(General) To retrieve a clean dataset by deleting outliers.
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Highly Reliable Parallel Filter Design Based On Reduced Precision Error Corre...iosrjce
The project is mainly focusing on multiple error detection and correction. Digital filters are widely
used in signal processing and communication n systems. In some cases, the reliability of those systems is critical
and fault tolerant implementations are needed. So that, the idea is generalized to show that parallel FIR filters
can be protected using error correction codes. Triple Modular Redundancy (TMR) is the traditional mitigation
techniques for Field-Programmable Gate Arrays (FPGAs) subject to Single-Event Upsets (SEUs) in high
radiation environment. To overcome the problem, in our project we propose RFFF (Reduced Faultless FIR
Filter) is a technique combined with TMR used to multiple errors are detected and corrected. TMR increases
the parameters like area, power and delay. In RFFF, multiple errors are corrected and the comparison of parameters like area, power and delay of existing and the proposed technique is done
Hardware Implementations of RS Decoding Algorithm for Multi-Gb/s Communicatio...RSIS International
In this paper, we have designed the VLSI hardware for a novel RS decoding algorithm suitable for Multi-Gb/s Communication Systems. Through this paper we show that the performance benefit of the algorithm is truly witnessed when implemented in hardware thus avoiding the extra processing time of Fetch-Decode-Execute cycle of traditional microprocessor based computing systems. The new algorithm with less time complexity combined with its application specific hardware implementation makes it suitable for high speed real-time systems with hard timing constraints. The design is implemented as a digital hardware using VHDL
Architecture neural network deep optimizing based on self organizing feature ...journalBEEI
Forward neural network (FNN) execution relying on the algorithm of training and architecture selection. Different parameters using for nip out the architecture of FNN such as the connections number among strata, neurons hidden number in each strata hidden and hidden strata number. Feature architectural combinations exponential could be uncontrollable manually so specific architecture can be design automatically by using special algorithm which build system with ability generalization better. Determination of architecture FNN can be done by using the algorithm of optimization numerous. In this paper methodology new proposes achievement where FNN neurons respective with hidden layers estimation work where in this work collect algorithm training self organizing feature map (SOFM) with advantages to explain how the best architectural selected automatically by SOFM from criteria error testing based on architecture populated. Different size of dataset benchmark of 4 classifications tested for approach proposed.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
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Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
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The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
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All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
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Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
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💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
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👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
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LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
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During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
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Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
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Encryption in Microsoft 365 - ExpertsLive Netherlands 2024
A BINARY TO RESIDUE CONVERSION USING NEW PROPOSED NON-COPRIME MODULI SET
1. Signal & Image Processing : An International Journal (SIPIJ) Vol.7, No.3, June 2016
DOI : 10.5121/sipij.2016.7301 1
A BINARY TO RESIDUE CONVERSION USING
NEW PROPOSED NON-COPRIME MODULI SET
Mansour Bader1
, Andraws Swidan2
, Mazin Al-hadidi3
and Baha Rababah4
1,2
Department of Computer Engineering, Jordan University, Amman, Jordan
3
Department of Computer Engineering, Al-Balqa'a Applied University, Salt, Jordan
4
Department of Computer Engineering, University of Portsmouth, Portsmouth, UK
ABSTRACT
Residue Number System is generally supposed to use co-prime moduli set. Non-coprime moduli sets are a
field in RNS which is little studied. That's why this work was devoted to them. The resources that discuss
non-coprime in RNS are very limited. For the previous reasons, this paper analyses the RNS conversion
using suggested non-coprime moduli set.
This paper suggests a new non-coprime moduli set and investigates its performance. The suggested new
moduli set has the general representation as {2n
–2, 2n
, 2n
+2}, where n ∈{2,3,…..,∞}. The calculations
among the moduli are done with this n value. These moduli are 2 spaces apart on the numbers line from
each other. This range helps in the algorithm’s calculations as to be shown.
The proposed non-coprime moduli set is investigated. Conversion algorithm from Binary to Residue is
developed. Correctness of the algorithm was obtained through simulation program. Conversion algorithm
is implemented.
KEYWORDS
Forward Conversion, Residue Number System, Non-coprime Moduli Set
1. INTRODUCTION
Residue number system (RNS) is a subfield of finite field arithmetic [1]. It is widely used in
digital signal processing, image processing, FIR (Finite Impulse Response) filters, and IIR
(Infinite Impulse Response) filters because it is a carry-free system and high efficient in addition
and multiplication [2]. So, residue number system is used by most applications that need a high
degree of concurrency. A lot of researches in computer systems are enthusiastic to go through
residue numbering system because of its characteristics such as, error detection and correction
(fault tolerant) [3], modularity, and embedded parallelism.
RNS allows dividing a large number into smaller sub numbers. Numbers are represented by
tipples which need less number of bits. The bits can be processed individually and in parallel
without carry between them. This improves computation time and simplifies hardware
implementation cost.
RNS has also the following advantages over conventional binary number system:
• Reducing the hardware complexity because the system is implemented by designing
smaller processing units.
2. Signal & Image Processing : An International Journal (SIPIJ) Vol.7, No.3, June 2016
2
• Improving the speed of operations since all of the tasks are performed in parallel.
• Efficient realization of the various building blocks needed such as adders, multipliers.
• The absence of carry propagation between the modulus channels makes the RNS
appealing for building parallel fast processors. This facilitates the realization of high-
speed, low-power arithmetic. This advantage is of paramount importance in embedded
processors, especially those found in portable devices, for which power consumption is
the most critical aspect of the design [4].
Because of these features, computer arithmeticians have historically promoted the RNS for high-
speed arithmetic-intensive applications [5].
The rest of this paper is organized as follows. In Section 2, overview of the new algorithm of
forward conversion is proposed. Section 3 presents the new non-coprime realization of the
proposed forward converter. The hardware implementation of the moduli set is presented in
section 4, while the paper is concluded in Section 5.
2. NEW ALGORITHM OF THE FORWARD CONVERSION OVERVIEW
In working with RNS the following three main terminologies are used:
1. Moduli set: defined in terms of relatively prime moduli where the ith
modulus presented
by m୧ and the gcd൫m୧, m୨൯ = 1, j ≠ i, i = 1,2, … , n. Numerous moduli sets can be
used. The characteristics of RNS based systems depend on the moduli set chosen.
2. Dynamic range (M): this is equal to the product of mi terms; M = ∏ m୧
୬
୧ୀଵ , and denotes
the interval of integers that can be represented uniquely in the RNS using the specific
moduli set.
3. Residues: to represent any number X in RNS we find x୧ = X mod m୧ for all m୧ moduli.
The number is represented as X = xଵ, xଶ, xଷ.
RNS based processing units are generally composed of: Forward convertor, arithmetic and logic
unit (ALU) and a reverse convertor shown in figure 1 [6].
Conversion from Binary to Residue is called forward conversion. This conversion is used in order
to process numbers in Residue format, because it is faster and it is easier for human being
understood. To use the Residue Number System efficiently one has to interface it with the real
world, the numbers should be converted from usual representation either binary or analog to
residue representation, this is the first step in using RNS. This step is a very complex and
demanding process, which acts as an academic challenge that restrict the use of RNS in many
practical applications. Many researches conducted to find the most efficient algorithm, hardware
architectures and schemes either using special or arbitrary moduli sets in the implementation of
forward convertors in RNS.
In the forward translation of a binary number to its RNS equivalent, one of the most trivial,
classical expensive ways is to store all the residues and recall them based on the value of the
binary input.
3. Signal & Image Processing : An International Journal (SIPIJ) Vol.7, No.3, June 2016
3
Using the fact that the number can be represented as:
ܺ = ݔିଵ ݔିଶ … ݔଵݔ = ∑ ݔ2ିଵ
ୀ (1)
Figure 1. Block diagram of RNS based processing.
It is clear that this is a memory consuming process where you have to store all values in a lookup
table that typically consists of ROM, and for complex applications that require large number
representation, the size of memory will increase dramatically and thus increasing the cost.
The other implementation is to have special moduli set representation used in the conversion
process, consist of three, four, or five bits, the design of these convertors is based on using carry
save adder (CSA).
2.1. Non-coprime Moduli Sets Overview
Initially, only RNS with co-prime moduli set was investigated and used. Non-coprime had drawn
the attention of research only lately. Thus the knowledge of non-coprime characteristics has been
obtained from the co-prime one's as going to be seen through this chapter sections.
It is relatively easy to convert even numbers into their residue numbers representation. Numbers
as 2n
, like 16 which is pow(2,4) or in form that we are familiar with now 24
, and 14 which is 24
–
2 and 18 which is 24
+2, are not co-primed with each other since there is a common factor
between them which is number 2.
The usual way to compute a mod m is to take the remainder after integer division. This is straight
forward when the operands are within the range of the available divide hardware, but the divide
operation is known to be a slow arithmetic operation. Some small microcontrollers have no divide
4. Signal & Image Processing : An International Journal (SIPIJ) Vol.7, No.3, June 2016
4
hardware, and it is occasionally necessary to divide very large numbers outside the range that can
be done using the available hardware [7].
It can be faster to take the modulus directly than to use the divide instruction when the
modulus m is constant, even where there is a hardware divide instruction. Rules of divisibility
mentioned in table 1 become even more valuable on machines without a hardware divide
instruction or where the numbers involved are out of range.
Table 1. Some of divisibility check rules applied to decimal system.
Divisibility by n Check
10 The least significant decimal digit is zero.
2 The least significant decimal digit is even.
5 The least significant decimal digit is 0 or 5
3 Sum of the decimal digits is divisible by 3.
9 Sum of the decimal digits is divisible by 9
2.2. Some Math Identities Review
2.2.1. Single General Rule
All divisibility check rules mentioned in table 1 are actually special cases of a single general rule.
Given that:
a is represented in number base b
a mod m = ( (b mod m)(a/b) + (a mod b) ) mod m
In the case of divisibility by 2, 5 and 10 for base 10, the term (b mod m) is zero because 2, 5 and
10 all divide evenly into 10. As a result, the divisibility test simplifies to asking whether
(a mod b), that is, the least significant digit of the number, is evenly divisible.
In the case of divisibility by 3 or 9 in base 10, the term (b mod m) is one. As a result, the
multiplier for the first term is one. Applying the formula recursively leads to the simple sum of
the digits [7].
2.2.2. The Trivial Case: Mod 2, Mod 4, Mod 2n
Computing modulus for powers of two is trivial on a binary computer, the term (b mod m) is
zero, so we just take the modulus by examining the least significant i bits of the binary
representation:
a mod 2i = a & (2i –1)
Thus, for a mod 2, we use a & 1, for a mod 4, we use a & 3, and for a mod 8, we use a & 7.
Recall that the & operator means logical and. When applied to integers, this computes each bit of
the result as the and of the corresponding bits of the operands. For all nonzero positive integers i,
5. Signal & Image Processing : An International Journal (SIPIJ) Vol.7, No.3, June 2016
5
the binary representation of 2i
–1 consists of i consecutive one bits, so anding with 2i
–1 preserves
the least significant i bits of the operand while forcing all more significant bits to zero [7].
The problem is more interesting when the modulus is not a power of two only.
2.2.3. Mersenne’s Number: Mod 3, Mod 7, Mod 2n
-1
In mathematics, a Mersenne prime is a prime number that is one less than a power of two, i.e.
2n
-1. That is, it is a prime number that can be written in the form Mn = 2n
− 1 for some integer n.
They are named after Marin Mersenne, a French Minim friar, who studied them in the early 17th
century [8].
Consider the problem of computing a mod 3 in binary number system. Note that 4 mod 3 is 1, so:
a mod 3 = ( (a/4) + (a mod 4) ) mod 3
That is, a mod 3 can be computed from the sum of the digits of the number in base 4. Base 4 is
convenient because each base 4 digit of the number consists of 2 bits of the binary represenation;
thus a mod 4 can be computed using a & 3 and a / 4 can be computed using a >> 2.
The number 3 is a Mersenne number, that is, one less than a power of two. The property noted
above is true of all Mersenne numbers. Thus, we can compute a mod 7 or a mod 15 on a binary
computer using:
a mod 7 = ( (a/8) + (a mod 8) ) mod 7
a mod 15 = ( (a/16) + (a mod 16) ) mod 15
Recall that a >> b shifts the binary representation of a left a total of b places. As with logical and,
this is a very inexpensive operation on a binary computer, and the effect is the same as
dividing a by 2b [7].
In this paper the problem is more interesting when the modulus is in a different shape of a power
of two, where it is in Mod (2n
– 2), Mod (2n
+ 2) consequently as a new moduli set proposed
along with Mod (2n
), that are going to be discussed in the next section.
Our work is done by suggesting the new moduli set {2n
– 2, 2n
, 2n
+ 2} and proposing new
conversion algorithms upon this new non-coprime moduli set. The next coming section will
discuss the background of non-coprime moduli sets.
2.3. Our New Non-coprime Moduli Set Overview
As its name shows "non-coprime" means the non-coprimality among its modulus numbers. Non-
coprime moduli sets can be used for error detection and correction purposes [9]. This non-
coprimality could be shown in theorems and by examples to prove them too.
Observation 1: 2k
− 2 is not relatively prime to 2k
, where k is a positive natural number.
It is obvious that 1 is not the only prime divisor of 2k
and 2k
– 2, since they are both even and 2k
–
2 is a multiple of 2 (i.e. a number multiplied by 2). Thus, there is a common divisor of them
rather than 1, which is number 2 in this case. So 2k
−2 is not relatively prime to 2k
.
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6
Example 1:
Let us take K = 4, in this case the two numbers of the theorem one would be 16 and 14
consequently, and it is obvious that there is a common divisor which is 2 between them when we
try to bring them back to their elementary elements.
Observation 2: 2k
+ 2 is not relatively prime to 2k
, where k is a positive natural number.
It is obvious that 1 is not the only prime divisor of 2k
and 2k
+ 2 , since they are both even and 2k
+ 2 is a multiple of 2 (i.e. a number multiplied by 2). Thus, there is a common divisor of them
other than 1, which is number 2 in this case. So 2k
+2 is not relatively prime to 2k
.
Example2:
Again let us take k = 4, in this case the two numbers of the theorem two would be 16 and 18
consequently, and it is obvious that there is a common divisor which is 2 between them when we
try to bring them back to their elementary elements.
2.4. Properties of Non-coprime Moduli Set
2.4.1 Dynamic Range of Our Non-coprime Moduli Set
This property of having a common divisor other than number 1 led to the non-coprime moduli set
when gathering the two theorems above. Based on these theorems the moduli set {2n - 2, 2n, 2n +
2} is non-coprime. The dynamic range of co-prime moduli set (M) is equal to M = ∏ m୧
୬
୧ୀଵ . In
the non-coprime case it is M = (∏ m୧
୬
୧ୀଵ )/4, it is 1/4 of the size of the co-primed one {2n – 1,
2n, 2n + 1}. This quarter comes from the multiplication of the common divisor (i.e. 2) between its
modulus numbers leading to number 4 which can not be multiplied to form the usual (M), thus its
size is less than the co-prime one. However it is important to know other characteristics such as
its uniqueness and bits representation.
Definition [9]: We define a non-prime moduli set as (ml, ..., mk), where gcd (mi,mj) = l may not
be satisfied for some i and j. The least common multiple of the moduli (m1, ..., mk), denoted as:
M = lcm(m1, ..., mk), is the dynamic range of (m1, ..., mk) . For any decimal number y∈[O, M –
1), y has a unique representation as (y1, ...,yk), where y = yi mod mi, 0 ≤ yi< mi.
If the residue number (y1, ...,yk) is consistent, the decimal number it represents can be found
using the CRT theorem, where M = lcm(m1, ..., mk) [9].
To find M through a formula as the one of the co-prime, we suggest the following formula due to
the special non-coprime moduli set:
M = (∏ m୧
୬
୧ୀଵ )/4 (2)
2.4.2 Uniqueness Verification
After dealing with the major and most important part of RNS in the previous section, it is
important to discuss the moduli set uniqueness when converted from decimal form (as we see it)
into RNS form (as to be implemented). In this section a mathematical proof is going to be
presented powered by table 2 to show the uniqueness itself.
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7
As a mathematical proof, we already know that 6, 8 and 10 are not co-primed with each other, in
this case the LCM should be used as the previous section showed. Thus we have to return them
back into their fundamental factors, for 6 which equal 2*3, for 8 it equals 23 and for 10 it is 2*5,
now by taking the non common numbers without repetition and multiplying them we see that:
3*23*5 which equals 120, so M = 120. This is true for all other moduli sets chosen with the form
(2n-2 ,2n, 2n +2), and this is the non-coprime moduli set that we have got and found our research
on it for thesis level responsibilities, since the pre-moduli value (i.e. 2n -2) and the post moduli
one (i.e. 2n +2) are multiples of 2 and are un-coprimed with each other, but they are co-prime
with each other without it (as in 3 and 5 for the example above, when neglecting the
multiplication of them with number 2). This fact is also true for all other moduli sets used; this is
because they are 2 numbers relatively co-primed with each other and they are always odd.
The uniqueness interval was verified by simulation program, the results of a program using the
moduli set (6,8,10) was simulated, at which each iteration is repeated every 6*8*10/4 times,
which is in this case the number 120 (that is ‘M’ for the moduli set itself), and thus the
uniqueness is guaranteed under the non-coprime moduli set within its dynamic range.
3. FORWARD CONVERSION ALGORITHM
This section has three sub sections of it as the number of the modulus numbers forming the
moduli set are three.
3.1 Pre-modulus Algorithm Implementation
The binary representation led to this part's discovery, since its values are prime after dividing it by
2. We will give you how it works in words first then the algorithm of calculation
|X|2n
-2 can be represented in figure 1.
The idea of its binary cutting circles around the common factor which is number 2 in this case, as
the previous sections showed that after dividing the pre number by the common factor the result
is 2n-1
– 1. Since the pre value has a 2n
– 2 shape, then the cut of its binary representation would
be in (n cut at the beginning as the co-prime algorithm did, but for the rest part it is taken (n-1)
each time) starting from LSB again.
3.2 Middle-modulus Part Algorithm
No change is done on it, so we refer you to [15] – [17] where obtaining the residue of X with
respect to modulus 2n
is the easiest operation.
3.3 Post-modulus Algorithm Implementation
The binary representation led to its working algorithm, since its value is prime after dividing it by
2. Again we will give you how it works in words first then we will put them in the flowchart of
figure 2 to easily understand it.
The idea of its binary cutting circles around the common factor which is number 2 in this case, as
the pre-modulus section showed. Here dividing the post number by the common factor the result
is 2n
-1 + 1, and since the post value has a 2n
+ 2 shape, then the cut of its binary representation
would be in (n cut at the beginning as the co-prime algorithm did, but for the rest parts it is taken
(n-1) each time) starting from LSB again as the pre-modulus did, some examples will show how
this is done.
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8
yes
else
yes
else
Figure 1. Computing the residue with respect to 2
n
-2.
Are bits left
after the cut
> n-1
Is final value ≥
pre-modulus
Divide these L-bits into parts of length n-bits at
the first cut, then (n-1) for the remaining parts
and save each part alone
Number in decimal format
Adding the parts in binary version addition
Final result of
modulus 2
n
- 2
Bit-rewiring to be in binary shape of L-bits
length
n-1 parts are to be shifted to left by one
element before adding them to the n-bits cut
Subtracting pre-
modulus value,
making result of
length n
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9
yes
else
yes
else
Figure 2. Computing the residue with respect to 2n+2.
Are bits left
after the cut
> n-1
Is final value
≥post-modulus
Divide these L-bits into parts of length n-
bits at the first cut, then (n-1) for the
remaining parts and save each part alone
Number in decimal
format
Adding the parts in binary version addition
Final result of
modulus 2n + 2
Bit-rewiring to be in binary shape of
L-bits length
n-1 parts are to be shifted to left by one
element before adding them to the n-bits cut
Subtracting
post-modulus
value, making
result of length
n
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4. ALGORITH IMPLEMENTATION
In this section the implementation of the new non-coprime moduli set converter's implementation
is done through hardware block diagrams. As described in the previous section, the converter has
3 stages of computing the modulus; they are (pre-modulus '2n
– 2', middle modulus '2n
' and post-
modulus '2n
+ 2'). So this section also consists of three hardware implementation blocks of them.
4.1 Pre-modulus Hardware Implementation
From the proposed algorithm presented for the pre-modulus calculation discussed in the flowchart
of figure 1, we can come with this block diagram for the hardware design of it in figure 3.
Notice that the start for cutting is from LSB side to the MSB. The DR for any n value is
calculated as was shown in formula (2), thus any number inside the range of M has 3 part cuts -at
most-. For example let n = 5, M = 15*32*17 = 8160, so the numbers inside the DR are
{0,1,2,……,8159}. However 8159 is represented in binary form as (1111111011111) which
consist of 13 digits and it is equal to 5 + 4 + 4 as the cuts presented by its algorithm showed. This
is true for all n values, so we will name the first n-bits cut A, the second (n-1) bits cut B and the
final part of (n-1) bits is C.
3n-2 Input X
C B A
(n-1) n
1
(n-1)
n
1
n
Figure 3. Calculation of Pre-modulus (2n
– 2).
4.2 Middle-modulus Hardware Implementation
No change is done on it, so we refer you to [15]-[17]. Obtaining the residue of X with respect to
modulus 2n
is the easiest operation. Block diagram of it is shown in figure 4.
(n-1) bits (n-1) bits n-bits
Full Adder
Full Adder
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11
3n-2 Input X
n
Figure 4. Calculation of Middle-modulus (2n).
4.3 Post-modulus Hardware Implementation
From the proposed algorithm presented for the post-modulus (2n
+ 2) calculation discussed in the
flowchart of figure 2, we can come with this block diagram for the hardware design of it in figure
5.
Notice that the start for cutting is from LSB side to the MSB. The DR for any n value is
calculated as was shown in formula (2), thus any number inside the range of M has 3 part cuts -at
most-. For example let n = 5, M = 15*32*17 = 8160, so the numbers inside the DR are
{0,1,2,……,8159}. However 8159 is represented in binary form as (1111111011111) which
consists of 13 digits and it is equal to 5 + 4 + 4 as the cuts presented by its algorithm showed.
This is true for all n values, so we will name the first n-bits cut A, the second (n-1) bits cut B and
the final part of (n-1) bits is C.
C B A
(n-1) bits n-bits
(n-1) bits 1
n-bits
1
n -bits
n-bits
Figure 5. Calculation of Post-modulus (2n + 2).
(n-1) bits (n-1) bits n-bits
Additive
inverse
X input of size (3n-2)
Full Adder
Full Adder
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5. CONCLUSIONS
A new non-coprime moduli set has been proposed. A general formula for the dynamic range was
derived. Algorithm of the special non-coprime moduli set has been suggested. The uniqueness for
the new special non-coprime moduli set just as the co-prime one's among DR has been verified.
This research revealed that non-coprime moduli set may be suitable for wide variety of cases not
limited to co-prime only.
ACKNOWLEDGEMENTS
The authors would like to thank everyone.
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AUTHORS
Mansour Bader holds a MSc in computer engineering and networks, University of
Jordan, Jordan, 2016. BSc Computer Engineering, Al-Balqa Applied University,
Jordan, 2008. He is a technical support engineer of computer networks at computer
center of Al-Balqa Applied University for 8 years and a half.
Dr. Andraws I. Swidan was born in Al-Karak Jordan in 1954. He received his
diploma in Computer Engineering (with honours) and Ph.D. in Computer Engineering
from LETI Ulianov Lenin, Sanct Peterburg (Leningrad), Russia in 1979 and 1982
respectively. He Joined the Electrical Engineering Department at the University of
Jordan in 1983 and was one of the founders of the Computer Engineering Department
at the University of Jordan in 1999. Since then he is a professor at the department. He
is also an Adjunct Professor with the ECE department of the McGill University,
Montreal, Canada. He holds several technical certifications among which the CISSP. He is an IEEE
member, Jordanian Engineering Association member Quebec College of engineers member. He is a Canada
Professional Engineer (The province of Quebec). He was member of several national and international
scientific committees. He holds several patents and tens of publications. His main areas of research interest
are: computer arithmetic, computer security, encryption algorithms.
Mazin Al-hadidi has PhD. in Engineering Science (Computing Machines, Systems
and Networks), Institute of Problems of Simulation in Power Engineering Academy
of Science, Ukraine/Kiev .1990-1994, with grade Excellent. Bachelor and Master
Degrees in Engineering (Computer and intellectual systems and networks) Kiev
Institute of Civil Aviation Engineers, as a governmental scholarship, Soviet Union /
Kiev, 1984-1990, with grade very good. General Secondary 12 Years Certificate in
the Science branch, Jordan/Al-Salt, 1984, with grade very good.
Baha Rababah has a MSc of computer network administration and management
(with Distinction), University of Portsmouth, UK, 2015. BSc Computer Engineering,
Al-Balqa Applied University, Jordan, 2010. He is a lecturer of computer networks
subjects in Keys Training and Solution, Irbid, Jordan.