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A 13b SAR ADC with Eye-opening VCO Based Comparator
- 1. A 13b SAR ADC with Eye-opening VCO Based Comparator Kentaro Yoshioka and Hiroki Ishikuro Keio University, Japan K Yoshioka 1/26
- 2. Overview Motivation Low power techniques for high resolution SAR ADCs C-DAC Comparators Proposed technique VCO comparator Eye-opening operation Measurement results Conclusions K Yoshioka 2/26
- 3. Motivation Low power and high resolution ADCs required Medical devices Sensors for “internet of things” Wearable devices and etc. Target: SNDR >65dB SAR ADC 0 50 100 150 200 250 2013 2014 2015 2016 2017 2018 IoTMarketinJapan[B$] http://www.idc.com/ K Yoshioka 3/26
- 4. SAR ADC building blocks and challenges Main SAR ADC building blocks VIN S/H Logic C-DAC Digital Power increases linearly C-DAC Mismatch requirements kT/C Comparators Noise SAR ADC and high resolution challenges K Yoshioka 4/26
- 5. Overview Background Low power techniques for high resolution SAR ADCs C-DAC Comparators Proposed technique VCO comparator Eye-opening operation Measurement results Conclusions K Yoshioka 5/26
- 6. Low power techniques for C-DAC Digital calibration to compensate mismatch [1] Sub-binary radix Can size C to match kT/C noise 1.8N-1C 1.8C C C Vin SAR Logic CLK Transfer Function With MSB mismatch [1] W. Liu, ISSCC 2010 Calibration Circuit ADCOUT K Yoshioka 6/26
- 7. Challenges for comparators Dynamic comparators typically used in SAR ADCs Noise suitable for 10-bit SAR Lower noise obtained by cascading amplifiers For 1-bit improvement, power increases 4x Latch CLK CLK Noise Power Total Power Dynamic comp. 240uVrms 1 1 x 10=10 (10-bit) Low noise comp. 30uVrms 64 64 x 13 = 832(13-bit) + - + - + - Latch K Yoshioka 7/26
- 8. Data driven noise reduction [2] Event when Δvin < LSB occur only once in SA cycle Comparator noise requirements relaxed at other cycles DAC Dvin 4LSB LSB 3LSB 2LSB Dvin=|Vinp-Vinn| [2] P. Harpe, ISSCC 2013 K Yoshioka 8/26
- 9. Majority voting for noise reduction Majority voting done when ΔVin is small Noise will be 𝟏 𝑵 (N: number of votes) N time Voting TDC Vin CLK OUT Optimum N different Single guess Voting Vin CLK OUT Voting DVin<LSB DVin<3LSB K Yoshioka 9/26
- 10. Our goal Scale the comparator power v.s. DVin Reduce the total comparator power Comp.Power Δvin2 LSBLSB Low-noise comp. Majority Voting This work 64 16 8 LSB4 LSB Comp DAC Logic Low-noise Voting This work 1/4 1/2 K Yoshioka 10/26
- 11. Overview Background Low power techniques for high resolution SAR ADCs C-DAC Comparators Proposed technique VCO comparator Eye-opening operation Measurement results Conclusions K Yoshioka 11/26
- 12. VCO comparator Based on time domain comparators [3] VCO is used instead of a delay line Time amp[4] amplifies the “time difference” of the pulse [3] A. Agnes, ISSCC 2008 [4] M. Lee, JSSC 2009. VinP VinN Phase Detector EN Time Amp x8 K Yoshioka 12/26
- 13. Phase Detectors (PD) Frequently used in PLLs Explicit the dead zone characteristic 0 Δt CN=1 CP=1 Deadzone CN,CP=0 CP tinP tinN CN DFF based PD K Yoshioka 13/26
- 14. Eye-opening operation VinP VinN EN VCO_P,N TA_P,N CP,CN When Dvin fairly large Result of 50 times noise simulation. “Eye” is already opened Conventional delay line operation. K Yoshioka 14/26
- 15. Eye-opening operation VinP VinN EN VCO_P,N TA_P,N CP,CN When Dvin fairly large When Dvin near LSB CP/CN does not rise, since Δt within Deadzone Completely corrupted by noise K Yoshioka 15/26
- 16. Eye-opening operation VinP VinN EN VCO_P,N TA_P,N CP,CN When Dvin fairly large When Dvin near LSB After few loops, “eye” opens CP/CN does not rise, since Δt within Deadzone Completely corrupted by noise Oscillation Reduces noise adaptively K Yoshioka 16/26
- 17. 1 3 5 7 PulseDifferenceatVCOoutput Times of Oscillation Dvin=11b LSB Dvin=12b LSB Dvin=13b LSB Dead zone Accumulated jitter Signal and noise during oscillation VCO is an “integrator” Integrates signal and noise during N time oscillation Signal: αN, Noise: 𝑵 Optimum noise reduction for given DVin achieved K Yoshioka 17/26
- 18. PVT drifts of VCO comparator Noise of VCO ∝ 𝒈 𝒎 Gain of time amp ∝ 𝟏 𝒈 𝒎 Oscillation N Comp. noise Fast variations Slow variations VinP VinN Phase Detector EN Time Amp K Yoshioka 18/26
- 19. SAR ADC implementation SAR ADC based on [1] 13b+2b redundancy 1.8214C 1.82C C Filtering Cap on 5 MSBs 20C VCM C Perturbation Injection SAMP 13b+2b C-DAC SAMPB VinP VinN SAR Logic Perturbation Signal DSAR[14:0] VCO Comp. LMS Calibration Offchip software DOUT CLK C=0.5fF [1] W. Liu, ISSCC 2010 K Yoshioka 19/26
- 20. Overview Background Low power techniques for high resolution SAR ADCs C-DAC Comparators Proposed technique VCO comparator Eye-opening operation Measurement results Conclusions K Yoshioka 20/26
- 21. Chip implementation 65nm CMOS 150u x 180u K Yoshioka 21/26 C-DAC C-DAC VCO Comp SAR Logic Output Buffer SW 150 mm 180mm
- 22. FFT spectrum w/peak SNDR -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 Frequency [kHz] FIN HD3HD2 fs=1024 kHz fin=63.625 kHz SNDR=66.4 dB SFDR=85.2 dB After LMS calibrationBefore LMS calibrationFIN fs=1024 kHz fin=63.625 kHz SNDR=48.7 dB SFDR=61.1 dB -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 Frequency [kHz] HD3 HD2 Power[dB] VDD=0.85 V Vin=0.7 Vpp VDD=0.85 V Vin=0.7 Vpp Only C-DAC calibrated No tuning is applied to VCO comparator K Yoshioka 22/26
- 23. Performance and comparison Liu ISSCC2010 Harpe ISSCC2014 Elzakker ISSCC2008 This work Technology [nm] 130 65 65 65 Architecture SAR SAR SAR SAR fs [MS/s] 45 0.04 1 1 SNDR [dB] 67 62.5 56.2 64.4 Power [uW] 3000 0.097 1.9 45 Calibration Off-chip None None Off-chip FOM [fJ/conv.] 36 2.2 4.4 33 FoMS[dB] 165 176 168 164 K Yoshioka 23/26
- 24. Conclusions A VCO comparator which automatically scales its noise and power depending on DVin was presented. When the DVin is small, the comparator oscillates and performs an eye-opening operation to obtain accurate results. This technique can be extended to further resolution and benefits can be granted by process scaling as well. K Yoshioka 24/26
- 25. Thank you for your kind attention! K Yoshioka 25/26
Editor's Notes
- High resolution and low powered ADCs are required in implant medical devices and sensors for IoT devices, which the market is growing rapidly in these years. This shows the market growth of the IoT market in only in Japan, and IoT devices will continuously increase. Therefore, we target to design low power ADCs with SNDR of 65dB. In this several years, the ADC power efficiency has improved significantly. The SAR ADC has lead this low power trend, since it grants large merit from process scalings. The resolution is under 10b, because its noise and mismatch requirements are quite low. On the other hand, the works in high resolution SAR ADCs has been rather left untouched. このような背景のため、我々はSNDR 65dB以上の低電力SAR ADCをターゲットとし、研究を行った。
- Digital logic designs does not change much since all you have to do is to add registers reflecting the number of bits. The power increasses only slightly. When high resolution is targeted in SAR ADCs, design of every analog elements becomes challenging. The comparator must meet low noise requrements and C-DAC will have severe mismatch requrements and designed to maintain sufficient kT/C noise.
- To meet the mismatch requreiemts in high resolution C-DACs, the unit capacitors must be enarged; which increases the power consumption. By making the DAC sub-binary and employing digital calibrations, the capacitor mismatch can be canceled. Therefore, with digital calibration the capacitor mismatch requirements can be greatly relaxed and unit capacitors can be scaled down until kT/C noise limits
- For low powered SAR ADC, dynamic comparators are often used. When designed with typical transitor sizing in 65nm CMOS, its input reffered noise will be about 240uVrms which is suitable for 10-bit SAR ADC and extending the noise level beyond that is quite difficult. To obtain better noise performance, few stages of preamps can be cascaded. However, we must remember that to improve the IRN of 1-bit, 4x of power must be spent. So, for 13-bit noise 64 times of power must be spent compared to 10 bit comparators . Thefore, comparator power consumption can be dominate in SAR ADCs.
- In actual binary SAR conversion, the condition when the comparator input voltage, delta vin is lower than LSB occur only once. For the other cycles, the comparator noise requrements are quite relaxed. Therefore, by adaptively configuring the comparator noise reflecting the dvin amount, using cheap and sloppy comparators when dVin is large and use costly but precise comparators only when Dvin is small
- The previously proposed data dependant noise reduction echnique conducts a majority voting operation when dvin is small. With N times voting, the comparator noise can be improved to 1/N root squrare. dVin amount is detected by monitoring the metastable time of the comparator, because smaller the dVin, the longer the metastable time will be. Optimum voting number differ with how close the dVin is. If we can detect the precise Dvin and configure the N reflecting that as well, power can be further decreased.
- ある一点で電力ががっと上がってしまう。 これを連続的にするためVCOcompを提案する。
- VCO比較器のブロック図を載せる。 3つのコンポーネント、VCOとタイムアンプ、そしてフェイズディテクターの3要素で構成される。 基本的な動作は従来発表されたタイムドメイン比較器にとても似ている。 VCOは入力電圧に依存した遅延を持つパルスを作り出す。 そしてその2つのパルス感をタイムアンプは増幅し、フェイズディテクタが判定しやすくする。タイムアンプはあまり線形性は良くないが、比較器のプリアンプ用途だと単調性があれば良い。 そしてどちらのパルスが先に来たかを比較するのがフェイズディテクタである。 これによって電圧をパルスに変換し時間ドメインで比較を行うことが出来る。
- 2つのパルスがどちらが先に来たかを判定するためにフェイズディテクタはPLLなどでよく使われる。 フェイズディテクタには大きく分けてNANDタイプとDFFタイプがある NANDはダイナミック比較器のようにポジティブフィードバックを互いにかけているのが特徴である。 そのためパルス間が非常に短い場合でも、ノイズによって比較器出力はガウス分布のようになる。これは普通の電圧ベース比較器と同じである 一方でDFFベースのPDはDFFの有限のセットアップタイムのため、もしパルス間が非常に近くてもそれがセットアップタイム未満の場合フリフロは出力を出さない。 そのためこの図のように一定のデッドゾーンを持ってしまう。ΔTがこの間の時PDは動作をしない。 今回提案するVCO比較器ではこのデッドゾーン特性をexplicitする。
- Δvinがある程度大きい時のVCO比較器の動作をまず説明する。 ENが立ち上がるとVCOはイネーブルになり、VCOの出力にはVinに応じた遅延を持つパルスが立ち上がる。 この時のVCO出力の50かいのノイズシミュレーション結果をプロットする。 ノイズ（またはサイクルtoサイクルジッタ）は無視できるほど小さく、ポジティブ側の出力とネガティブ側の出力のパルス間に十分なアイが開いていることがわかる。 このような時はタイムアンプでパルス間を増幅しフェイズディテクタに与えれば精度の良い比較結果が得られる。この時の動作は従来のディレイライン動作と同様である。
- それではΔvinがかなり小さい時を考える。 この時のVCO出力をプロットすると、アイが開いていないことがわかる。これは電圧依存のパルス遅延よりもノイズ由来のジッタの方が大きい時怒ってしまう。 このようなパルスをNANDベースPDに入れても、正常な比較結果は得られない。 しかしVCO比較器はDFFベースPDを使用しており、このようにパルス間が非常に短い時はΔtがデッドゾーン以内なので比較結果は出力されない。
- 比較結果がデないのでENは立ち上がったままである。VCOはリングオシレータのため、パルスが入力インバータにフィードバックされて発振動作を行う。 発振が続くとジッタ成分よりも信号依存のパルス遅延が大きくなるため、アイが開いてくる。 するとパルス間が十分に離れているため、PDのデッドゾーンからデて比較ッカを出力する。PDが結果を出力すると発振は停止する。
- Why do eye opening operation work? Remember that VCO is an integrator and during oscillation the signal and noise is integated. However, while the signal related pulse difference is integrated as alpha N, the noise is square root N. Alpha is a constant reflexting the amount of DVin. Therefore, if we plot the signal related and noise related pulse difference, it would be like this. The signal is integrated lineary but the noise is square root and the S/N improves with oscilation. So, if we set the dead zone of DFF phase detectors like this, the comparator will not make a descision when the noise is dominant but will output when the signal is dominant. So even with small DVin, accurate decision can be made. The comparator power will be a function of Dvin, because the comparator power consumption is also proportional to times of oscillation.
- PVTドリフトに対する追従性を述べる。 例えば低温やファストコーナのようにトランジスタしきい値が下がる変動があったときの動作を考える. するとgmが増加しバンド幅が増加するためVCOのノイズは増えてしまう。しかしタイムアンプのゲインは下がるためデッドゾーンを超えるために必要な発振回数は増加する。 発振回数が増加するとVCOの積分動作のためVCOのノイズはキャンセルされる。 同様にスローPVTでも逆が起こり、比較器のノイズレベルはいっていに保たれる。
- While the calibration is active, the ADC does 2 conversions for single input with injecting positive and negative dithers respectively. After the mismatch has been cancelled, the calibration can be shut down and ADC can operate with 1 conversion for single input to save power.
- 13b Calibrated sar ADC but got only 11b ENOB. Due to lack of measurement equipments We could not filter out the signal generator’s spurs efficiently. That ended up with voltage input of 0.7Vpp, which was half of expected but the noise floor was right where we wanted.
- When we look at the walden fom, its quite worsened but with schreier fom its quite competable with other state of the art SAR designs.