The document provides an overview of Analog-to-Digital Converters (ADCs), particularly focusing on successive approximation and flash converters used in VLSI circuits. It details their operation, advantages, disadvantages, and design considerations, highlighting the importance of factors such as resolution, speed, and power consumption. Additionally, it introduces two-step ADCs as an alternative offering a balance of performance and efficiency in high-speed digital applications.

1. Introduction to VLSI Circuits and Systems, NCUT 2007
Module-IV
NYQUIST RATE A/D CONVERTERS
Prepared By:
Dr. Vasudeva
Assistant Professor

2. Introduction to VLSI Circuits and Systems, NCUT 2007
Syllabus
 D/A-Based Successive Approximation Converter
 Flash/Parallel Converters
 Issues in Designing Flash A/D Converters
 Two-Step A/D Converters
 Two-Step Converter with Digital Error Correction.

3. Introduction to VLSI Circuits and Systems, NCUT 2007
What is a Successive Approximation ADC?
 The Successive Approximation ADC is
the ADC of choice for low cost
medium to high resolution
applications, the resolution for SAR
ADCs ranges from 8 - 18 bits, with
sample speeds up to 5 mega-samples
per second (Msps).
 Also, it can be constructed in a small
form factor with low power
consumption, which is why this type of
ADC is used for portable battery-
powered instruments.
 As the name implies, this ADC applies a binary search algorithm to convert the
values, which is why the internal circuitry may be running at several MHZ but the
actual sample rate is much less due to the Successive Approximation algorithm.

4. Introduction to VLSI Circuits and Systems, NCUT 2007
Working of Successive Approximation ADC
 This ADC consists of a comparator, a digital to analog converter, and a successive
approximation register along with the control circuit.
 Now, whenever a new conversation starts, the sample and hold circuit samples the
input signal. And that signal is compared with the specific output signal of the
DAC.

5. Introduction to VLSI Circuits and Systems, NCUT 2007
Contd…
Suppose a five-bit SAR ADC. An analog voltage signal of 19 volts is applied at the
input.
Initial Condition
 The operation starts by clearing all the bits in SAR. Let’s suppose Q is the output,
since it is a 5-bit ADC, the output will have five bits from Q0 to Q4. Initially, the
contents in successive approximation register (SAR) are given below:
 Q = [00000], VDAC = 0V, Vin > VDAC, Vcomp = high

6. Introduction to VLSI Circuits and Systems, NCUT 2007
Contd…
First Clock Cycle
 The comparator output is connected to SAR. As the comparator output goes high,
the device sets the SAR’s most significant bit to one while leaving the other bits at
zero.
 Q = [10000], VDAC = 16V, Vin < VDAC, Vcomp = low
Second Clock Cycle
 Again, the same procedure will be followed. This time the n-1 bit (that is, the 4th
bit) is set to 1, while all other bits remain unchanged.
 Q = [11000], VDAC = 24V, Vin < VDAC, Vcomp = low

7. Introduction to VLSI Circuits and Systems, NCUT 2007
Contd…
Third Clock Cycle
 In this clock cycle, the n-2 bit (that is, the 3rd bit) is set. while the value of the
previous n-1 bit is 0. The value of SAR in the second clock cycle was Q =
[11000] = 24V.
 Q = [10100], VDAC = 20V, Vin < VDAC, Vcomp = low
 But this value (Q = 10100 or VDAC = 20) is greater than the input voltage.
The approximation is wrong. The output of the comparator goes low.

8. Introduction to VLSI Circuits and Systems, NCUT 2007
Contd…
Fourth Clock Cycle
 In this clock cycle, the n-3 bit (the second bit) is set. while the value of the
previous n-2 bit is 0.
 The value of SAR in the third clock cycle was Q = [10100] = 20 V. But this value
is greater than the input voltage. Again, n the approximation is wrong. The n-2 bit
goes low while the n-3 bit goes high.
 Q = [10010], VDAC = 18V, Vin < VDAC, Vcomp = high

9. Introduction to VLSI Circuits and Systems, NCUT 2007
Contd…
Fifth Clock Cycle
 In this clock cycle, the n-4 or LSB bit is set. while the other bits remain
unchanged. The value of SAR in the fourth clock cycle was Q = [10010] = 18V.
But this value is less than the input voltage.
 The comparator output goes high. The least significant bit goes high.
 At the end of the conversion, the input of the DAC is equal to the output of the
DAC.
 Q = [10011], VDAC = 19V, End of conversion

10. Introduction to VLSI Circuits and Systems, NCUT 2007
Contd…
Advantages
 High Accuracy
 Low power consumption
 Easy to Interface
 Noise immunity
Disadvantages
 Slow Conversion Rate
 Limited Resolution
 Non-linear Behavior
 Complexity

11. Introduction to VLSI Circuits and Systems, NCUT 2007
Flash/Parallel Converters
 Flash converters are the
standard approach for
realizing very-high-speed
converters.
 The input signal in a flash
converter is fed to 2𝑛
comparators in parallel, as
shown in Fig.
 Each comparator is also
connected to a different node
of a resistor string. Any
comparator connected to a
resistor string node where 𝑉𝑟1
is larger than 𝑉𝑖𝑛 will have a 1
output while those connected
to nodes with 𝑉𝑟1 is less than
𝑉𝑖𝑛 will have 0 outputs.

12. Introduction to VLSI Circuits and Systems, NCUT 2007
Flash/Parallel Converters
 Such an output code word is commonly referred to as a thermometer code since it
looks quite similar to the mercury bar in a thermometer.
 Note that the top and bottom resistors in the resistor string have been chosen to
create a 0.5LSB offset in an A/D converter.
 The NAND gate that has a 0-input connected to its inverting input and a 1 input
connected to its noninverting input detects the transition of the comparator outputs
from 1s to 0s and will have a 0 output.
 All other NAND-gate outputs will be 1, resulting in simpler encoding. It also
allows for error detection by checking for more than one 0 output, which occurs
during a bubble error (see the next subsection) and, perhaps, error correction.
 Flash A/Ds are fast, but the number of comparators grows exponentially with the
resolution N, so they typically take up a large area and are very power hungry,
even for modest N—especially when they are clocked fast.

13. Introduction to VLSI Circuits and Systems, NCUT 2007
Contd…
 When ∅ is high, the inverter is set to its bistable operating point, where its input
voltage equals its output voltage (i.e., its threshold voltage).
 Normally with an odd number of inverters, a ring oscillator is formed; however, in
the case of a single CMOS inverter, the inverter operates as a single stage opamp
with only one pole (no nondominant poles), so stability is guaranteed.

14. Introduction to VLSI Circuits and Systems, NCUT 2007
Contd…
 With this inverter set to its threshold voltage, the other side of C is charged to 𝑉𝑟1.
 When ∅ goes low, the inverter is free to fall either high or low depending on its
input voltage.
 At the same time, the other side of C is pulled to the input voltage 𝑉𝑖𝑛
 Since the inverter side of the capacitor is floating, C must keep its original charge,
and therefore the inverter’s input will change by the voltage difference between 𝑉𝑟1
& 𝑉𝑖𝑛.
 Since the inverter’s input was at its bistable point, the difference between 𝑉𝑟1 &
𝑉𝑖𝑛 will determine which direction the inverter’s output will fall.
 However, it should be mentioned that this simple comparator suffers from poor
power supply rejection, which is often a critical design specification in fast
converters. Using fully differential inverters helps alleviate this shortcoming.

15. Introduction to VLSI Circuits and Systems, NCUT 2007
Issues in Designing Flash A/D Converters
Input Capacitive Loading
 The large number of comparators connected to 𝑉𝑖𝑛 results in a large parasitic load
at the node 𝑉𝑖𝑛. Such a large capacitive load often limits the speed of the flash
converter and usually requires a strong and power-hungry buffer to drive 𝑉𝑖𝑛. We
shall see that this large capacitive loading can be reduced by going to an
interpolating architecture.
Resistor-String Bowing
 Any input currents to the comparators cause errors in the voltages of the nodes of
the resistor string. These errors usually necessitate the bias current in the resistor
string being two orders of magnitude greater than the input currents of the
comparators. This is particularly significant if bipolar comparators are used.
 The errors are greatest at the center node of the resistor string and thus
considerable improvement can be obtained by using additional circuitry to force
the center tap voltage to be correct.

16. Introduction to VLSI Circuits and Systems, NCUT 2007
Contd…
Comparator Latch-to-Track Delay
 Another consideration that is often overlooked is the time it takes a comparator
latch to come from latch mode to track mode when a small input signal of the
opposite polarity from the previous period is present.
 This time can be minimized by keeping the time constants of the internal nodes of
the latch as small as possible. This is sometimes achieved by keeping the gain of
the latches small, perhaps only two to four.
 In many cases, the differential internal nodes might be shorted together temporarily
as a reset just after latch time.
Signal and/or Clock Delay
 Even very small differences in the arrival of clock or input signals at the different
comparators can cause errors. To see this, consider a 250-MHz, 1-V peak-input
sinusoid. This signal has a maximum slope of 1570 V/μs at the zero crossing

17. Introduction to VLSI Circuits and Systems, NCUT 2007
TWO-STEP A/D CONVERTERS
 Two-step (or subranging) converters are used for high-speed medium-accuracy
A/D converters.
 They offer several advantages over their flash counterparts. Specifically, two-step
converters require less silicon area, dissipate less power, have less capacitive
loading, and the voltages the comparators need to resolve are less stringent than for
flash equivalents.
 The throughput of two-step converters approaches that of flash converters,
although they do have a larger latency.

18. Introduction to VLSI Circuits and Systems, NCUT 2007
TWO-STEP A/D CONVERTERS
 A two-step converter may be thought of as a special case of a pipelined converter
with only two pipeline stages.
 The 4-bit MSB A/D determines the first four MSBs. To determine the remaining
LSBs, the quantization error (residue) is found by reconverting the 4-bit digital
signal to an analog value using the 4-bit D/A and subtracting that value from the
input signal.
 To ease the requirements in the circuitry for finding the remaining LSBs, the
quantization error is first multiplied by 16 using the gain amplifier, and the LSBs
are determined using the 4-bit LSB A/D. With this approach, rather than requiring
256 comparators as in an 8-bit flash converter, only 32 comparators are required
for a two-step A/D converter.
 However, this straightforward approach would require all components to be at least
8-bit accurate. To significantly ease the accuracy requirements of the 4-bit MSB
A/D converter, digital error correction is commonly used.

19. Introduction to VLSI Circuits and Systems, NCUT 2007
TWO-STEP A/D CONVERTERS
 A two-step converter may be thought of as a special case of a pipelined converter
with only two pipeline stages.
 The 4-bit MSB A/D determines the first four MSBs. To determine the remaining
LSBs, the quantization error (residue) is found by reconverting the 4-bit digital
signal to an analog value using the 4-bit D/A and subtracting that value from the
input signal.
 To ease the requirements in the circuitry for finding the remaining LSBs, the
quantization error is first multiplied by 16 using the gain amplifier, and the LSBs
are determined using the 4-bit LSB A/D. With this approach, rather than requiring
256 comparators as in an 8-bit flash converter, only 32 comparators are required
for a two-step A/D converter.
 However, this straightforward approach would require all components to be at least
8-bit accurate. To significantly ease the accuracy requirements of the 4-bit MSB
A/D converter, digital error correction is commonly used.

20. Introduction to VLSI Circuits and Systems, NCUT 2007
Thank You…