The document describes a hybrid digital low-dropout (DLDO) regulator that uses both a DLDO and low current analog ripple cancelation amplifier (RCA) to provide stable output voltage across a wide load range while reducing ripple. The HD-LDO was designed and fabricated in 180-nm CMOS technology, occupies 0.697 mm2 of die area, and achieves a 99.11% current efficiency and 15 clock period settling time with a 0.5-MHz clock for current switching between 10-90 mA. The RCA suppresses the fundamental, second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB respectively. The architecture is

1. A 100-mA, 99.11% Current Efficiency,2-mVpp Ripple
Digitally Controlled LDO with Active Ripple Suppression
ABSTRACT:
Digital low-dropout (DLDO) regulators are gaining attention due to their design
scalability for distributed multiple voltage domain applications required in state-of-
the-art system on-chips. Due to the discrete nature of the output current and the
discrete-time control loop, the steady-state response of the DLDO has inherent
output voltage ripple. A hybrid DLDO (HD-LDO) with fast response and stable
operation across a wide load range while reducing the output voltage ripple is
proposed. In the HD-LDO, a DLDO and a low current analog ripple cancelation
amplifier (RCA) work in parallel. The output dc of the RCA is sensed by a 2-bit
analog-to-digital converter, and the digitized linear stage current is fed into the
DLDO as an error signal. During load transients, a gear-shift controller enables fast
transient response using dynamic load estimation. The DLDO suppresses the
output dc of the RCA within its current resolution. With this arrangement, a
majority of the dc load current is provided by the DLDO and the RCA supplies
ripple cancelation current. The HD-LDO is designed and fabricated in a 180-nm
CMOS technology, and occupies 0.697 mm2 of the die area. The HD-LDO
operates with an input voltage range of 1.43–2.0 V and an output voltage range of

2. 1.0–1.57 V. At 100-mA load current, the HD-LDO achieves a current peak
efficiency of 99.11% and a settling time of 15 clock periods with a 0.5-MHz clock
for a current switching between 10 and 90 mA. The RCA suppresses fundamental,
second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB,
respectively. The proposed architecture of this paper analysis the logic size, area
and power consumption using Tanner tool.
SOFTWARE IMPLEMENTATION:
 Tanner tool