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AD9122 - Dual, 16-Bit, 1200 MSPS, TxDAC <ul><li>Source: Analog Devices </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>An   introduction   to   Dual,   16-Bit,   1200   MSPS,   TxDAC </li></...
Features <ul><li>Flexible LVDS interface allows word, byte, or nibble load. </li></ul><ul><li>Single-carrier W-CDMA ACLR =...
Key Applications <ul><li>Wireless infrastructure </li></ul><ul><li>W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE </li></ul><...
Functional Block Diagram  AD9122 Functional Block Diagram
Typical Performance Characteristics  Harmonics vs. f OUT  over f DATA , 2× Interpolation, Digital Scale = 0 dBFS, f SC  = ...
Serial Port Operation  Serial Port Interface Pins  Serial Port Instruction Byte  <ul><li>The serial port is a flexible, sy...
Serial Port Timing Diagram Timing Diagram for Serial Port Register Write   Timing Diagram for Serial Port Register Read
FIFO Operation  Block Diagram of FIFO  <ul><li>The AD9122 contains a 2-channel, 16-bit wide, eight-word deep FIFO designed...
Digital Datapath  Block Diagram of Digital Datapath  HB1 Filter Modes  HB2, Even Filter Modes
Quadrature Modulator   Digital Quadrature Modulator Block Diagram  <ul><li>The   quadrature   modulator   is   used   to  ...
DAC Input Clock Configurations  PLL Clock Multiplication Circuit  <ul><li>The on-chip PLL clock multiplier circuit can be ...
Transmit DAC Operation  Simplified Block Diagram of DAC Core  TYPICAL SIGNAL CHAIN
Basic Transmit DAC Output Circuit  Basic Transmit DAC Output Circuit  Voltage Output Waveforms
Interfacing To Modulators  Typical Interface Circuitry Between the AD9122 and the ADL537x  DAC Modulator Interface with Fi...
AD9122 Evaluation Board Bench Set-Up
Additional Resource <ul><li>For ordering AD9122, please click the part list or </li></ul><ul><li>Call our sales hotline </...
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AD9122 - Dual, 16-Bit, 1200 MSPS, TxDAC

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An introduction to Dual, 16-Bit, 1200 MSPS, TxDAC

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AD9122 - Dual, 16-Bit, 1200 MSPS, TxDAC

  1. 1. AD9122 - Dual, 16-Bit, 1200 MSPS, TxDAC <ul><li>Source: Analog Devices </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>An introduction to Dual, 16-Bit, 1200 MSPS, TxDAC </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Features and Key application. </li></ul></ul><ul><ul><li>Functional Block Diagram </li></ul></ul><ul><ul><li>Serial Port interface, FIFO Operation, Quadrature modulator </li></ul></ul><ul><ul><li>DAC input clock and DAC operation. </li></ul></ul><ul><ul><li>Interfacing to Modulators. </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>17 pages </li></ul></ul>
  3. 3. Features <ul><li>Flexible LVDS interface allows word, byte, or nibble load. </li></ul><ul><li>Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF. </li></ul><ul><li>Analog output: adjustable 8.7 mA to 31.7 mA,RL = 25 Ω to 50 Ω. </li></ul><ul><li>Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth. </li></ul><ul><li>Digital gain and phase adjustment for sideband suppression. </li></ul><ul><li>Multiple chip synchronization interfaces. </li></ul><ul><li>High performance, low noise PLL clock multiplier. </li></ul><ul><li>Digital inverse sinc filter. </li></ul><ul><li>Low power: 1.5 W @ 1.2 GSPS, 800 mW @ 500 MSPS, full operating conditions. </li></ul><ul><li>72-lead, exposed paddle LFCSP. </li></ul>
  4. 4. Key Applications <ul><li>Wireless infrastructure </li></ul><ul><li>W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE </li></ul><ul><li>Digital high or low IF synthesis </li></ul><ul><li>Transmit diversity </li></ul><ul><li>Wideband communications: LMDS/MMDS, point-to-point </li></ul>
  5. 5. Functional Block Diagram AD9122 Functional Block Diagram
  6. 6. Typical Performance Characteristics Harmonics vs. f OUT over f DATA , 2× Interpolation, Digital Scale = 0 dBFS, f SC = 20 mA 1-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS, f SC = 20 mA, PLL On
  7. 7. Serial Port Operation Serial Port Interface Pins Serial Port Instruction Byte <ul><li>The serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard micro-controllers and microprocessors. </li></ul><ul><li>The interface allows read/write access to all registers that configure the AD9122. </li></ul><ul><li>Single or multiple byte transfers are supported, as well as MSB-first or LSB-first transfer formats </li></ul><ul><li>The serial interface ports can be configured as a single pin I/O (SDIO) or two unidirectional pins for input/output (SDIO/SDO). </li></ul>
  8. 8. Serial Port Timing Diagram Timing Diagram for Serial Port Register Write Timing Diagram for Serial Port Register Read
  9. 9. FIFO Operation Block Diagram of FIFO <ul><li>The AD9122 contains a 2-channel, 16-bit wide, eight-word deep FIFO designed to relax the timing relationship between the data arriving at the DAC input ports </li></ul><ul><li>The FIFO acts as a buffer that absorbs timing variation between the data source and DAC, such as the clock-to-data variation of an FPGA or ASIC, which significantly increases the timing budget of the interface. </li></ul><ul><li>To initialize the FIFO data level through the serial port, Bit 1 of Register 0x18 should be toggled from 0 to 1 and back. </li></ul>
  10. 10. Digital Datapath Block Diagram of Digital Datapath HB1 Filter Modes HB2, Even Filter Modes
  11. 11. Quadrature Modulator Digital Quadrature Modulator Block Diagram <ul><li>The quadrature modulator is used to mix the carrier signal generated by the NCO with the I and Q signal. </li></ul><ul><li>A complex carrier signal is a pair of sinusoidal waveforms of the same frequency, offset 90° from each other. </li></ul><ul><li>The available signal bandwidth of the datapath is dependent on the center frequency of the output signal in relation to the center frequency of the interpolation filters used. </li></ul>
  12. 12. DAC Input Clock Configurations PLL Clock Multiplication Circuit <ul><li>The on-chip PLL clock multiplier circuit can be used to generate the DAC sample rate clock from a lower frequency reference clock. </li></ul><ul><li>The clock multiplication circuit operates such that the VCO outputs a frequency, f VCO , equal to the REFCLK input signal frequency multiplied by N1×N0. </li></ul>
  13. 13. Transmit DAC Operation Simplified Block Diagram of DAC Core TYPICAL SIGNAL CHAIN
  14. 14. Basic Transmit DAC Output Circuit Basic Transmit DAC Output Circuit Voltage Output Waveforms
  15. 15. Interfacing To Modulators Typical Interface Circuitry Between the AD9122 and the ADL537x DAC Modulator Interface with Fifth-Order, Low Pass Filter <ul><li>Most applications require a baseband anti-imaging filter between the DAC and the modulator to filter out Nyquist images and broadband DAC noise. </li></ul><ul><li>The baseband inputs of the ADL537x family require a dc bias of 500 mV. The nominal midscale output current on each output of the DAC is 10 mA. </li></ul>
  16. 16. AD9122 Evaluation Board Bench Set-Up
  17. 17. Additional Resource <ul><li>For ordering AD9122, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.analog.com/en/digital-to-analog-converters/da-converters/ad9122/products/product.html </li></ul></ul><ul><li>Visit Element 14 to post your question </li></ul><ul><ul><li> www.element-14.com </li></ul></ul><ul><li>For additional inquires contact our technical service hotline or even use our “Live Technical Chat” online facility </li></ul>

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