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LMK03000 Family of  Precision Clock Conditioners  <ul><li>Source: National Semiconductor </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>Overview   of   Precision   Clock   Conditioner   with   Integrated   V...
Precision Clock Conditioners Basics <ul><li>A clock conditioner gives the designer the capability to design a complete clo...
LMK03000 Family Features <ul><li>Integrated VCO with very low phase noise floor </li></ul><ul><li>Integrated Integer-N PLL...
LMK03000 Family Members
Functional Block Diagram
Target Applications <ul><li>Data Converter Clocking </li></ul><ul><li>Networking, SONET/SDH, DSLAM </li></ul><ul><li>Wirel...
Internal Voltage-Controlled Oscillators (VCO) <ul><li>The VCO combined with Phase Locked Loop (PLL) in order to synchroniz...
Loop Filter Loop Filter Capacitor C3, C4 Values Loop Filter Resistor R3,R4 Values
Serial Data Timing <ul><li>Serial communication is used to program the device. </li></ul><ul><li>The registers consist of ...
Termination and Use of Clock Outputs <ul><li>When terminating clock drivers below are the guidelines to be taken care for ...
Termination for DC Coupled Differential Operation Fig 1:Differential LVDS Operation, DC Coupling Fig 2:Differential LVPECL...
Termination for AC Coupled Differential Operation Fig:1 Differential LVDS Operation, AC Coupling Fig:2 Differential LVPECL...
Programming Sequence <ul><li>Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state....
Typical Application
Additional Resource <ul><li>For ordering the  LMK03000 family of clock conditioners , please click the part list or </li><...
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LMK03000 Family of Precision Clock Conditioners

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Overview of Precision Clock Conditioner with Integrated VCO

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LMK03000 Family of Precision Clock Conditioners

  1. 1. LMK03000 Family of Precision Clock Conditioners <ul><li>Source: National Semiconductor </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>Overview of Precision Clock Conditioner with Integrated VCO </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Basic knowledge of precision clock conditioner </li></ul></ul><ul><ul><li>Overview of LMK03000 family and its target applications </li></ul></ul><ul><ul><li>System / Functional Block Diagram. </li></ul></ul><ul><ul><li>Application information </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>16 pages </li></ul></ul>
  3. 3. Precision Clock Conditioners Basics <ul><li>A clock conditioner gives the designer the capability to design a complete clock architecture (sub-system) that achieves the best possible performance for the cost. </li></ul><ul><li>A clock conditioner gives the designer the capability to not only generate a precision clock, but also to re-condition and distribute a derived or externally generated clock. </li></ul><ul><li>The key characteristics of a precision clock conditioner include: </li></ul><ul><ul><li>noise performance </li></ul></ul><ul><ul><li>skew between the outputs in a multi-output device, or clock distribution stage </li></ul></ul><ul><li>Applications </li></ul><ul><ul><li>In a clock reconditioning application, the objective is to reduce the noise on an existing clock, sometimes referred to as jitter cleaning. </li></ul></ul><ul><ul><li>A clock conditioner could be used as a jitter cleaner is a Clock and Data Recovery (CDR) application, </li></ul></ul><ul><ul><li>In clock multiplier applications, the VCO is locked to a multiple of the input clock signal, so that it can be divided down to several different frequencies and distributed. </li></ul></ul>
  4. 4. LMK03000 Family Features <ul><li>Integrated VCO with very low phase noise floor </li></ul><ul><li>Integrated Integer-N PLL with outstanding normalized phase noise contribution of 224 dBc/Hz </li></ul><ul><li>VCO divider values of 2 to 8 (all divides) </li></ul><ul><li>Channel divider values of 1, 2 to 510 (even divides) </li></ul><ul><li>LVDS and LVPECL clock outputs </li></ul><ul><li>Partially integrated loop filter </li></ul><ul><li>Dedicated divider and delay blocks on each clock output </li></ul><ul><li>3.15 to 3.45 V operation </li></ul><ul><li>Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) </li></ul><ul><li>200 fs RMS Clock generator performance (10 Hz to 20 MHz) with a clean input clock </li></ul>
  5. 5. LMK03000 Family Members
  6. 6. Functional Block Diagram
  7. 7. Target Applications <ul><li>Data Converter Clocking </li></ul><ul><li>Networking, SONET/SDH, DSLAM </li></ul><ul><li>Wireless Infrastructure </li></ul><ul><li>Medical </li></ul><ul><li>Test and Measurement </li></ul><ul><li>Military / Aerospace </li></ul>
  8. 8. Internal Voltage-Controlled Oscillators (VCO) <ul><li>The VCO combined with Phase Locked Loop (PLL) in order to synchronize the oscillator to a specific frequency reference source. </li></ul><ul><li>The Ref Osc input is routed to a Phase Locked Loop (PLL) that locks the VCO to a frequency that is typically equal to, or a higher multiple of the clock input frequency. </li></ul>
  9. 9. Loop Filter Loop Filter Capacitor C3, C4 Values Loop Filter Resistor R3,R4 Values
  10. 10. Serial Data Timing <ul><li>Serial communication is used to program the device. </li></ul><ul><li>The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the data field DATA[27:0] </li></ul><ul><li>During Programming, LEuWire is low and serial data is clocked in on the rising edge of CLKuWire (MSB first). </li></ul><ul><li>When LE goes high, data is transferred to the register bank selected by the address field. </li></ul>
  11. 11. Termination and Use of Clock Outputs <ul><li>When terminating clock drivers below are the guidelines to be taken care for optimum phase noise and jitter performance: </li></ul><ul><ul><li>Transmission line theory should be followed for good impedance matching to prevent reflections. </li></ul></ul><ul><ul><li>Clock drivers should be presented with the proper loads. </li></ul></ul><ul><ul><li>For example: </li></ul></ul><ul><ul><ul><li>LVDS drivers are current drivers and require a closed current loop. </li></ul></ul></ul><ul><ul><ul><li>LVPECL drivers are open emitter and require a DC path to ground. </li></ul></ul></ul><ul><ul><li>Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level. In this case, the signal should normally be AC coupled. </li></ul></ul>
  12. 12. Termination for DC Coupled Differential Operation Fig 1:Differential LVDS Operation, DC Coupling Fig 2:Differential LVPECL Operation, DC Coupling <ul><li>For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS receiver. </li></ul><ul><li>For operation with LMK03000 family LVDS drivers it is recommend to use AC coupling with LVDS receivers that have an internal DC bias voltage. </li></ul><ul><li>For DC coupled operation of an LVPECL driver, terminate with 50 Ω to Vcc - 2V , Alternatively terminate with a Thevenin equivalent circuit. </li></ul>
  13. 13. Termination for AC Coupled Differential Operation Fig:1 Differential LVDS Operation, AC Coupling Fig:2 Differential LVPECL Operation, AC Coupling, Thevenin Equivalent <ul><li>AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important to ensure the receiver is biased to its ideal DC level. </li></ul><ul><li>When driving LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors </li></ul><ul><li>When AC coupling an LVPECL signal use 120 Ω emitter resistors close to the LVPECL driver to provide a DC path to ground </li></ul><ul><li>The typical DC bias voltage (common mode voltage) for LVPECL receivers is 2 V. </li></ul>
  14. 14. Programming Sequence <ul><li>Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state. When the reset bit is set in R0, the other R0 bits are ignored. </li></ul><ul><ul><li>— If R0 is programmed again, the reset bit is programmed clear (RESET = 0). </li></ul></ul><ul><li>Program R0 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings. </li></ul><ul><li>Program R8 for optimum phase noise performance. </li></ul><ul><li>Program R9 with Vboost setting if necessary. Only needed to set Vboost = 1. </li></ul><ul><li>Program R11 with DIV4 setting if necessary. </li></ul><ul><li>Program R13 with oscillator input frequency and internal loop filter values </li></ul><ul><li>Program R14 with Fout enable bit, global clock output bit, power down setting, PLL mux setting, and PLL R divider. </li></ul><ul><li>Program R15 with PLL charge pump gain, VCO divider, and PLL N divider. Also starts frequency calibration routine. </li></ul>
  15. 15. Typical Application
  16. 16. Additional Resource <ul><li>For ordering the LMK03000 family of clock conditioners , please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.national.com/cat/index.cgi?i=i//350 </li></ul></ul>Newark Farnell

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