This document presents the design of a 64 point fast Fourier transform (FFT) processor called Turbo64. It uses a radix-2 decimation-in-time algorithm to decompose a 64 point FFT into two 8 point FFTs. The architecture includes input, multiplier, constant buffer, and output units. The multiplier unit utilizes constant multiplication through hard-wired representations of constants. Fabricated in 0.25um BiCMOS, Turbo64 has a core area of 6.8 sq mm and power consumption of 41 mW, making it suitable for applications like OFDM used in wireless communications standards.

1. Presented by:
SHALY JOSE
ECE
VJCET
2011-2015
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2. INTRODUCTION
Discrete Fourier Transform
 Fast Fourier Transform:
Algorithm to compute DFT using
reduced no of calculations.
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3. Applications of FFT
Used in signal processing applications,such as:
 OFDM:Orthogonal Frequency Division Multiplexing;
 A method encoding digital data on multiple carrier
frequencies.
 Software defined radio:SDR:
 Radio communication components implemented by
means of software on a personal computer
or embedded system.
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4. 64 pt FFT PROCESSOR—turbo 64
 Developed for IEEE 802.11(a) standard.
 Core area:6.8 sq. mm
 Average power consumption: 41 mW at 1.8 V @ 20 MHz
frequency
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5. Why TURBO64 at 20 MHz?
IEEE 802.11(a)
standard
4microsec
Cooley-Turkey
Algorithm
192 complex
butterfly
operations for a
64 point FFT
1 butterfly
operation
• 20.8 ns
48 MHz
frequency
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6. • FFT, A(r)= 𝑘=0
𝑁−1
𝐵 𝑘 𝑊 𝑟𝑘
𝑁
………………………….1
Where B(k)-complex data sequence
N-length of the sequence
𝑊𝑁 ------ 𝑒−2𝑗𝜋/𝑁
• Consider:
N=MT,r=s+Tt ,k=l+Mm
s,l ∈ 0,1, … … 7
k,m∈ 0, … … 𝑇 − 1
Applying these values in above equation:
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7. A(s+Tt)= 𝑙=0
𝑇−1
𝑊 𝑙𝑡
𝑀[𝑊 𝑠𝑙
𝑀𝑇 𝑚=0
𝑇−1
𝐵(𝑙 + 𝑀𝑚)𝑊 𝑠𝑚
𝑇
]………….2
• Eqn (2) FFT decomposed into M point and T point FFT
And combined for final result.
• Considering M=8 and T=8: the 64 point FFT can be expressed as:
A(s+Tt)= 𝑙=0
7
𝑊 𝑙𝑡
8 [𝑊 𝑠𝑙
64 𝑚=0
7
𝐵(𝑙 + 8𝑚)𝑊 𝑠𝑚
8
]………
3
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8. Signal Flow graph of a 8 point DFT
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Swap real and
imaginary
terms
Forward FFT
Again swap
the real and
imaginary
terms.

10. ARCHITECTURE OF TURBO64
Input unit
1st 8 pt
FFT unit
Multiplier
unit
CB unit
2nd 8 pt
FFT unit
Output
unit
Data 16bit
Start input
5 bit binary
counter
Start mode
count
16 bit
complex
output
Data out
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11. INPUT
UNIT
Three
additional
register
Input register
bank
16 bit
wordlength and
57 complex
samples
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Block diagram of input unit

13. 8 point FFT Unit
• Fully parallel 8
Point FFT
• Internal
wordlength:16 bit
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Signal flow graph of a 8 point FFT

14. MULTIPLIER UNIT
Interdimensional Constants:
• 49 non trivial interdimensional constants to be
multiplied to result of 1st 8 point FFT.
(𝑊 𝑠𝑙
64
,s,l ∈ {1,2….7})
• Only nine sets are unique
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15. Contd…
• (1,0), (0.995178, 0.097961), (0.980773,
0.195068),(0.956909, 0.290283), (0.923828,
0.382629), (0.881896,0.471374), (0.831420,
0.555541), (0.773010, 0.634338),
(0.707092, 0.707092)
• Each constant decomposed as summation/subtraction
based on powers of 2.
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16. • Eg:0.991578 (1-2−8 − 2−10+2−14)
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Circuit diagram of proposed multiplier unit-----hard
wired representation of the constant

17. TABLE I
REALIZATION OF DIFFERENT CONSTANTS
IN TERMS OF POWER OF 2
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18. • Final design of multiplier unit,
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Block diagram of complete multiplier unit

19. TABLE II
UTILIZATION OF THE DIFFERENT HARD-WIRED CONSTANTS DURING THE
49 COMPLEX MULTIPLICATION OPERATION
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20. COMPARISON
Synthesized
multiplier unit
Cell area:0.6 sqmm
Average power
consumption:19mW
Multiplier unit with
8 complex
multipliers
Cell area:1.1 sqmm
Average power
consumption:31mW
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21. Multiplier unit also
has 2 shuffle
network:
1.Routes data to
appropriate
constants
2.Maps multiplied
data to appropriate
index of CB unit.
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22. ARCHITECTURE OF TURBO64
Input unit
1st 8 pt
FFT unit
Multiplier
unit
CB unit
2nd 8 pt
FFT unit
Output
unit
Data 16bit
Start input
5 bit binary
counter
Start mode
count
16 bit
complex
output
Data out
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23. OUTPUT UNIT
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Block diagram of output
unit

24. • Fabricated using 0.25micrometer 3 metal
layer BiCmos process.
• 85 I/O ports
• Average power dissipation over 55 fabricated
chips:
o 4.1mW at 1.8V @ 20MHz frequency
o 84mW at 2.5 V @ same frequency
o Maximum frequency of operation:
o At 1.8 V=26 MHz
o At 2.5 V=38MHz
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25. Die photograph of
TURBO64 processor
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26. CONCLUSION
• Requires smaller no. of clock cycles
• Better power perfomance, less silicon area
• Proposed architecture can be used for any fast and
low power requirement operations.
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27. REFERENCES
• [1]A 64 point fourier transform chp for high speed
wireless LAN application using OFDM-
K.Maharatna,E.Grass,U.Jaghold
• [2] A. M. Despain, “Very fast Fourier transform
algorithms hardware for implementation,” IEEE
Trans. Comput., vol. C-28, no. 5, pp. 333–341,1979.
• [3]C. Chen and L.Wang, “A new efficient systolic
architecture for the 2-D discrete Fourier transform,”
in Proc. IEEE Int. Symp. Circuits and Systems,vol.
6, ch. 732, 1992, pp. 689–692.
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