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UIC Thesis Cancare

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UIC Thesis Cancare

  1. 1. Modeling Methodologies for Dynamic Reconfigurable Systems Thesis Defense - May 2008 Fabio Cancare Thesis Committee: Tanya Berger-Wolf, Shantanu Dutt (Chair), Donatella Sciuto
  2. 2. Rationale <ul><li>Dynamic reconfiguration is a new and promising technique, it can be applied to cope with: </li></ul><ul><ul><li>Lack of available resources </li></ul></ul><ul><ul><li>System adaptability </li></ul></ul><ul><ul><li>System reliability </li></ul></ul><ul><li>Main drawback: implementing DR systems is a complex and time-consuming task </li></ul><ul><li>Model-based design paradigm allow the fast development of complex architecture </li></ul>Understand how it is possible to exploit the model-design paradigm in dynamic reconfigurable system implementation
  3. 3. Innovative Contribution <ul><li>Outline a model-based design flow for implementing large designs onto FPGAs with limited available resources </li></ul>
  4. 4. Useful Novelties <ul><li>Development of SysGen, a tool automating a portion of the low-level implementation phase </li></ul><ul><li>Implementation of a real-world application demanding for Dynamic Reconfigurable to enhance its perfomance </li></ul>
  5. 5. Outline <ul><li>Fundamental Concepts </li></ul><ul><li>Proposed Flow </li></ul><ul><ul><li>High-level Modeling Phase </li></ul></ul><ul><ul><li>Low-level Implementation Phase </li></ul></ul><ul><li>Case Study </li></ul><ul><li>Results </li></ul><ul><li>Conclusions and follows-up </li></ul>
  6. 6. Outline <ul><li>Fundamental Concepts </li></ul><ul><li>Proposed Flow </li></ul><ul><ul><li>High-level Modeling Phase </li></ul></ul><ul><ul><li>Low-level Implementation Phase </li></ul></ul><ul><li>Case Study </li></ul><ul><li>Results </li></ul><ul><li>Conclusions and follows-up </li></ul>
  7. 7. Reconfigurable Computing “ Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware” (K. Compton and S. Hauck, Reconfigurable Computing: a Survey of Systems and Software , 2002)‏
  8. 8. Reasons Behind <ul><li>Applications often require performance which cannot be achieved by software </li></ul><ul><li>Applications often require to be flexible, modifiable, adaptable. Traditional hardware cannot achieve such results </li></ul><ul><li>Reconfigurable Computing techiniques are able to alter a concrete architecture once it has been deployed onto a high-performance device, in order to meet: </li></ul><ul><ul><li>Resources constraints </li></ul></ul><ul><ul><li>Adaptability constraints </li></ul></ul><ul><ul><li>Reliability constraints </li></ul></ul>
  9. 9. Reconfigurable Computing Techniques <ul><li>Targeted devices: PLDs (Programmable Logic Devices)‏ </li></ul><ul><ul><li>In particular, FPGAs (Fields Programmable Gate Arrays)‏ </li></ul></ul><ul><li>Several configuration techniques: </li></ul><ul><ul><li>Static vs Dynamic </li></ul></ul><ul><ul><li>Partial vs Total </li></ul></ul><ul><ul><li>External vs Internal </li></ul></ul>
  10. 10. Useful Definitions <ul><li>Core : a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)‏ </li></ul><ul><li>IP-Core : a core described using a HDL combined with its communication infrastructure (i.e. the bus interface)‏ </li></ul><ul><li>Reconfigurable Functional Unit : an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture </li></ul><ul><li>Reconfigurable Region : a portion of the device area used to implement a reconfigurable core </li></ul><ul><li>Reconfigurable Slot : a high-level representation of a Reconfigurable Region </li></ul>
  11. 11. Outline <ul><li>Fundamental Concepts </li></ul><ul><li>Proposed Flow </li></ul><ul><ul><li>High-level Modeling Phase </li></ul></ul><ul><ul><li>Low-level Implementation Phase </li></ul></ul><ul><li>Case Study </li></ul><ul><li>Results </li></ul><ul><li>Conclusions and follows-up </li></ul>
  12. 12. Flow Overview <ul><li>Dynamic Partial Reconfiguration </li></ul><ul><li>Flow composed of two phases: </li></ul><ul><ul><li>HLMP </li></ul></ul><ul><ul><li>LLIP </li></ul></ul><ul><li>Support from system specification to system FPGA implementation </li></ul>
  13. 13. High Level Modeling Phase <ul><li>From the System Specification to the System Hardware Description </li></ul>
  14. 14. HLMP – Tools and Techniques <ul><li>Two techniques to model dynamic reconfigurable systems are proposed: </li></ul><ul><ul><li>Reconfiguration Aware Modeling </li></ul></ul><ul><ul><li>Reconfiguration Unaware Modeling </li></ul></ul>
  15. 15. Simulink HDL Coder Compliant Models
  16. 16. HLMP – Reconfiguration Aware Modeling
  17. 17. HLMP – Reconfiguration Unaware Modeling <ul><li>The first technique requires more knowledge but can lead to better results </li></ul>
  18. 18. Low Level Implementation Phase
  19. 19. System Generation
  20. 20. LLIP – The Caronte Flow and SysGen <ul><li>Main LLIP thesis contribution: SysGen </li></ul>SysGen
  21. 21. Outline <ul><li>Fundamental Concepts </li></ul><ul><li>Proposed Flow </li></ul><ul><ul><li>High-level Modeling Phase </li></ul></ul><ul><ul><li>Low-level Implementation Phase </li></ul></ul><ul><li>Case Study </li></ul><ul><li>Results </li></ul><ul><li>Conclusions and follows-up </li></ul>
  22. 22. Real-world Application <ul><li>Inpeco Corporation proposed to implement an embedded vision system exploiting dynamic reconfiguration </li></ul><ul><li>The goal is to provide functionalities such as: </li></ul><ul><ul><li>Mapping of the test-tubes within a rack </li></ul></ul><ul><ul><li>Test-tube sample chromatic analysis </li></ul></ul><ul><ul><li>Test-tube lateral recognition </li></ul></ul><ul><li>The system must also be as flexible as possible, since new functionalities may be required in the future </li></ul>
  23. 23. Overall Description
  24. 24. Real-world Application – System Model
  25. 25. Outline <ul><li>Fundamental Concepts </li></ul><ul><li>Proposed Flow </li></ul><ul><ul><li>High-level Modeling Phase </li></ul></ul><ul><ul><li>Low-level Implementation Phase </li></ul></ul><ul><li>Case Study </li></ul><ul><li>Results </li></ul><ul><li>Conclusions and follows-up </li></ul>
  26. 26. Classical System <ul><li>The static system implementation uses 96.9% of targeted device, a Xilinx XC4VFX12-FF668-10 FPGA, slices (and some functionalities are missing)‏ </li></ul>FPGA Logical view FPGA Physical view Base Arch. RGB to grayscale Edge detection Circle detection Slot detection
  27. 27. Dynamic Reconfigurable System <ul><li>The dynamic reconfigurable implementation uses only 66.6% of available slices (26.0% of them can be reused)‏ </li></ul>FPGA Logical view Physical view Static Area Base Arch. Rec. Area RFU Free Resource
  28. 28. Occupation Data Static System Dynamic Reconfigurable System
  29. 29. Classic System vs DR System
  30. 30. Scientific Papers <ul><li>A paper describing the improved version of the low-level implementation phase has been published in the RAW (Reconfigurable Architectures Workshop) 2008 proceedings: </li></ul><ul><li>A Design Flow Tailored for Self Dynamic Reconfigurable Architecture </li></ul><ul><li>(Marco D. Santambrogio, Donatella Sciuto and Fabio Cancare)‏ </li></ul><ul><li>A paper describing the high-level modeling phase has been submitted at CODES+ISSS (International Conference on Hardware-Software Codesign and System Synthesis) 2008 </li></ul>
  31. 31. Outline <ul><li>Fundamental Concepts </li></ul><ul><li>Proposed Flow </li></ul><ul><ul><li>High-level Modeling Phase </li></ul></ul><ul><ul><li>Low-level Implementation Phase </li></ul></ul><ul><li>Case Study </li></ul><ul><li>Results </li></ul><ul><li>Conclusions and follows-up </li></ul>
  32. 32. Conclusions and Follow-ups <ul><li>The model-based design paradigm has been successfully used as part of a dynamic reconfigurable system implementation flow </li></ul><ul><li>Two high-level modeling techniques were outlined </li></ul><ul><li>Enhancement of the Caronte low-level implementation phase </li></ul><ul><li>The proposed flow has been employed to produce a first version of an industrial application </li></ul><ul><li>Test the approach with other applications </li></ul><ul><li>For what concerns the case study, it is necessary to implement the other functionalities and to introduce DMA </li></ul>
  33. 33. General Information <ul><li>Webpage </li></ul><ul><ul><li>www.dresd.org/?q=hlr </li></ul></ul><ul><li>Mailing List </li></ul><ul><ul><li>[email_address] </li></ul></ul><ul><li>Contact </li></ul><ul><ul><li>To have more information regarding HLR: </li></ul></ul><ul><ul><ul><li>[email_address] </li></ul></ul></ul><ul><ul><li>For a complete list of information on how to contact us: </li></ul></ul><ul><ul><ul><li>www.dresd.org/?q=contact _hlr </li></ul></ul></ul>
  34. 34. Any Question? <ul><li>Thank you very much! </li></ul>

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