This document introduces VulcaNoCs, a SystemC-based simulation environment for modeling the dynamic thermal behavior of Networks-on-Chip (NoCs). VulcaNoCs uses an equivalent RC circuit model to represent the thermal properties of a system, where heat flow is analogous to electrical current. It allows simultaneous simulation of high-level system behavior and temperature distribution. Experiments show VulcaNoCs has significantly better simulation performance than SPICE-based approaches, with up to 98.5% faster modeling for a 2x2 NoC. VulcaNoCs provides a physically accurate way to model dynamic thermal effects without external tools for power estimation.
THERMAL MODELING AND ANALYSIS OF 3- DIMENSINAL MEMORY INTEGRATION cscpconf
Moore's law describes a long-term trend in the history of computing hardware. The
conventional methods have reached his limits so new fields has to be exploited. Such a concept
is 3-Dimensional integration where the components are arranged in 3D plane. This
arrangement can increase the package density of devices. The successful construction of 3D
memory can lead to a new revolution in designing and manufacturing high performance
microprocessor system on chip. The major problem is the increased temperature effects. It’s
important to develop an accurate power profile extraction methodology to design 3D memory.
The total power dissipation includes static and dynamic component. In this paper the static
power dissipation of the memory cell is analysed and is used to accurately model the inter-layer
thermal effects for 3D memory stack. Then packaging of the chip is considered and modelled
using an architecture level simulator. This modelling is intended to analyse the thermal effects
of 3D memory, its reliability and lifetime of the chip with greater accuracy.
Modeling and Optimization of Cold Crucible Furnaces for Melting MetalsFluxtrol Inc.
http://fluxtrol.com
Cold Crucible Furnaces (CCFs), widely used in multiple special applications of
melting metals, oxides, glasses and other materials [1], are essentially 3D devices and their modeling is a complicated task. Multiple studies of CCFs have been made for their
optimization, but their electrical efficiency is still low; for metals approximately 25-30% andeven lower. Fluxtrol, Inc., made an extensive study of electromagnetic processes of CCFs using computer simulation and laboratory tests. This study showed that electrical efficiency of CCFs may be strongly improved by means of optimal design of the whole system with use of magnetic flux controllers. Theoretical results had been confirmed by laboratory tests on mockups and by industrial tests with real melting processes. The presentation contains a description of the computer modeling procedure and major findings. They form a basis for optimal design of electromagnetic systems of CCFs.
Performance prediction of PV & PV/T systems using Artificial Neural Networks ...Ali Al-Waeli
This presentation offers insight into use of ANN and machine learning for various applications in solar energy. Prepared and presented by Dr. Ali H. A. Alwaeli.
New Magnetodielectric Materials for Magnetic Flux ControlFluxtrol Inc.
http://fluxtrol.com
Magnetodielectric materials play an important role in improvement of induction systems for heat treatment, brazing, soldering, sealing and other technologies. This presentation is a continuation of the report made at HIS-01. Current report shows the results of development of new magnetodielectric materials for magnetic flux control and intensive study of their properties.
Master Thesis presentation.
Nanocomposite generator for energy harvesting from a bending movement.
Research: CNTs, Nanocomposites and Piezoelectric effect theoretical background.
Nanocomposite Generator modelling and practical experiment.
Results presentation.
28 Chòm sao được chia thành bốn hướng như sau: Đông, Tây, Nam, Bắc. Người ta dùng những con vật linh mang biểu tượng may mắn để đặt tên gọi là “Tứ tượng”.
THERMAL MODELING AND ANALYSIS OF 3- DIMENSINAL MEMORY INTEGRATION cscpconf
Moore's law describes a long-term trend in the history of computing hardware. The
conventional methods have reached his limits so new fields has to be exploited. Such a concept
is 3-Dimensional integration where the components are arranged in 3D plane. This
arrangement can increase the package density of devices. The successful construction of 3D
memory can lead to a new revolution in designing and manufacturing high performance
microprocessor system on chip. The major problem is the increased temperature effects. It’s
important to develop an accurate power profile extraction methodology to design 3D memory.
The total power dissipation includes static and dynamic component. In this paper the static
power dissipation of the memory cell is analysed and is used to accurately model the inter-layer
thermal effects for 3D memory stack. Then packaging of the chip is considered and modelled
using an architecture level simulator. This modelling is intended to analyse the thermal effects
of 3D memory, its reliability and lifetime of the chip with greater accuracy.
Modeling and Optimization of Cold Crucible Furnaces for Melting MetalsFluxtrol Inc.
http://fluxtrol.com
Cold Crucible Furnaces (CCFs), widely used in multiple special applications of
melting metals, oxides, glasses and other materials [1], are essentially 3D devices and their modeling is a complicated task. Multiple studies of CCFs have been made for their
optimization, but their electrical efficiency is still low; for metals approximately 25-30% andeven lower. Fluxtrol, Inc., made an extensive study of electromagnetic processes of CCFs using computer simulation and laboratory tests. This study showed that electrical efficiency of CCFs may be strongly improved by means of optimal design of the whole system with use of magnetic flux controllers. Theoretical results had been confirmed by laboratory tests on mockups and by industrial tests with real melting processes. The presentation contains a description of the computer modeling procedure and major findings. They form a basis for optimal design of electromagnetic systems of CCFs.
Performance prediction of PV & PV/T systems using Artificial Neural Networks ...Ali Al-Waeli
This presentation offers insight into use of ANN and machine learning for various applications in solar energy. Prepared and presented by Dr. Ali H. A. Alwaeli.
New Magnetodielectric Materials for Magnetic Flux ControlFluxtrol Inc.
http://fluxtrol.com
Magnetodielectric materials play an important role in improvement of induction systems for heat treatment, brazing, soldering, sealing and other technologies. This presentation is a continuation of the report made at HIS-01. Current report shows the results of development of new magnetodielectric materials for magnetic flux control and intensive study of their properties.
Master Thesis presentation.
Nanocomposite generator for energy harvesting from a bending movement.
Research: CNTs, Nanocomposites and Piezoelectric effect theoretical background.
Nanocomposite Generator modelling and practical experiment.
Results presentation.
28 Chòm sao được chia thành bốn hướng như sau: Đông, Tây, Nam, Bắc. Người ta dùng những con vật linh mang biểu tượng may mắn để đặt tên gọi là “Tứ tượng”.
Parametric Transient Thermo-Electrical PSPICE Model For A Single And Dual Con...IJERDJOURNAL
ABSTRACT:A parametric macro model for a single and dual conductor power cable for transient thermo-electrical coupled simulation in PSPICE will be derived. The articledepicts the modelling of a simplified, single- and dual conductor cable and its use during simulation. Its verification against experiment and finite element simulation shows a good agreement. The derived single- and dual conductor PSPICE cable macro model enables a quick modelling at system level. It offers a time saving transient thermo-electrical simulation under various thermal conditions and cable geometries and to optimize e.g. size, weight. The approach support the engineer to overlook the thermal influences and temperatures along the power cable under real ‘thermal’ assembling conditions in an e.g. car engine room or aircraft.
Thermal aware task assignment for multicore processors using genetic algorithm IJECEIAES
Microprocessor power and thermal density are increasing exponentially. The reliability of the processor declined, cooling costs rose, and the processor's lifespan was shortened due to an overheated processor and poor thermal management like thermally unbalanced processors. Thus, the thermal management and balancing of multi-core processors are extremely crucial. This work mostly focuses on a compact temperature model of multicore processors. In this paper, a novel task assignment is proposed using a genetic algorithm to maintain the thermal balance of the cores, by considering the energy expended by each task that the core performs. And expecting the cores’ temperature using the hotspot simulator. The algorithm assigns tasks to the processors depending on the task parameters and current cores’ temperature in such a way that none of the tasks’ deadlines are lost for the earliest deadline first (EDF) scheduling algorithm. The mathematical model was derived, and the simulation results showed that the highest temperature difference between the cores is 8 C for approximately 14 seconds of simulation. These results validate the effectiveness of the proposed algorithm in managing the hotspot and reducing both temperature and energy consumption in multicore processors.
Cascade forward neural network based on resilient backpropagation for simulta...Mellah Hacene
Cascade-Forward Neural Network Based on Resilient Backpropagation for Simultaneous Parameters and State Space Estimations of Brushed DC Machines
Advances in Modelling and Analysis B
The use of ekf to estimate the transient thermal behaviour of induction motor...Mellah Hacene
In this paper, a survey is conducted to examine the problem of estimating the states and parameters of an asynchronous machine when some of these measures are not available or the estimation approach is the best solution. The modeling is based on the theory of power dissipation; heat transfer and the rate of temperature increase the stator and the rotor, taking into account the effect of speed on trade. The first purpose of this article is displayed the effect of variable losses depending on the load and constant losses on the thermal behavior of asynchronous motor. According to the sensor’s problems and the obtaining of the thermal information about the rotor, the second goal is the use of a sensorless method like the use of the EKF (extended Kalman filter), some simulation results are given and commented.
Coal-Fired Boiler Fault Prediction using Artificial Neural Networks IJECEIAES
Boiler fault is a critical issue in a coal-fired power plant due to its high temperature and high pressure characteristics. The complexity of boiler design increases the difficulty of fault investigation in a quick moment to avoid long duration shut-down. In this paper, a boiler fault prediction model is proposed using artificial neural network. The key influential parameters analysis is carried out to identify its correlation with the performance of the boiler. The prediction model is developed to achieve the least misclassification rate and mean squared error. Artificial neural network is trained using a set of boiler operational parameters. Subsequenlty, the trained model is used to validate its prediction accuracy against actual fault value from a collected real plant data. With reference to the study and test results, two set of initial weights have been tested to verify the repeatability of the correct prediction. The results show that the artificial neural network implemented is able to provide an average of above 92% prediction rate of accuracy.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
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yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal,
Multi-objective Pareto front and particle swarm optimization algorithms for p...IJECEIAES
The progress of microelectronics making possible higher integration densities, and a considerable development of on-board systems are currently undergoing, this growth comes up against a limiting factor of power dissipation. Higher power dissipation will cause an immediate spread of generated heat which causes thermal problems. Consequently, the system's total consumed energy will increase as the system temperature increase. High temperatures in microprocessors and large thermal energy of computer systems produce huge problems of system confidence, performance, and cooling expenses. Power consumed by processors are mainly due to the increase in number of cores and the clock frequency, which is dissipated in the form of heat and causes thermal challenges for chip designers. As the microprocessor’s performance has increased remarkably in Nano-meter technology, power dissipation is becoming non-negligible. To solve this problem, this article addresses power dissipation reduction issues for high performance processors using multi-objective Pareto front (PF), and particle swarm optimization (PSO) algorithms to achieve power dissipation as a prior computation that reduces the real delay of a target microprocessor unit. Simulation is verified the conceptual fundamentals and optimization of joint body and supply voltages (V thV DD ) which showing satisfactory findings.
Performance assessment of an optimization strategy proposed for power systemsTELKOMNIKA JOURNAL
In the present article, the selection process of the topology of an artificial neural network (ANN) as well as its configuration are exposed. The ANN was adapted to work with the Newton Raphson (NR) method for the calculation of power flow and voltage optimization in the PQ nodes of a 10-node power system represented by the IEEE 1250 standard system. The purpose is to assess and compare its results with the ones obtained by implementing ant colony and genetic algorithms in the optimization of the same system. As a result, it is stated that the voltages in all system nodes surpass 0,99 p.u., thus representing a 20% increase in the optimal scenario, where the algorithm took 30 seconds, of which 9 seconds were used in the training and validation processes of the ANN.
POWER SYSTEM PROBLEMS IN TEACHING CONTROL THEORY ON SIMULINKijctcm
This experiment demonstrates to engineering students that control system and power system theory are not orthogonal, but highly interrelated. It introduces a real-world power system problem to enhance time domain State Space Modelling (SSM) skills of students. It also shows how power quality is affected with real-world scenarios. Power system was modeled in State Space by following its circuit topology in a bottom-up fashion. At two different time instances of the power generator sinusoidal wave, the transmission line was switched on. Fourier transform was used to analyze resulting line currents. It validated the harmonic components, as expected, from power system theory. Students understood the effects of switching transients at various times on supply voltage sinusoid within control theory and learned time domain analysis. They were surveyed to gauge their perception of the project. Results from a before/after assessment analyzed usingT-Tests showed a statistically significant enhanced learning in SSM.
Power System Problems in Teaching Control Theory on Simulinkijctcm
This experiment demonstrates to engineering students that control system and power system theory are not orthogonal, but highly interrelated. It introduces a real-world power system problem to enhance time domain State Space Modelling (SSM) skills of students. It also shows how power quality is affected with real-world scenarios. Power system was modeled in State Space by following its circuit topology in a bottom-up fashion. At two different time instances of the power generator sinusoidal wave, the transmission line was switched on. Fourier transform was used to analyze resulting line currents. It validated the harmonic components, as expected, from power system theory. Students understood the effects of switching transients at various times on supply voltage sinusoid within control theory and learned time domain analysis. They were surveyed to gauge their perception of the project. Results from a before/after assessment analyzed usingT-Tests showed a statistically significant enhanced learning in SSM.
A Review on Thermal Aware Optimization of Three Dimensional Integrated Circui...IJMER
As the technology size has reached upto 14nm, further shrinking creates some major
performance issues. Three dimensional integrated circuits (3D ICs) are gaining importance in the present
arena on account of their advanced features. While stacking of die on die in 3D ICs also result in serious
thermal problems. These thermal issues can be minimised at different physical design stages with the help
of various techniques and algorithms. In this paper an overview of the various methods used for thermal
optimization is presented including techniques at floorplanning, placement and routing. It also includes
the techniques involving the use of TSVs (through-silicon-vias).
This paper deals with subsynchronous resonance (SSR) phenomena in a capacitive series-compensated DFIG-based wind farm. Using both modal analysis and time-domain simulation, it is shown that the DFIG wind farm is potentially unstable due to the SSR mode. In order to damp the SSR, the rotor-side converter (RSC) and grid-side converter (GSC) controllers of the DFIG are utilized. The objective is to design a simple proportional SSR damping controller (SSRDC) by properly choosing an optimum input control signal (ICS) to the SSRDC block, so that the SSR mode becomes stable without decreasing or destabilizing the other system modes. Moreover, an optimum point within the RSC and GSC controllers to insert the SSRDC is identified. Three different signals are tested as potential ICSs including rotor speed, line real power, and voltage across the series capacitor, and an optimum ICS is identified using residue-based analysis and root-locus method. Moreover, two methods are discussed in order to estimate the optimum ICS, without measuring it directly. The studied power system is a 100 MW DFIG-based wind farm connected to a series-compensated line whose parameters are taken from the IEEE first benchmark model (FBM) for computer simulation of the SSR. MATLAB/Simulink is used as a tool for modeling and designing the SSRDC, and power system computer aided design/electromagnetic transients including dc (PSCAD/EMTDC) is used to perform time-domain simulation for design process validation.
Metal welding processes are employed in various indus-tries. Gas welding techniques use the heat from a flame to melt the parts to be joined and a filler material simulta-neously. Extreme thermal loading is applied to the parts being joined, and complex material responses are initi-ated. The steep, localized thermal gradients result in stress concentrations in the welding zone. Consequently, modeling and simulation of welding processes are often complex and challenging. In this technology brief the use of Abaqus for this class of problems is discussed and an example analysis is presented.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD
and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead
compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running
different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
SAP Sapphire 2024 - ASUG301 building better apps with SAP Fiori.pdfPeter Spielvogel
Building better applications for business users with SAP Fiori.
• What is SAP Fiori and why it matters to you
• How a better user experience drives measurable business benefits
• How to get started with SAP Fiori today
• How SAP Fiori elements accelerates application development
• How SAP Build Code includes SAP Fiori tools and other generative artificial intelligence capabilities
• How SAP Fiori paves the way for using AI in SAP apps
SAP Sapphire 2024 - ASUG301 building better apps with SAP Fiori.pdf
28
1. Simulation of Thermal Behavior for
Networks-on-Chip
Tim Wegner, Claas Cornelius, Martin Gag, Andreas Tockhorn, Adelinde Uhrmacher
Institute of Applied Microelectronics and Computer Engineering, University of Rostock,
Richard-Wagner-Str. 31, 18119 Rostock-Warnemuende, Germany
tim.wegner@uni-rostock.de, www.networks-on-chip.com
Abstract—Due to increasing integration densities and the it is the foundation for efficient measurements for thermal
emergence of nanotechnology, especially reliability and power management, that have to be taken in order to reduce tem-
related design aspects become critical for chip design. Since the perature and thermal stress. The basic idea proposed in this
arising problems are enforced by high circuit temperatures, the
need for a possibility to model thermal behavior of a system in paper is to model the dynamic thermal behavior of ICs by
an accurate and physically correct way becomes inevitable. using an equivalent electrical RC circuit. Inside this circuit
Hence, in this paper VulcaNoCs, a SystemC-based simulation heat flow can be described as a current passing through a
environment for systems based on NoCs, is introduced. Vul- thermal resistance and leading to a temperature difference
caNoCs is designed to enable simultaneous execution of both analogous to a voltage. Within this model capacitors represent
high-level system simulation and dynamic modeling of tempera-
ture distributions in NoC-based systems. To emulate a system’s the thermal capacity of a component and resistors represent the
thermal properties equivalent RC-circuits are used, exploiting thermal resistivity for heat flow to and from that component
the dualism between heat flow and electrical phenomena. To in a certain direction [5]. Model generation is done by using
verify the temperature model, VulcaNoCs is compared to a more the SystemC Analog Mixed Signal (AMS) library [7] in order
commonly used SPICE-based approach, exhibiting significant to integrate the model into a simulation environment for NoC-
increases in simulation performance of up to 98,5 % for modeling
a 2×2 NoC, for example. based systems. The resulting simulation environment is called
Index Terms—Network-on-Chip, Temperature Modeling, Inte- VulcaNoCs and supports simultaneous simulation of high-level
grated Circuits system behavior and dynamic thermal behavior. Temperature
modeling can be done at different levels of granularity having
I. I NTRODUCTION major influence on the trade-off between modeling accuracy
The increasing integration density and the emergence of and complexity or performance respectively. The long-term
nanotechnology lead to rising complexity as well as computing objective of this project is to enable real-time modeling and
power of modern multi- and many-core systems. A com- near-term prediction of temperature gradients in NoC-based
munication architecture meeting the communication require- SoCs instead of using cost-intensive physical sensors to mon-
ments of such increasingly complex systems is provided by itor temperature. Thereby, slow reactive countermeasures can
Networks-on-Chip (NoCs). However, the shrinking of device be replaced by proactive measurements to prevent predicted
sizes causes issues related to reliability and robustness to temperature rises in advance. However, in this paper we focus
become dominant factors for system design. On the course on the introduction of VulcaNoCs.
of miniaturization, transistor count per die increases, giving The remainder of this paper is organized as follows. In
rise to a generally higher probability of system failures. Section II we give an overview over existing work done on
Additionally, the probability for a single transistor to fail is thermal modeling and analysis of on-chip systems and outline
also raised, since the decreasing structural size of Integrated the advantages of concurrent simulation of system behavior
Circuits (ICs) leads to higher susceptibility to environmental and dynamic thermal modeling. In Section III, functionality
influences and deterioration. Several physical mechanisms and features of VulcaNoCs are described. Subsequently, in
contributing to these effects are known to be abetted by Section IV first results of the comparison between VulcaNoCs
high temperatures. This leads to temperature having major and an equivalent SPICE model are presented. Finally, in
influence on various parameters of ICs like long-term fail- Section V conclusions are drawn and future work is outlined.
ure rate, lifetime, performance and power consumption. The
relationship between temperature and reliability is given by II. R ELATED W ORK AND D ISCUSSION
the Arrhenius model, describing the influence of temperature Due to the great importance of modeling thermal behavior
changes on the velocity of chemical reactions [1]. Thus, of ICs much work has already been done in this field. [5]
lifetime of ICs depending exponentially on temperature can be proposes to use equivalent electrical RC-circuits in order to
predicted. Two of the most important mechanisms accounting model thermal behavior of an arbitrary chip and its cooling
for deterioration are Electromigration [2] and Time Dependent package defined by a given floorplan. Modeling can be done
Dielectric Breakdown [3] [4]. The stated facts emphasize that on various granularity levels resulting in different degrees of
accurate temperature modeling for ICs is indispensable, since accuracy and speed. The modeling environment uses the aver-
978-1-4244-8971-8/10$26.00 c 2010 IEEE
2. age power dissipated by each functional block over a certain supporting simultaneous simulation of system behavior and
period to compute block temperatures for this period. Power temperature distribution promises to be a good starting point.
profiles are provided by Wattch [6] and have to be determined
III. T HE S IMULATION E NVIRONMENT
in advance by analyzing hardware access statistics gathered
during system simulation. In [8] the approach of [5] is refined In this section the functionality of VulcaNoCs is described.
and used to model thermal behavior of on-chip networks. Additionally, the underlying RC-circuit model as well as the
Therefore, the equivalent RC-circuit model is extended by the available modeling parameters and their expected impact on
inclusion of heat spreading angles. Similar to [5], a separate modeling speed and accuracy are depicted more detailed.
power model called Orion [9] is used to statically determine The cycle accurate NoC simulation environment that provides
on-chip power consumption based on a predefined workload. the basis for VulcaNoCs uses both the core SystemC and
For workload determination the actual simulation of the on- the Transaction-Level Modeling (TLM) libraries. It provides a
chip system has to be performed in advance and the activity high degree of parameterization permitting for example deter-
profiles have to be captured. In [10] Liu et al. generate a mination of NoC size, link width, simulation duration, sample
SPICE netlist in order to model the equivalent thermal RC- period and individual configuration of Intellectual Property
network of a chip on the granularity level of standard cells Cores (IPCs) regarding load factors and packet lengths for
for application in thermal-aware placement and scheduling instance. Furthermore, it includes a comprehensive set of
tools. To model on-chip temperature distribution, the average monitoring functions to trace network health (e.g. blocked
power consumption is estimated based on annotated switching paths or deadlocks), latencies and activity profiles. Every time
activity of random generated vectors and is then delivered the aforementioned sample period expires, all statistics are
to the simulation environment. The methodology presented captured and reset until simulation has finished. To preserve
by Tockhorn et al. focuses on modeling the dynamic nature the integrity of the whole simulation environment VulcaNoCs
of temperature distribution in many-core systems based on was developed by using the novel SystemC AMS library [7].
NoCs [11]. For this purpose, the thermal properties of accord- This has the advantage that thermal behavior can be modeled
ing systems are modeled by equivalent RC-circuits, exploiting without dependence on external tools for estimation of power
the dualism between electrical and thermal flows of energy. consumption. Since such tools usually require activity infor-
After a SPICE netlist is generated representing the RC-circuit mation for the whole simulation time, power calculation during
of the underlying NoC, current sources are attached to the system simulation is not feasible preventing parallel execution
RC-network incorporating sources of thermal energy. During of system simulation and thermal modeling. For the purpose
circuit simulation current values, calculated from previously of modeling thermal behavior of NoCs, VulcaNoCs reverts
captured activity statistics, are fed into the network. to the well-known dualism of electrical and thermal energy
As a consequence of all models relying on data for power flows at which heat flow can be described as an electrical
consumption, that has to be provided by anticipant, simulation current passing through a thermal resistance and leading to a
of thermal behavior can only be accomplished after the actual temperature difference analogous to a voltage [5].
system simulation. This is due to the fact that all approaches
R R
revert to external tools for the extraction of values regarding Current
IPC IPC Source
power consumption, which in turn depend on availability
of component activity. On the one hand, this allows for R R
application of such models during design phase (e.g. for
IPC IPC
thermal-aware mapping and placement). On the other hand, the
possibility for thermal modeling and temperature monitoring
of NoC-based systems during operation is excluded a priori. Fig. 1. 2×2 NoC mapped on a grid of 4×4 RC-tiles (Block model)
For this reason we introduce VulcaNoCs, a SystemC-based
simulation environment to account for simultaneous simulation Fig. 1 shows a 2×2 NoC mapped on a grid of 4×4 RC-tiles.
of system behavior and temperature distribution. Unlike the Each tile consists of one vertical and 4 lateral thermal resistors,
aforementioned methodologies, VulcaNoCs does not rely on a current source and a thermal capacitor. During simulation
any external tools. This independency is achieved by using the temperature of a RC-tile is represented by the voltage
the Analog Mixed Signal (AMS) library recently released drop over the associated capacitor. The vertical resistor models
by the Open SystemC Initiative (OSCI) [7]. Thereby, the the connection to the cooling package of the chip. Thermal
opportunity to model the thermal properties of a system within capacitors are used in order to account for the delay before a
the actual simulation environment is provided. In addition change in power results in temperature variation. Besides the
to thermal-aware design, VulcaNoCs will be deployable to rather coarse-grained block modeling, VulcaNoCs supports 2
a much wider range of applications including modeling of more precise models in which a functional block is resolved
temperature distributions and proactive thermal management into multiple RC-tiles. This results in a more accurate but also
during system operation. Admittedly, a multiplicity of modifi- more complex model of the temperature distribution across
cations and optimizations still has to be performed to achieve the chip. For high resolution models only the central RC-
this objective, but the current implementation of VulcaNoCs tile of a block is assigned a current source. In addition to
3. modeling the chip, VulcaNoCs models the cooling package modules and checked for solvability (4). Hence, depending on
consisting of a heat spreader and a heat sink, following the NoC size and desired model resolution, elaboration takes a
approach in [5]. This contributes to a more realistic model more or less big fraction of the overall simulation runtime.
behavior because most of the heat is dissipated along the path After elaboration has finished, simulation is started by setting
through spreader and sink to the ambience. Both, spreader the initial conditions of all instantiated ELN primitives (5)
and sink are resolved in 5 RC-tiles omitting current sources, followed by the actual simulation of the NoC and its thermal
since the cooling package does not produce heat itself. Due behavior (6). Corresponding to the sample period, the ELN
to poor thermal conductivity heat dissipation into the die’s equation system is solved numerically and for each period the
ceramic insulating cap is neglected. To account for differ- newly calculated currents are injected into the network. Results
ent SoC and cooling package configurations, VulcaNoCs is for temperature are reported periodically as well.
highly parameterized. Amongst others, parameters for model The essential advantage of VulcaNoCs is that it combines the
resolution (Block; Res1: 1 Tile/Router; Res2: 4 Tiles/Router), assets of both SPICE-based netlist simulation and SystemC-
thermal conductivity and capacitance, geometrical dimensions based NoC modeling. On the one hand, the ELN computation
(die, spreader, sink thickness; edge length of IPCs and routers) model provides the same physically correct electrical primi-
and power consumption per flit (for IPCs, routers and links) tives that SPICE offers. Thereby, accurate modeling of thermal
are defined. Die size is calculated by means of the edge length behavior is ensured. On the other hand, the static nature of a
of IPCs and routers as well as NoC size. Heat spreader size SPICE netlist is eliminated making it possible to inject stimuli
amounts to die size multiplied by 1,5, while heat sink size is and to monitor temperature gradients during simulation. Ad-
defined as spreader size multiplied by 2. The sample period ditionally, temperature modeling no longer relies on external
controls the time of simulation after which the voltage drops tools for the provision of values for power consumption.
over the capacitors are captured and the newly calculated
currents are fed into the RC-network, depending on the activity IV. E XPERIMENTS AND R ESULTS
of the functional blocks during the previously passed period. In this section first results concerning modeling accuracy
and simulation performance of VulcaNoCs are presented. To
NoC Geometry, Chip Geometry, provide for comparable values, simulations are additionally
Simulation Model Accuracy
Parameters performed using an equivalent HSPICE model like it is pro-
Sample Period
posed in [11]. Note that the HSPICE model does not support
1
block model resolution.
NoC Setup ELN Setup 2
For our experiments we assume die, spreader and sink thick-
Run Prede- ness to be 0,6 mm, 1 mm and 6,8 mm. The edge lengths of
fined Time
Time Step ELN IPC and router are 1,85 mm and 0,141 mm resulting in a die
Calculation & 3 Elaboration
Periodic NoC Propagation of about 4×4 mm for an 2×2 NoC. Values for thermal con-
Simulation 6
Equation Setup & 4 ductivity are 100 W/m∗K for the die (i.e. silicon), 400 W/m∗K
Solvability Check
for heat spreader and sink (i.e. copper) and 2 W/m∗K for
Initialization 5
the die package (i.e. ceramics). Thermal capacitance is set to
Periodic Output: ELN Time-
Component Activity
Periodic Equation
domain 1,75∗106 J/������3 ∗K for silicon and 3,55∗106 J/������3 ∗K for copper.
Solving
6 Simulation
Ambience is assumed to be at a fixed temperature of 45 ∘ C.
Periodic Ouput:
Temperature Profile
NoC configuration is a regular mesh topology with a clock
frequency of 1 GHz and a router buffer depth of 6 flits. During
Fig. 2. Simulation flow of VulcaNoCs simulation all IPCs generate packets with a probability of 50 %
using random destination addresses.
With the given parameter values for NoC geometry and To estimate simulation performance and accuracy of different
simulation VulcaNoCs is executed according to the flow model resolutions a 2×2 NoC was simulated over 1 ms to com-
depicted in Fig. 2. First, the NoC topology is set up (1) pare VulcaNoCs and the HSPICE-based temperature model.
whereas the IPCs are represented as sending and receiving As expected, within both models different resolutions have
units. Subsequently, the equivalent RC-network is established only negligible impact on average temperature (see Fig. 3).
according to the defined parameters. The required descriptions With values of 0,009 ∘ C (Block) and 0,006 ∘ C (Res1 and Res2)
for the electrical components (i.e. resistors, capacitors, current for average deviation with respect to the HSPICE-based model
sources) are extracted from the SystemC AMS library using using Res2, discrepancy between both modeling approaches
the Electrical Linear Networks (ELN) model of computation. is vanishingly small. However, these differences apparently
Execution of an ELN model is divided into elaboration and increase over time and originate from the disparate implemen-
time-domain simulation. During elaboration electrical primi- tation of the used current sources. HSPICE uses Piecewise
tives are declared and instantiated (2). Additionally, sample Linear Sources (PWL), which model currents by pairs of
period for all ELN primitives is defined and propagated points in time and according current values. Therefore, current
throughout the network (3). Furthermore, the differential equa- between 2 points in time follows a linear function. By contrast,
tion system is composed from all contributing ELN primitive current sources applied for VulcaNoCs use these pairs to form
4. a continuous-time signal. Since this is a more lifelike way of V. C ONCLUSION AND F UTURE W ORK
modeling current flows, we hold that deviations in temperature In this paper we presented VulcaNoCs, a SystemC-based
between VulcaNoCs and HSPICE are at most a sign of higher environment for simultaneous simulation of system behavior
accuracy for VulcaNoCs. Performance results for temperature and temperature distribution in NoC-based Systems-on-Chip.
modeling have to be examined more differentiated as modeling A wide range of topological, geometrical and technological
in VulcaNoCs is divided into phases of elaboration and sim- parameters allows for a flexible and detailed description of
ulation. For the purpose of comparison, only the overall time the targeted chip and the associated cooling package. By
taken for HSPICE is considered because simulation cannot comparing VulcaNoCs to an equivalent HSPICE model the
be divided in similar sub-phases. Table I shows the results benefits of VulcaNoCs regarding performance of the actual
regarding time spent for elaboration ������������������������������ and the actual mod- simulation were highlighted.
eling of temperature ������������������������,������ℎ������������������������������ . As expected, elaboration Nevertheless, it would be desirable to avoid the strongly time
time for VulcaNoCs increases drastically with rising model consuming part of elaboration whenever possible. This would
resolution yielding 1,817 s for Block resolution (16 RC-tiles), be of convenience if multiple simulations of the same SoC
73,438 s for Res1 resolution (784 RC-tiles) and 5005,276 s for (i.e. with identical modeling parameters) shall be performed
Res2 resolution (3136 RC-tiles). Despite the fact that high or if a running simulation is interrupted and then resumed.
resolutions cause a serious penalty to overall performance, Since it is planned to modify VulcaNoCs for the purpose of
they are still valuable if a detailed and fine-grained depiction of thermal monitoring and management during system operation,
temperature profiles is required at all costs. Thus, performance it is conceivable to equip VulcaNoCs with a set of differ-
has to be traded off against detailedness of modeling. However, ent pre-elaborated SoC models so that only the appropiate
VulcaNoCs’ model resolution has almost no impact on the model has to be selected and temperature modeling can be
time taken for simulation, while HSPICE simulation runtime started directly. Another possibility is to use a save-and-
is significantly affected by high resolutions. This results in restore technique following the approach in [12] for example.
VulcaNoCs needing only 37,2 % (for Res1) and 1,5 % (for The storage of elaboration state is already proposed in the
Res2) of the time that is required by HSPICE. For this reason, SystemC Language Reference Manual [13]. However, the
if elaboration is excluded, VulcaNoCs clearly outperforms the ultimate objective is to enhance VulcaNoCs for the deployment
HSPICE model especially for high resolutions. This behavior in near-term prediction of thermal behavior. Thereby, the need
is anticipated to be enforced with growing NoC sizes, but for comparatively slow and expensive physical temperature
can only be exploited if the nonrecurring elaboration phase sensors could be eliminated and reactive thermal management
is somehow backed up. For repeated temperature modeling of measurements could be replaced by proactive alternatives.
identical NoC configurations, this backup might be restored.
Thereby, unnecessary repetition of elaboration can be avoided ACKNOWLEDGMENT
and computation overhead can be reduced. The authors would like to thank Sven Poeggel for his
contribution to this research project.
45,35
VulcaNoCs Block
45,3
VulcaNoCs Res1 R EFERENCES
VulcaNoCs Res2
HSpice Res1
HSpice Res2
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