This document describes the development of macromodels for an LVDS output driver and receiver using Spice simulations provided by the manufacturer. The driver model includes feedback to accurately model the relationship between differential outputs. DC and TDR analyses were used to optimize static characteristics and dynamic behaviors like capacitance. The final models reflect the actual device architecture and match simulation results like output waveforms and impedances.
Three Step Table Validation Pharmasug 2007snail_chen
I wrote this when I joined Forest in 2006. It extracts the main body of Table and compares it with the validator\'s output. It can pinpoint the differences and is extremely efficient and accurate. Valuable tool for large table validation. Presented at Pharmasug 2007, Denver
VECTOR VS PIECEWISE-LINEAR FITTING FOR SIGNAL AND POWER INTEGRITY SIMULATIONPiero Belforte
The basic concepts of two fitting methods suitable for signal and power integrity simulation up to multi-gigabit/sec rates are presented. The traditional method is based on Vector Fitting (VF), a well known technique to approximate complex functions of frequency by a rational polynomial expression in terms of poles and residues. The second is a full time-domain approach mainly based on behavioral models supported by the Digital Wave Simulator.
PWLFIT/DWS advantages over VECTFIT/Spice can be summarized with the 3S acronym: SIMPLICITY, STABILITY and SPEED.
SIMPLICITY because the pwl fitting of a time-domain behavior is a very fast, explicit and intuitive process that doens't need the solution of implicit equations as required by Vector fitting. Time-domain S-parameter of actual devices in matched conditions shows simpler behaviors than the corresponding impedance in the frequency domain.
STABILITY because the use of Digital Wave processing is intrinsically very stable. Extracted pwl behaviors processed by fast convolution within DWS are unconditionally stable if the source behavior is stable. This means that NO numerical conditioning is required. As known Vector Fitting often require numerical conditioning to get stable results.
SPEED: time-domain pwl fitting is a very fast process. DWS simulations are also very fast even at very small time steps required by multigigabit system analysis. DWS/SPICE typical speedups are 100X for traditional VF derived RLC-TL circuits and up to 10000X when using pwl Behavioral Models in time domain.
Three Step Table Validation Pharmasug 2007snail_chen
I wrote this when I joined Forest in 2006. It extracts the main body of Table and compares it with the validator\'s output. It can pinpoint the differences and is extremely efficient and accurate. Valuable tool for large table validation. Presented at Pharmasug 2007, Denver
VECTOR VS PIECEWISE-LINEAR FITTING FOR SIGNAL AND POWER INTEGRITY SIMULATIONPiero Belforte
The basic concepts of two fitting methods suitable for signal and power integrity simulation up to multi-gigabit/sec rates are presented. The traditional method is based on Vector Fitting (VF), a well known technique to approximate complex functions of frequency by a rational polynomial expression in terms of poles and residues. The second is a full time-domain approach mainly based on behavioral models supported by the Digital Wave Simulator.
PWLFIT/DWS advantages over VECTFIT/Spice can be summarized with the 3S acronym: SIMPLICITY, STABILITY and SPEED.
SIMPLICITY because the pwl fitting of a time-domain behavior is a very fast, explicit and intuitive process that doens't need the solution of implicit equations as required by Vector fitting. Time-domain S-parameter of actual devices in matched conditions shows simpler behaviors than the corresponding impedance in the frequency domain.
STABILITY because the use of Digital Wave processing is intrinsically very stable. Extracted pwl behaviors processed by fast convolution within DWS are unconditionally stable if the source behavior is stable. This means that NO numerical conditioning is required. As known Vector Fitting often require numerical conditioning to get stable results.
SPEED: time-domain pwl fitting is a very fast process. DWS simulations are also very fast even at very small time steps required by multigigabit system analysis. DWS/SPICE typical speedups are 100X for traditional VF derived RLC-TL circuits and up to 10000X when using pwl Behavioral Models in time domain.
A simple 10-cell RL-TL test circuit has been simulated using two completely different simulators: Microcap10 (MC10, evaluation version) and DWS. The first one is a classical Nodal Analysis Spice family simulator with a good model for Transmission Lines (TL). DWS (Digital Wave Simulator) is based on completely different DSP algorithms (Digital Wave Network equivalent)
The latest version of DWS (Digital Wave Simulator) user manual.
DWS 8.5 is included in the latest version 3.0 of Spicy SWAN available both on web and mobile.
DWS vs CST CABLE STUDIO SIMULATION SPEEDUPPiero Belforte
A classical way to model lossy TL is to apply the Vector Fitting (VF) technique to theoretical frequency domain impedance expression taking into account both conductor and dielectric losses. The resulting poles and zeros can be implemented by a cascade of unit cells containing a lumped RLC circuit and a transmission line. To get a wideband (40Ghz) model a suitable number of cells and a sub-picosecond simulation time step are required to get accurate results. This VF technique has been applied to a RG58 coaxial cable and the resulting circuit has been simulated in time domain using DWS. The results are then compared at 40Gb/s to those coming from CST Cable Studio up showing a very good agreement with a DWS/CST speedup of about 710X.
Ls catalog thiet bi dien mms(e) dienhathe.vnDien Ha The
Khoa Học - Kỹ Thuật & Giải Trí: http://phongvan.org
Tài Liệu Khoa Học Kỹ Thuật: http://tailieukythuat.info
Thiết bị Điện Công Nghiệp - Điện Hạ Thế: http://dienhathe.org
Catalog LS, Catalog,
Catalog Thiết Bị Điện LS, Catalog Thiết Bị Điện,
http://dienhathe.com,
Chi tiết các sản phẩm khác của LS tại https://dienhathe.com
Xem thêm các Catalog khác của LS tại https://dienhathe.info
Để nhận báo giá sản phẩm LS vui lòng gọi: 0907.764.966
A simple 10-cell RL-TL test circuit has been simulated using two completely different simulators: Microcap10 (MC10, evaluation version) and DWS. The first one is a classical Nodal Analysis Spice family simulator with a good model for Transmission Lines (TL). DWS (Digital Wave Simulator) is based on completely different DSP algorithms (Digital Wave Network equivalent)
The latest version of DWS (Digital Wave Simulator) user manual.
DWS 8.5 is included in the latest version 3.0 of Spicy SWAN available both on web and mobile.
DWS vs CST CABLE STUDIO SIMULATION SPEEDUPPiero Belforte
A classical way to model lossy TL is to apply the Vector Fitting (VF) technique to theoretical frequency domain impedance expression taking into account both conductor and dielectric losses. The resulting poles and zeros can be implemented by a cascade of unit cells containing a lumped RLC circuit and a transmission line. To get a wideband (40Ghz) model a suitable number of cells and a sub-picosecond simulation time step are required to get accurate results. This VF technique has been applied to a RG58 coaxial cable and the resulting circuit has been simulated in time domain using DWS. The results are then compared at 40Gb/s to those coming from CST Cable Studio up showing a very good agreement with a DWS/CST speedup of about 710X.
Ls catalog thiet bi dien mms(e) dienhathe.vnDien Ha The
Khoa Học - Kỹ Thuật & Giải Trí: http://phongvan.org
Tài Liệu Khoa Học Kỹ Thuật: http://tailieukythuat.info
Thiết bị Điện Công Nghiệp - Điện Hạ Thế: http://dienhathe.org
Catalog LS, Catalog,
Catalog Thiết Bị Điện LS, Catalog Thiết Bị Điện,
http://dienhathe.com,
Chi tiết các sản phẩm khác của LS tại https://dienhathe.com
Xem thêm các Catalog khác của LS tại https://dienhathe.info
Để nhận báo giá sản phẩm LS vui lòng gọi: 0907.764.966
A Survey and Experimental Verification of Modular Multilevel ConvertersIAES-IJPEDS
This article primarily brings to limelight the Multi-level converters review and specifically the form and function of modular multilevel converter (MMC) with their modulation, design considerations, balancing issues, control schemes, and applications. This article intends to make a detailed analysis of MMC with their controller related issues in comprehensive manner. It is an approach for MMC design and modulation schemes in easy manner. Furthermore, a five level MMC have been designed with optimal controller and verified by its experimental results and explored. In addition to that, this approach draws strategic conclusions on MMC towards making the system more robust in operation, less complex in design and control.
Catalog LS, Catalog,
Catalog Thiết Bị Điện LS, Catalog Thiết Bị Điện,
http://dienhathe.com,
Chi tiết các sản phẩm khác của LS tại https://dienhathe.com
Xem thêm các Catalog khác của LS tại https://dienhathe.info
Để nhận báo giá sản phẩm LS vui lòng gọi: 0907.764.966
Ls catalog thiet bi dien mms e_0901_dienhathe.vnDien Ha The
Khoa Học - Kỹ Thuật & Giải Trí: http://phongvan.org
Tài Liệu Khoa Học Kỹ Thuật: http://tailieukythuat.info
Thiết bị Điện Công Nghiệp - Điện Hạ Thế: http://dienhathe.org
The recent development of the automated version of PWLFIT[1,2,4] opens the door also to hybrid PWL/VF[5,8,9] methods. This further possibility expands up to six the number of possible alternatives to modeling and simulation methods
Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...Piero Belforte
This paper describes PWLFIT+, an extension to the frequency domain ofPWLFIT, a new paradigm in time-domain macromodel ing for linear multiportsystems, based on a piecewise-linea r (PWL) behavioral representation of the S-parameters step response.
A parallel-plate capacitor implemented by a rectangular double-sided printed circuit board is characterized by means a stimulus signal injected at a corner. Both frequency-domain (VNA) and time-domain (TDR) techniques are utilized to determine the step response of the reflected wave (S11) to be compared to the theoretical behavior of the equivalent parallel plate capacitance. A commercial application is utilized to convert the frequency domain tabulated data of the frequency response into the corresponding TDR response. A very accurate and fast 2D TLM (Transmission Line Model) model can be easily extracted from these single time-domain experimental responses.
Automated Piecewise-Linear Fitting of S-Parameters step-response (PWLFIT) for...Piero Belforte
An innovative full time-domain macromodeling
technique for general, linear multiport systems is described. The
methodology is defined in a digital wave framework and timedomain
simulations are performed via an efficient method called
Segment Fast Convolution (SFC). It is based on a piecewiseconstant
(PWC) model of the impulse response of scattering
parameters, computed starting from a piecewise-linear fitting
of their step response (PWLFIT). Such step response is directly
available from time-domain reflectometer measurements
(TDR/TDT) or equivalent simulations. The model-building phase
is performed in a fast automated framework and an analytic
formulation of computational efficiency of the SFC with respect to
the standard time-domain convolution is given. Two application
examples are used to verify the PWLFIT performance and to
perform a comparison with macromodeling methods defined in
the frequency-domain, such as Vector Fitting (VF).
Index Terms—Digital wave models, time-domain macromodeling,
S-parameters, step response.
Multigigabit modeling of hi safe+ flying probe fp011Piero Belforte
This document describes the modeling methodology used to assess the performance of these probes in terms of allowed digital bandwidth of signals chosen for temporary fault insertion trials. This methodology is based on time-domain characterization of Scattering parameters (TDR/TDT) and subsequent extraction of a Behavioral Time-domain Model (BTM) [13] of the probe itself. This technique called PWLFIT (Piece-Wise Linear FITting) [14] [15]is supported by the Digital Wave Simulator DWS [16] [17] and its companion tool DWV [18] developed starting in the early '90s for very fast modeling and simulation of high-speed circuits and systems.
HDT (High Design Technology) related content on Cseltmuseum Dec. 13 2017Piero Belforte
HDT (High Design Technology) has been a high-tech startup founded at the end of '80s for the development of state-of-the art predictive CAE tools in the field of Signal/Power Integrity and EMC. Here the collection of posted content related to HDT on the CSELTMUSEUM Facebook public group.
HiSAFE related content on Cseltmuseum Dec. 13 2017 Piero Belforte
HiSAFE is a wideband (20Gbps) Fault Insertion System for Testing purposes. Here the collection of posted content related to HiSAFE on the CSELTMUSEUM Facebook public group.
In his public lecture, Christian Timmerer provides insights into the fascinating history of video streaming, starting from its humble beginnings before YouTube to the groundbreaking technologies that now dominate platforms like Netflix and ORF ON. Timmerer also presents provocative contributions of his own that have significantly influenced the industry. He concludes by looking at future challenges and invites the audience to join in a discussion.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfPaige Cruz
Monitoring and observability aren’t traditionally found in software curriculums and many of us cobble this knowledge together from whatever vendor or ecosystem we were first introduced to and whatever is a part of your current company’s observability stack.
While the dev and ops silo continues to crumble….many organizations still relegate monitoring & observability as the purview of ops, infra and SRE teams. This is a mistake - achieving a highly observable system requires collaboration up and down the stack.
I, a former op, would like to extend an invitation to all application developers to join the observability party will share these foundational concepts to build on:
Threats to mobile devices are more prevalent and increasing in scope and complexity. Users of mobile devices desire to take full advantage of the features
available on those devices, but many of the features provide convenience and capability but sacrifice security. This best practices guide outlines steps the users can take to better protect personal devices and information.
Why You Should Replace Windows 11 with Nitrux Linux 3.5.0 for enhanced perfor...SOFTTECHHUB
The choice of an operating system plays a pivotal role in shaping our computing experience. For decades, Microsoft's Windows has dominated the market, offering a familiar and widely adopted platform for personal and professional use. However, as technological advancements continue to push the boundaries of innovation, alternative operating systems have emerged, challenging the status quo and offering users a fresh perspective on computing.
One such alternative that has garnered significant attention and acclaim is Nitrux Linux 3.5.0, a sleek, powerful, and user-friendly Linux distribution that promises to redefine the way we interact with our devices. With its focus on performance, security, and customization, Nitrux Linux presents a compelling case for those seeking to break free from the constraints of proprietary software and embrace the freedom and flexibility of open-source computing.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
GraphSummit Singapore | The Art of the Possible with Graph - Q2 2024Neo4j
Neha Bajwa, Vice President of Product Marketing, Neo4j
Join us as we explore breakthrough innovations enabled by interconnected data and AI. Discover firsthand how organizations use relationships in data to uncover contextual insights and solve our most pressing challenges – from optimizing supply chains, detecting fraud, and improving customer experiences to accelerating drug discoveries.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
- Reduction in onboarding time from 5 weeks to 1 day
- Improved developer experience and productivity through actionable findings and reduction of false positives
- Maintenance of superior security standards and inherent policy enforcement with Authorization to Operate (ATO)
Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
Sudheer Mechineni, Head of Application Frameworks, Standard Chartered Bank
Discover how Standard Chartered Bank harnessed the power of Neo4j to transform complex data access challenges into a dynamic, scalable graph database solution. This keynote will cover their journey from initial adoption to deploying a fully automated, enterprise-grade causal cluster, highlighting key strategies for modelling organisational changes and ensuring robust disaster recovery. Learn how these innovations have not only enhanced Standard Chartered Bank’s data infrastructure but also positioned them as pioneers in the banking sector’s adoption of graph technology.
SAP Sapphire 2024 - ASUG301 building better apps with SAP Fiori.pdfPeter Spielvogel
Building better applications for business users with SAP Fiori.
• What is SAP Fiori and why it matters to you
• How a better user experience drives measurable business benefits
• How to get started with SAP Fiori today
• How SAP Fiori elements accelerates application development
• How SAP Build Code includes SAP Fiori tools and other generative artificial intelligence capabilities
• How SAP Fiori paves the way for using AI in SAP apps
Essentials of Automations: The Art of Triggers and Actions in FMESafe Software
In this second installment of our Essentials of Automations webinar series, we’ll explore the landscape of triggers and actions, guiding you through the nuances of authoring and adapting workspaces for seamless automations. Gain an understanding of the full spectrum of triggers and actions available in FME, empowering you to enhance your workspaces for efficient automation.
We’ll kick things off by showcasing the most commonly used event-based triggers, introducing you to various automation workflows like manual triggers, schedules, directory watchers, and more. Plus, see how these elements play out in real scenarios.
Whether you’re tweaking your current setup or building from the ground up, this session will arm you with the tools and insights needed to transform your FME usage into a powerhouse of productivity. Join us to discover effective strategies that simplify complex processes, enhancing your productivity and transforming your data management practices with FME. Let’s turn complexity into clarity and make your workspaces work wonders!
UiPath Test Automation using UiPath Test Suite series, part 5DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 5. In this session, we will cover CI/CD with devops.
Topics covered:
CI/CD with in UiPath
End-to-end overview of CI/CD pipeline with Azure devops
Speaker:
Lyndsey Byblow, Test Suite Sales Engineer @ UiPath, Inc.
Alt. GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using ...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Removing Uninteresting Bytes in Software FuzzingAftab Hussain
Imagine a world where software fuzzing, the process of mutating bytes in test seeds to uncover hidden and erroneous program behaviors, becomes faster and more effective. A lot depends on the initial seeds, which can significantly dictate the trajectory of a fuzzing campaign, particularly in terms of how long it takes to uncover interesting behaviour in your code. We introduce DIAR, a technique designed to speedup fuzzing campaigns by pinpointing and eliminating those uninteresting bytes in the seeds. Picture this: instead of wasting valuable resources on meaningless mutations in large, bloated seeds, DIAR removes the unnecessary bytes, streamlining the entire process.
In this work, we equipped AFL, a popular fuzzer, with DIAR and examined two critical Linux libraries -- Libxml's xmllint, a tool for parsing xml documents, and Binutil's readelf, an essential debugging and security analysis command-line tool used to display detailed information about ELF (Executable and Linkable Format). Our preliminary results show that AFL+DIAR does not only discover new paths more quickly but also achieves higher coverage overall. This work thus showcases how starting with lean and optimized seeds can lead to faster, more comprehensive fuzzing campaigns -- and DIAR helps you find such seeds.
- These are slides of the talk given at IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW 2022.
2. Data redazione: 2 marzo 2013 Pagina 2 di 21
Index
1. Introduction..........................................................................................................................3
2. Acronyms.............................................................................................................................3
3. Device description................................................................................................................3
4. Model architecture................................................................................................................3
5. DC behavioral optimization...................................................................................................5
6. TDR simulated analysis........................................................................................................8
7. Output waveform................................................................................................................13
8. Differential receiver VI characteristic...................................................................................16
9. TDR characterization of the differential receiver..................................................................17
10. 400mV Driver Model Netlist (LVDSOUT_4_B) ....................................................................18
11. 800mV driver model netlist.................................................................................................19
12. Output waveform validation netlist (400mV driver) ..............................................................20
13. Differential TDR validation netlist (400mV driver)................................................................20
14. LVDSIN model netlist .........................................................................................................21
15. LVDSIN common model TDR analysis netlist .....................................................................21
3. Data redazione: 2 marzo 2013 Pagina 3 di 21
1. Introduction
This report describes the procedure used to develop THRIS models for the LSI logic cells
LVDSOUTR1 and LVDSINRI, a differential swing-programmable driver and a differential receiver
respectively.
The models has been extracted starting from Spice simulations (the Hspice model was available from
the manufacturer):
- dc characteristics (driver/receiver)
- unloaded output waveform (driver)
- balanced and common mode TDR (driver/receiver).
The driver’s model has been developed for two different output voltage swings: 400mV and 800mV
nominal.
2. Acronyms
DUT Device Under Test
TDR Time Domain Reflectometer
THRIS Telecom Hardware Robustness Inspection System
PWL Piece Wise Linear approximation
3. Device description
A scheme of the driver cell is reported below:
Figura 3.1 Architectural scheme of the output cell
The termination resistors are included in the cells. The current suppliers (high impedance) force a
current in the load. The common mode voltage is controlled by means of a feedback that senses the
common mode voltage and controls the current pumps. The user sets the reference common mode
voltage (1.2V in this case).
Any external load asymmetry is detected by the feedback that modifies the quiescent value of the
current pumps in order to stabilize the common mode voltage.
The four switches control the current flow direction.
4. Model architecture
4. Data redazione: 2 marzo 2013 Pagina 4 di 21
Normally, the standard methodology used in THRIS models differential drivers as a couple of single
ended outputs driven by complementary stimuli. This approach introduces an advantage in flexibility
and modeling of the driver. The drawback is the complete decoupling of the two drivers. For typical
drivers this is not a problem.
In this application, the common mode reaction introduces a strong relationship between the differential
outputs, as shown in the DC characteristics Spice simulation reported below.
Fig. 4.1: DC analysis response of the LVDSOUTR1 output cell (400mV swing) simulated with Hspice.
The simulation scheme adopted is reported below. The asymmetrical stimulation (the current is
injected in one output only) has been chosen to stimulate both common mode and differential mode
reactions.
Fig.4.2 DC analysis scheme
From figure 4.1 it is possible to note the behavior of the output left open. This highlights the strong
relationship between the two outputs that make impossible the usage of two stand-alone models to
simulate the complementary outputs. As a consequence, the output cell has been represented by
customized model architecture (by using the “Special Component” modeling methodology available in
THRIS).
A first trial to reproduce the DC output behavior by means of model without internal reaction failed. In
fact, the simulation of the macromodel (with SPRINT) showed a completed different behavior at the
output pin left unloaded (its slope was reversed).
At the end, a model with feedback has been chosen.
The final macromodel structure reflects the actual architecture of the device. The optimization
procedure has been the following:
- DC behavioral optimization,
- TDR behavioral optimization
7.000E-01
8.000E-01
9.000E-01
1.000E+00
1.100E+00
1.200E+00
1.300E+00
1.400E+00
1.500E+00
1.600E+00
1.700E+00
1.800E+00
1.900E+00
2.000E+00
2.100E+00
2.200E+00
2.300E+00
2.400E+00
2.500E+00
-1.000E-02
-9.000E-03
-8.000E-03
-7.000E-03
-6.000E-03
-5.000E-03
-4.000E-03
-3.000E-03
-2.000E-03
-1.000E-03
0.000E+00
1.000E-03
2.000E-03
3.000E-03
4.000E-03
5.000E-03
6.000E-03
7.000E-03
8.000E-03
9.000E-03
1.000E-02
I out (A)
Vout(V)
voltage out
voltage outn
5. Data redazione: 2 marzo 2013 Pagina 5 di 21
- Output waveform optimization
5. DC behavioral optimization
The macromodel architecture is the following:
Fig.5.1: Macromodel structure: 1001 is the stimulus node, 1 and 3 are the output nodes,
2000 and 3000 are power and ground nodes.
The DC analysis involves the following primitives:
VCMREF
VCMTERM
G_UP
G_DOWN
The common mode voltage (node 2) is compared to a reference value (VCMREF). Any deviation
modifies the quiescent current value of G_UP and G_DOWN. The quiescent value (6.3mA for the
driver set at 400mV output swing and 11mA for the driver set at 800mV) has been calculated from the
static characteristics (Iout=0) simulated by Spice.
The VCMTERM power supply and its 30ohm resistor has been calculated from the resistance value
extracted from the quiescent value of the single-ended TDR response (about 80ohm = 50(R1) + 30
assigned to VCMTERM).
6. Data redazione: 2 marzo 2013 Pagina 6 di 21
The DC analysis characteristic slopes are optimized manually (Cut and Try) by modifying the static
PWL of G_UP and G_DOWN. The resulting characteristics are reported below:
Fig.5.1: Static characteristics simulated with Hspice (400mV output swing)
Fig.5.2: Static characteristics of the macromodel simulated with SPRINT (400mV output swing)
The saturation effects (unbalanced current larger than 5mA) are not simulated. In any case there is a
very small possibility to have this strong asymmetry in normal operation conditions.
7.000E-01
8.000E-01
9.000E-01
1.000E+00
1.100E+00
1.200E+00
1.300E+00
1.400E+00
1.500E+00
1.600E+00
1.700E+00
1.800E+00
1.900E+00
2.000E+00
2.100E+00
2.200E+00
2.300E+00
2.400E+00
2.500E+00
-7.000E-03
-6.000E-03
-5.000E-03
-4.000E-03
-3.000E-03
-2.000E-03
-1.000E-03
0.000E+00
1.000E-03
2.000E-03
3.000E-03
4.000E-03
5.000E-03
6.000E-03
7.000E-03
I out (A)
Vout(V)
voltage out
voltage outn
7. Data redazione: 2 marzo 2013 Pagina 7 di 21
The same optimization has been performed for the 800mV output swing driver.
Fig.5.3: Static characteristics simulated with Hspice (800mV output swing)
Fig.5.4: Static characteristics of the macromodel simulated with SPRINT (800mV output swing)
2.000E-01
3.000E-01
4.000E-01
5.000E-01
6.000E-01
7.000E-01
8.000E-01
9.000E-01
1.000E+00
1.100E+00
1.200E+00
1.300E+00
1.400E+00
1.500E+00
1.600E+00
1.700E+00
1.800E+00
1.900E+00
2.000E+00
2.100E+00
2.200E+00
2.300E+00
2.400E+00
2.500E+00
-1.200E-02
-1.100E-02
-1.000E-02
-9.000E-03
-8.000E-03
-7.000E-03
-6.000E-03
-5.000E-03
-4.000E-03
-3.000E-03
-2.000E-03
-1.000E-03
0.000E+00
1.000E-03
2.000E-03
3.000E-03
4.000E-03
5.000E-03
6.000E-03
7.000E-03
8.000E-03
9.000E-03
1.000E-02
1.100E-02
1.200E-02
Iout (mA)
Vout(V)
out
outn
8. Data redazione: 2 marzo 2013 Pagina 8 di 21
6. TDR simulated analysis
The TDR simulated response shows the dynamic behaviors of the DUT. In particular it is possible to
evaluate the capacitive/inductive and transmission line effects of the model, including the value of the
impedance in steady-state conditions. The simulation is performed by sending a small voltage wave
(50mV on a 50 reference impedance) in the DUT and by sampling the reflected waves. The
amplitude of the signal must be very small, in order to not modify the operating point of the device.
This is very important for devices showing strong non-linearity (i.e. clamping diodes). The modeling
procedure started from three TDR configurations simulated with HSpice: differential mode, common
mode and single-ended mode (the last one is only for verification). The simulated set-up is reported in
figure.6.1.
Figure 6.1: Simulation schemes of TDR analysis
The differential mode analysis was the first analyzed. The Hspice behavior for the 400mV-swing driver
is reported in Fig.6.2. The unloaded TDR amplitude is 100mV only. The 2ns-long region in the middle
of the graph represents the 50 transmission line (Fig.6.1) behavior and must be assumed as 50
reference impedance for the graph interpretation.
The data has been post-processed in order to read the behavior directly in RHO1 (Fig.6.3)
1 Each signal has been post-processed with the following formula: VRHO=(Vsimulated – V50)*20 where
Vsimulated is the waveform of Fig.10, V50 is the voltage value of the 50 transmission line. 20 is the
scaling factor required to scale the TDR response between –1RHO and +1RHO (TDR simulated
amplitude is 100mV only)
9. Data redazione: 2 marzo 2013 Pagina 9 di 21
Fig.6.2: Differential TDR analysis response simulated with Hspice (400mV output swing driver,
unloaded TDR step=100mV
-1.000E+00
-9.000E-01
-8.000E-01
-7.000E-01
-6.000E-01
-5.000E-01
-4.000E-01
-3.000E-01
-2.000E-01
-1.000E-01
0.000E+00
1.000E-01
2.000E-01
3.000E-01
4.000E-01
5.000E-01
6.000E-01
7.000E-01
8.000E-01
9.000E-01
1.000E+00
1.100E-08
1.120E-08
1.140E-08
1.160E-08
1.180E-08
1.200E-08
1.220E-08
1.240E-08
1.260E-08
1.280E-08
1.300E-08
1.320E-08
1.340E-08
1.360E-08
1.380E-08
1.400E-08
1.420E-08
1.440E-08
1.460E-08
1.480E-08
1.500E-08
1.520E-08
1.540E-08
1.560E-08
1.580E-08
1.600E-08
time
RHO
Figure 6.3: Differential TDR analysis response simulated with Hspice (400mV
output swing driver) The ordinate scale is in RHO units The upper curve refers
to the output that stands at “0” logic level.
The Figure 6.3 shows a typical capacitive behavior. This effect has been simulated by means of a
differential capacitor placed between the two outputs. The initial value of the capacitor has been
estimated by calculating the RC constant time of the simulated response (T=Rtdr * C12 where
Rtdr=50). The value has been optimized by simulating the macromodel in the same configuration
and by comparing the results, using a “cut and try” procedure. The Hspice simulation shows that the
internal impedance of the output at “0” logic is not perfectly equal to the other one (58 and 46
9.000E -0 1
9.200E -0 1
9.400E -0 1
9.600E -0 1
9.800E -0 1
1.00 0E +0 0
1.02 0E +0 0
1.04 0E +0 0
1.06 0E +0 0
1.08 0E +0 0
1.10 0E +0 0
1.12 0E +0 0
1.14 0E +0 0
1.16 0E +0 0
1.18 0E +0 0
1.20 0E +0 0
1.22 0E +0 0
1.24 0E +0 0
1.26 0E +0 0
1.28 0E +0 0
1.30 0E +0 0
1.32 0E +0 0
1.34 0E +0 0
1.36 0E +0 0
1.38 0E +0 0
1.40 0E +0 0
1.42 0E +0 0
1.44 0E +0 0
1.46 0E +0 0
1.48 0E +0 0
1.50 0E +0 0
8.000E-09
8.200E-09
8.400E-09
8.600E-09
8.800E-09
9.000E-09
9.200E-09
9.400E-09
9.600E-09
9.800E-09
1.000E-08
1.020E-08
1.040E-08
1.060E-08
1.080E-08
1.100E-08
1.120E-08
1.140E-08
1.160E-08
1.180E-08
1.200E-08
1.220E-08
1.240E-08
1.260E-08
1.280E-08
1.300E-08
1.320E-08
1.340E-08
1.360E-08
1.380E-08
1.400E-08
1.420E-08
1.440E-08
1.460E-08
1.480E-08
1.500E-08
1.520E-08
1.540E-08
1.560E-08
1.580E-08
1.600E-08
10. Data redazione: 2 marzo 2013 Pagina 10 di 21
respectively). However, the two resistances have been assumed both equal to 50 in the THRIS
macromodel.
Figure 6.4: Differential TDR response of the macromodel simulated with Sprint. “Pure” capacitive
effect.
Fig. 6.5: Differential TDR response of the macromodel simulated with Sprint. S12
behavioral block has been included to model the long time constant.
Fig. 6.4 shows the macromodel response simulated with SPRINT. It is interesting to highlight the
different long time constant effect (Fig.6.3 and 6.4): the response in Fig.6.3 is not due to a “pure”
capacitive effect (well represented in Fig.6.4) but a sum of two time constants. This effect is not
negligible because it affects significantly the output waveform shapes (described later in the
document). Adding a behavioral block (element B13 in the netlist of Section 11) has optimized the
queue effect. It reproduces the long constant time. The final result is shown in Fig. 6.5.
11. Data redazione: 2 marzo 2013 Pagina 11 di 21
Figure.6.6: Common mode TDR analysis response simulated with Hspice (400mV output
swing driver). Ordinate scale is in RHO units. The upper curve refers to the output
that stands at “1” logic level.
The common mode TDR response (as resulting from the post-processing procedure already
described for the differential TDR) simulated with Hspice is reported in Fig.6.6.
It is interesting to note that the behavior of the two outputs is quite different. This is due to the
common mode feedback. While the “1” logic level behavior is quite similar to a capacitive effect, the
“0” logic level tries, at the beginning” to follow” an identical behavior, but after 200-400ps the common
mode reaction forces the output voltage to decrease.
The macromodel behavior simulated with Sprint is reported in Fig.6.7, where a unbalanced capacitor
has been added to each output of the device under test (2pf each), as well as a behavioral elements
(B10 and B30) to reproduce the long time constant effect. It is interesting to note that the bounce on the
output at “0” logic level is smoothed. In fact, in the macromodel the common mode feedback loop has
no artificial delay and it results too fast.
Two behavioral, smoothing-effect, elements introduced in the G_UP and G_DOWN current generators
(by means of a s(t)=… dynamic statement) increase the model accuracy. The final response of the
macromodel is reported in Fig.6.8.
12. Data redazione: 2 marzo 2013 Pagina 12 di 21
Fig.7.6: Common mode TDR analysis response of the macromodel simulated with SPRINT (400mV
output swing driver) . Queue effects are included but common mode feedback delay is too small
Fig.6.8: Same of Fig. 6.7 with a more-realistic common-mode feedback delay
The value of R (Fig.6.6 and Fig.6.8) is not perfectly matched:
Hspice micromodel SPRINT macromodel
Upper waveform (“1” logic) 117 109
Lower waveform (“0” logic) 17 33
In order to verify the model a third configuration has been simulated: a single-ended TDR stimulation
(Fig. 6.1). The TDR responses are shown in Fig.6.9 and Fig.6.10.
13. Data redazione: 2 marzo 2013 Pagina 13 di 21
Fig.6.9: Single-ended TDR analysis response simulated with Hspice (400mV output swing driver).
The ordinate scale is in RHO units. The upper curve refers to the output that stands at “1” logic level.
Fig.6.10: Single-ended TDR analysis response of the macromodel simulated with SPRINT (400mV
output swing driver) . The positive bounce is produced by the common mode feedback delay.
7. Output waveform
The last modeling phase is the output waveform. In order to maintain compatibility with THRIS
modeling architecture, the input stimulus has been represented by an ideal digital sequence (1 and 0
voltage levels). This stimulus controls the four switches that invert the current flow in the load resistors
R1 and R2. The switches implemented by means of voltage-controlled non-linear resistors shows a
resistance of 0 when closed and 1e6 when open. The two characteristics cross each other at 25
resistance. In any case the model has shown a low sensitivity versus this value.
-1.0000E+00
-9.0000E-01
-8.0000E-01
-7.0000E-01
-6.0000E-01
-5.0000E-01
-4.0000E-01
-3.0000E-01
-2.0000E-01
-1.0000E-01
0.0000E+00
1.0000E-01
2.0000E-01
3.0000E-01
4.0000E-01
5.0000E-01
6.0000E-01
7.0000E-01
8.0000E-01
9.0000E-01
1.0000E+00
1.1000E-08
1.1200E-08
1.1400E-08
1.1600E-08
1.1800E-08
1.2000E-08
1.2200E-08
1.2400E-08
1.2600E-08
1.2800E-08
1.3000E-08
1.3200E-08
1.3400E-08
1.3600E-08
1.3800E-08
1.4000E-08
1.4200E-08
1.4400E-08
1.4600E-08
1.4800E-08
1.5000E-08
1.5200E-08
1.5400E-08
1.5600E-08
1.5800E-08
1.6000E-08
1.6200E-08
1.6400E-08
1.6600E-08
1.6800E-08
1.7000E-08
time (s)
RHO
v2scal
v4scal
14. Data redazione: 2 marzo 2013 Pagina 14 di 21
Fig.7.1: Switch resistance versus voltage control
The transition velocity depends of the rise/fall time of the voltage controlling the switches2. In order to
make it independent from the rise/fall of the stimulus signal (user-dependent), a voltage-controlled
voltage source has been introduced (ESHAPE). It first detects the threshold crossing (placed at 0.5V)
and than switches completely in 300ps.
Fig.7.2 shows the unloaded output waveform for the 400mV output swing driver (micro-model)
simulated with Hspice. Convergence problems have limited the minimum resolution time to 200ps.
Fig.7.3 shows the same configuration simulated with SPRINT (macromodel). The queue effects are
introduced by the behavioral parameters B10 B30 B13 already optimized during the TDR model
validation.
Fig. 7.2: Unloaded output waveform for the driver with 400mV voltage swing simulated with Hspice.
2 In this particular application, the shape of the output signal (left unloaded) is mainly due to the G_UP
and G_DOWN currents charging the output capacitance. In any case it is necessary that the
switches are faster than their charging time.
8.00E-01
8.50E-01
9.00E-01
9.50E-01
1.00E+00
1.05E+00
1.10E+00
1.15E+00
1.20E+00
1.25E+00
1.30E+00
1.35E+00
1.40E+00
1.45E+00
1.50E+00
1.55E+00
1.60E+00
0.000000003
3.2E-09
3.4E-09
3.6E-09
3.8E-09
0.000000004
4.2E-09
4.4E-09
4.6E-09
4.8E-09
0.000000005
5.2E-09
5.4E-09
5.6E-09
5.8E-09
0.000000006
6.2E-09
6.4E-09
6.6E-09
6.8E-09
0.000000007
out
outn
15. Data redazione: 2 marzo 2013 Pagina 15 di 21
Fig. 7.3: Unloaded output waveform for the 400mV driver simulated
with SPRINT (macromodel)
The dynamic behavior of the 800mV driver is quite similar to the 400mV driver. The only difference
between 400mV driver and 800mV driver is represented by the static characteristic. For this reason,
the 800mV driver modeling procedure is not reported.
16. Data redazione: 2 marzo 2013 Pagina 16 di 21
8. Differential receiver VI characteristic
The receiver has a very simple topology, as described below:
Fig.8.1: Differential input architecture.
The static characteristic has been simulated with Hspice by injecting a variable current in one of the inputs
and by connecting the other pin to a fixed value (1.2V) The voltage reference signal required by the Spice
micromodel has been set to 1.2V too.
The simulation scheme is reported in Fig. 8.2.
Fig.8.2: Simulation scheme for VI analysis (differential receiver).
Fig.8.3: Static characteristic of the differential receiver simulated with Hspice with the
scheme reported in Fig.8.2:
green: complete V/I characteristic (simulated with Hspice);
red: 100ohm differential resistance characteristic;
blue: clamping diodes characteristics included in the SPRINT macromodel (green – red)
-1.000E-01
-9.000E-02
-8.000E-02
-7.000E-02
-6.000E-02
-5.000E-02
-4.000E-02
-3.000E-02
-2.000E-02
-1.000E-02
0.000E+00
1.000E-02
2.000E-02
3.000E-02
4.000E-02
5.000E-02
6.000E-02
7.000E-02
8.000E-02
9.000E-02
1.000E-01
-1.500E+00
-1.300E+00
-1.100E+00
-9.000E-01
-7.000E-01
-5.000E-01
-3.000E-01
-1.000E-01
1.000E-01
3.000E-01
5.000E-01
7.000E-01
9.000E-01
1.100E+00
1.300E+00
1.500E+00
1.700E+00
1.900E+00
2.100E+00
2.300E+00
2.500E+00
2.700E+00
2.900E+00
3.100E+00
3.300E+00
3.500E+00
3.700E+00
3.900E+00
input voltage (V)
inputcurrents(A)
total current
100ohm res.
diodes current
17. Data redazione: 2 marzo 2013 Pagina 17 di 21
In the SPRINT macromodel the measured waveform (Fig.8.3 – green curve) has been represented by
a sum of two characteristics, one due the termination resistor of 100 (red) and one due the “pure”
clamping diode effect (blue).
9. TDR characterization of the differential receiver
The receiver Spice model has been simulated in TDR configuration for both differential and common
mode configurations.
The simulation scheme is identical to the one used for the TDR characterization of the output cell
(Fig.6.1). Fig.9.1 shows the common mode response simulated with Hspice.
Fig.9.1 Common mode TDR response simulated with Hspice and the micromodel.
Fig. 9.2: Common mode TDR response simulated with SPRINT and the
macromodel. Tuning C1 and C2 values has optimized the waveform.
In similar way the differential capacitor value (Cdiff) has been optimized by means of the differential
TDR behavior.
In the following pages the model listings are reported.
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.150E-08
1.160E-08
1.170E-08
1.180E-08
1.190E-08
1.200E-08
1.210E-08
1.220E-08
1.230E-08
1.240E-08
1.250E-08
1.260E-08
1.270E-08
1.280E-08
1.290E-08
1.300E-08
1.310E-08
1.320E-08
1.330E-08
1.340E-08
1.350E-08
1.360E-08
1.370E-08
1.380E-08
1.390E-08
1.400E-08
1.410E-08
1.420E-08
1.430E-08
1.440E-08
1.450E-08
time (s)
RHO
V2 norm
V3 norm