DWS 8.5 USER MANUAL

Copyright 1985-2015 Piero Belforte , Giancarlo Guaschino
i
DWS
Digital Wave Simulator
R E L E A S E 8 . 5
USER'S MANUAL

ii
Copyright 1985 – 2015 Piero Belforte, Giancarlo Guaschino
This document contains proprietary information of Piero Belforte and Giancarlo
Guaschino, Torino, Italy.
DWS (Digital Wave Simulator) is a trademark of Piero Belforte and Giancarlo
Guaschino.
DWV (Digital Wave Viewer) is a trademark of Piero Belforte and Giancarlo
Guaschino.
SWAN (Simulation by Wave ANalysis) is a trademark of Piero Belforte.
All rights are reserved.
The contents of this document may not be copied or reproduced in any form
without the express prior permission of Piero Belforte and Giancarlo Guaschino.
Piero Belforte and Giancarlo Guaschino shall not be liable for errors contained
herein and the information contained in this document is subject to change
without notice.
The authors wish to thank their friend Flavio Maggioni for his important
contribution to the early edition of this manual.
Piero Belforte's info can be found at http://www.linkedin.com/in/pierobelforte
An up-to-date list of DWS related web publications is also available at this
link.
SWAN/DWS project story is available here: SWAN Story
An online version of DWS with a schematic capture is available both as Web and
mobile applications: Spicy SWAN.

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Table of Contents DWS
v
TABLE OF CONTENTS
TABLE OF CONTENTS ............................................................................................................V
CHAPTER 1. GENERAL FEATURES............................................................................... 1-1
1.1 INTRODUCTION ............................................................................................................. 1-2
1.2 GENERAL USE CONSIDERATIONS ................................................................................... 1-4
1.2.1 Time Step.............................................................................................................. 1-4
1.2.2 Elements............................................................................................................... 1-5
1.2.3 Two-Port Element Conversion .............................................................................. 1-7
1.2.4 Reference Impedance...........................................................................................1-10
1.2.5 Delay Discretization............................................................................................1-11
1.2.6 DWS Operation ...................................................................................................1-13
1.2.7 Memory Requirements.........................................................................................1-15
1.3 CIRCUIT DESCRIPTION..................................................................................................1-16
1.4 INPUT FORMAT ............................................................................................................1-17
1.5 OUTPUT FILE ...............................................................................................................1-18
1.6 REPORT FILE ...............................................................................................................1-21
1.7 STARTING DWS...........................................................................................................1-22
CHAPTER 2. PASSIVE ELEMENTS................................................................................. 2-1
2.1 LINEAR RESISTORS ....................................................................................................... 2-3
2.2 PIECE-WISE LINEAR RESISTORS .................................................................................... 2-4
2.3 TIME-CONTROLLED LINEAR RESISTORS......................................................................... 2-6
2.3.1 DC Resistor Function ........................................................................................... 2-9
2.3.2 Pulse Resistor Function .......................................................................................2-10
2.3.3 PulsePoly Resistor Function ...............................................................................2-11
2.3.4 PulseErfc Resistor Function.................................................................................2-12
2.3.5 Erfc Resistor Function.........................................................................................2-13
2.3.6 Delta Resistor Function .......................................................................................2-14
2.3.7 Sinusoidal Resistor Function................................................................................2-15
2.3.8 Piece-Wise Linear Resistor Function....................................................................2-16
2.3.9 PulsePwl Resistor Function .................................................................................2-17
2.3.10 File Resistor Function........................................................................................2-18
2.3.11 PulseFile Resistor Function ...............................................................................2-19

vi
2.4 VOLTAGE-CONTROLLED RESISTORS.............................................................................2-21
2.5 CURRENT-CONTROLLED RESISTORS .............................................................................2-25
2.6 STATIC TRANSFER FUNCTIONS FOR VOLTAGE OR CURRENT-CONTROLLED RESISTORS ...2-29
2.6.1 Linear Static Transfer Function ..........................................................................2-29
2.6.2 Piece-Wise Linear Static Transfer Function.........................................................2-30
2.6.3 File Static Transfer Function...............................................................................2-31
2.6.4 Threshold Static Transfer Function......................................................................2-32
2.6.5 Hysteresis Static Transfer Function .....................................................................2-33
2.7 DYNAMIC TRANSFER FUNCTIONS FOR VOLTAGE OR CURRENT-CONTROLLED RESISTORS2-34
2.7.1 Unit-step Dynamic Response ...............................................................................2-35
2.7.2 S-plane Dynamic Transfer Function.....................................................................2-38
2.7.3 Z-plane Dynamic Transfer Function ....................................................................2-40
2.8 LINEAR CAPACITORS ...................................................................................................2-42
2.9 LINEAR INDUCTORS .....................................................................................................2-44
2.10 COUPLED INDUCTORS ................................................................................................2-46
2.11 UNBALANCED TRANSMISSION LINES ..........................................................................2-48
2.12 BALANCED TRANSMISSION LINES...............................................................................2-50
2.13 UNIT-DELAY TRANSMISSION LINES............................................................................2-52
2.14 IDEAL TRANSFORMERS ..............................................................................................2-54
2.15 JUNCTION DIODES......................................................................................................2-56
CHAPTER 3. INDEPENDENT SOURCES .........................................................................3-1
3.1 INDEPENDENT VOLTAGE SOURCES (THEVENIN EQUIVALENT)..........................................3-3
3.2 INDEPENDENT CURRENT SOURCES (NORTON EQUIVALENT) ............................................3-4
3.3 INDEPENDENT SOURCE FUNCTIONS ................................................................................3-5
3.3.1 DC Source Function..............................................................................................3-5
3.3.2 Pulse Source Function...........................................................................................3-6
3.3.3 PulsePoly Source Function...................................................................................3-7
3.3.4 PulseErfc Source Function ....................................................................................3-9
3.3.5 Erfc Source Function...........................................................................................3-10
3.3.6 Delta Source Function.........................................................................................3-11
3.3.7 Sinusoidal Source Function .................................................................................3-12
3.3.8 Piece-Wise Linear Source Function .....................................................................3-13
3.3.9 PulsePwl Source Function...................................................................................3-14
3.3.10 File Source Function .........................................................................................3-15
3.3.11 PulseFile Source Function.................................................................................3-16
3.4 SOURCE FUNCTIONS WITH A PARAMETER CONTROLLED BY A NODE VOLTAGE...............3-18

vii
3.5 BINARY DIGIT SEQUENCE ............................................................................................3-19
3.5.1 Sequence Definition.............................................................................................3-20
3.5.2 Single Sequence...................................................................................................3-21
3.5.3 Periodic Sequence ...............................................................................................3-22
3.5.4 Burst Sequence....................................................................................................3-22
CHAPTER 4. CONTROLLED SOURCES......................................................................... 4-1
4.1 VOLTAGE-CONTROLLED VOLTAGE SOURCES................................................................. 4-3
4.2 VOLTAGE-CONTROLLED CURRENT SOURCES ................................................................. 4-5
4.3 CURRENT-CONTROLLED VOLTAGE SOURCES ................................................................. 4-7
4.4 CURRENT-CONTROLLED CURRENT SOURCES ................................................................. 4-9
4.5 MULTIPLYING VOLTAGE-CONTROLLED VOLTAGE SOURCES..........................................4-11
4.6MULTIPLYINGVOLTAGE-CONTROLLEDCURRENTSOURCES.............................................................4-13
4.7 STATIC TRANSFER FUNCTIONS .....................................................................................4-15
4.7.1 Linear Static Transfer Function ...........................................................................4-15
4.7.2 Piece-Wise Linear Static Transfer Function .........................................................4-16
4.7.3 File Static Transfer Function ...............................................................................4-17
4.7.4 Threshold Static Transfer Function......................................................................4-18
4.7.5 Hysteresis Static Transfer Function......................................................................4-19
4.8 DYNAMIC TRANSFER FUNCTIONS FOR VOLTAGE OR CURRENT-CONTROLLED SOURCES..4-20
4.8.1 Unit-step Dynamic Response................................................................................4-21
4.8.2 S-plane Dynamic Transfer Function.....................................................................4-24
4.8.3 Z-plane Dynamic Transfer Function.....................................................................4-26
CHAPTER 5. S-PARAMETER ELEMENTS..................................................................... 5-1
5.1 INTRODUCTION TO S-PARAMETER ELEMENTS ................................................................ 5-2
5.2 1-PORT ELEMENTS DEFINED BY S-PARAMETERS ............................................................ 5-4
5.6 S-PARAMETER DESCRIPTION ......................................................................................... 5-8
5.6.1 Piece-Wise Linear S-Parameter Description ......................................................... 5-8
5.6.2 File S-Parameter Description ..............................................................................5-10
CHAPTER 6. ADAPTORS.................................................................................................. 6-1
6.1 GENERAL FEATURES ..................................................................................................... 6-2
6.2 SERIES ADAPTORS ........................................................................................................ 6-3
6.3 BIMODAL ADAPTORS .................................................................................................... 6-5

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6.4 MULTIMODAL ADAPTORS ..............................................................................................6-7
CHAPTER 7. SUBCIRCUITS AND CHAINS.....................................................................7-1
7.1 GENERAL FEATURES......................................................................................................7-2
7.2 SUBCIRCUITS.................................................................................................................7-3
7.2.1 .SUBCKT Statement ..............................................................................................7-3
7.2.2 .ENDS Statement...................................................................................................7-4
7.2.3 Subcircuit Calls.....................................................................................................7-4
7.3 CHAINS OF CELLS ..........................................................................................................7-5
7.3.1 .CELL Statement....................................................................................................7-5
7.3.2 .ENDC Statement ..................................................................................................7-6
7.3.3 Cell Calls..............................................................................................................7-6
CHAPTER 8. CONTROL STATEMENTS..........................................................................8-8
8.1 .OPTIONS STATEMENT ................................................................................................8-9
8.2 .TRAN STATEMENT.....................................................................................................8-10

DWS General Features
Chapter 1 1-1
Chapter 1
G e n e r a l F e a t u r e s
1.
1.1 Introduction
1.2 General use considerations
1.2.1 Time step
1.2.2 Elements
1.2.3 Two-port element conversion
1.2.4 Reference impedance
1.2.5 Delay discretization
1.2.6 DWS operation
1.2.7 Memory requirements
1.3 Circuit description
1.4 Input format
1.5 Output file
1.6 Report file
1.7 Starting DWS

Chapter 1 1-2
1.1 Introduction
DWS (Digital Wave Simulator) is a revolutionary electrical circuit simulator
implemented with the aim of dealing with the needs of advanced electronic
design in a more effective way than traditional tools. Using advanced concepts
and unique powerful DSP (Digital Signal Processing) wave algorithms instead of
classical Nodal Analysis (NA), DWS can perform simulations not feasible using
NA tools. While traditional simulators are based on EQUATION SOLVERS,
DWS is based on WAVE PROCESSORS.
As known, NA-based simulation engines suffer of poor modeling capability of
signal propagation effects because Nodal Analysis assumes no signal
propagation within the electrical network under analysis. This last assumption is
no more valid for dealing with modern high-speed circuitry where signal
transition times are of the same order of magnitude or even lower than signal
propagation delays.
DWS was created by engineers for modeling and simulation of high-speed
circuits and systems: DWS: early applications. The use of wave variables and
scattering blocks (circuital elements and nodes) instead of classical voltages and
currents of NA, leads to an extremely accurate and fast digital model of the
electrical network under analysis :Application brochure (1989).
Very accurate and effective models of both active and passive electronic devices
can be directly obtained by means of time-domain experimental characterizations
with no need of knowledge of the internal structure of them (BTM: Behavioral
Time Modeling technique). Multiport time-domain S-parameter blocks can be
easily built up starting from actual TDR (Time Domain Reflectometer)
measurements using efficient PWL (PieceWise Linear) description of behaviors.
Due to STABILITY of DWS wave algorithms, there is no need of strict
CAUSALITY and PASSIVITY of S-parameter behaviors. In this way, very
accurate and stable models of lossy interconnections (2-port, 4-port) can be
easily built up: High-performance modeling & simulation.
PWL behaviors can be used to describe non-linear resistors, allowing the user to
simulate non-linear circuits that are not affordable with conventional NA
simulators. I/O macromodels of digital integrated circuits, as the IBIS standard
models, can be easily supported: SI/PI application course. Non-linear circuits
including CHAOTIC circuits and systems can be easily simulated by DWS

Chapter 1 1-3
without iterations and related convergence problems. Simulation throughput is in
the order of Megasamples/sec compared to Kilosamples/sec of NA simulators.
Very fast and accurate Transmission Line models open the way to very effective
Transmission Line Modeling (TLM) of actual devices including 2-D lossy signal
propagation effects. 2-D arrays of lossy Transmission Lines described by PWL
Scattering Parameters can be used to build up accurate and fast models of power
distribution planes: Modeling of power distribution planes.
Working at fixed time step, DWS is fully Nyquist criterion compliant, while NA
simulators are not. Wideband simulations are quickly feasible by using very
small time steps and FFT post-processing leads to accurate results in frequency
domain due to oversampling.
The user can monitor a complete set of variables at each node of the circuit
including Voltage, Current, Power, Incident and Reflected Waves etc. without
any addition of extra elements as required by NA simulators.
DWS algorithms are so fast and powerful that very complex networks with
hundred thousand elements can be dealt with in seconds or minutes even for
hundred thousand out samples. For this reason they have been utilized by major
electronic system manufacturers for fast and accurate POST-LAYOUT
simulations of complex Multiboard systems including 2-D models of Power
Distribution network and accurate 4-port IBIS models of active devices I/Os:
PRESTO.
For the above reasons, DWS can be considered something more than simply a
simulator: it is also a powerful modeling and simulation environment with a 4-
decade long application history to state-of-the-art circuits and systems.
DWS utilizes a SPICE-like syntax for network description. Powerful primitives
permit a very efficient description of network elements and stimulus signals.
PieceWise Linear (PWL) fittings and stored samples coming from previous
simulations or measurements can be used as behavioral descriptions. In the same
way the outputs coming from other analog simulators can be utilized to get
DWS-compatible behavioral models.
DWS and its companion graphical post-processor DWV (Digital Wave Viewer)
belongs to the SWAN modeling and simulation environment.
An online version of DWS with a schematic capture is available both as Web and
mobile applications: Spicy SWAN.

Chapter 1 1-4
1.2 General Use Considerations
Even if DWS use is very similar to SPICE, its internal operation is completely
different from the conventional analog simulators using Newton-Raphson
iterative loops and NA sparse-matrix techniques. DWS utilizes a brand-new
technique that converts the electrical network into a numerical equivalent
operating like a true DSP (Digital Signal Processor) [1]. This approach gives the
user several advantages including very high simulation speed, robustness
(iterative procedures and convergence problems are virtually avoided), and the
capability of simulating high complexity networks. DWS's performance
advantages are more and more evident as this complexity increases and will
further grow with the increase of computer's power.
To operate DWS correctly, a few issues have to be taken into account. These
issues will be briefly dealt with in the following.
1.2.1 Time Step
Being a DSP, DWS operation requires a fixed time step. This time step is defined
by the user in the .TRAN statement (see also Chapter 8), and its choice is very
important because it greatly affects both accuracy and simulation speed.
In any case, the Nyquist criterion has to be taken into account, so that the
simulation time step is strictly correlated with the bandwidth of the simulated
system and of its stimuli.
Another consideration affecting the time-step choice is related to the delays of
elements belonging to the simulated network. If no DELAYMETH option is
specified, all the delays are rounded to an integer multiple of time step, so that no
delay error occurs if each specified delay is an integer multiple of the chosen
step. When this situation is not verified, as in the case of small delay differences
between elements, due for instance to different mode propagation velocities in
coupled lines, it is suggested to use the DELAYMETH=INTERPOLATION
.option that operates some kind of interpolation in the delay evaluation, so that
the simulation error is reduced even if a very small time step isn't used.
Simulation error increases roughly with the square of the time step [2]. When in
doubt about the choice, it is suggested to run a reference simulation with a small
time step (e.g. 1/10 of the selected one) in order to compare the DWS's responses
with this reference and to have an evaluation of the simulation error.

Chapter 1 1-5
1.2.2 Elements
.
DWS's simulation engine maps each element and each node belonging to the
source netlist into a numerical equivalent which exchanges signals with the rest
of the network through its ports..
A port of an element is an internal DWS structure basically carrying the
following variables.:
A: port's incident voltage wave
B: port's reflected voltage wave
Z0: port's reference impedance
where the voltage is normally referenced to ground (node 0).
(0)
NA
B
V
I
Z0
A
B
wave representation
port N
electrical representation
Z0
Generic port N
electrical
network
digital
network
wave
At each element's port the following wave equations. apply:
V = A + B stating that the port voltage is the sum of the port's
incident and reflected voltage waves.
I = (A - B) / Z0 stating that the current entering the port is the
difference between the incident and reflected
voltage waves divided by the port's reference
impedance Z0.
The reference impedance of each port is determined by DWS during a setup
phase before the beginning of the real simulation run when the signals at each
port are calculated. If DWS cannot determine all the port reference impedances,

Chapter 1 1-6
proper warning message will be issued so that the user will be able to enter some
more information (like the element's reference impedance) or to introduce in the
netlist some decoupling elements like unit delays..
DWS can deal with elements having more than two ports. Element ports cannot
be left open. An external resistor of practically infinite resistance (e.g. 1E9) can
be connected between the open port and ground.
In order to maintain SPICE compatibility, an element's port is normally identified
in the source netlist by a node identifier (integer number). The reference node 0
(ground) of the port is specified only if it is necessary to have SPICE
compatibility or to avoid misunderstanding.
Examples:
R1PORT 1 0 1K
specifies a 1k one-port resistor. The port
identifier is 1 corresponding to node 1. Here
the ground node 0 is specified to have
SPICE syntax compatibility.
R2PORT 1 2 10K
specifies a 10k two-port resistor. The port identifiers
are 1 and 2 corresponding to node 1 and node 2
respectively. Here the ground node 0 is NOT
specified to have SPICE syntax compatibility.
AS3PORT 1 2 3
specifies a three-port element (series
adaptor). The port identifiers are 1, 2 and 3
corresponding to node 1, node 2 and node
3 respectively. Here the ground node 0 is
NOT specified because SPICE
compatibility is not required (SPICE
doesn't allow the use of this kind of adaptors).
1
PORT1 R1PORT
1
PORT1
R2PORT
PORT2
2
1
PORT1 PORT2
2
3
PORT3

Chapter 1 1-7
The two-port unbalanced transmission-line elements accept both SPICE-like
syntax where the node 0 is specified and the short syntax where it is not
specified. So:
T2PORT 1 2 Z0=50 TD=1NS (short DWS syntax)
or
T2PORT 1 0 2 0 Z0=50 TD=1NS (Spice-like syntax)
are the two ways allowed to describe the same transmission-line.
1
PORT1 PORT2
2
T2PORT
1.2.3 Two-Port Element Conversion
.
Before starting the simulation run, DWS converts some types of two-port
elements of the flattened netlist into one-port elements connected to the third port
of a series adaptor. This automatic conversion applies in particular for the
following two-port elements:
- Resistors (including nonlinear and controlled resistors)
- Capacitors
- Voltage sources (including controlled sources)
- Current sources (including controlled sources)
- Diodes
Moreover, DWS converts the balanced transmission lines of the flattened netlist
(four-port elements) into two-port transmission lines connected to the third port
of two series adaptors.
A similar conversion is applied to balanced ideal transformers.
For example, the two-port resistor of the source netlist:

Chapter 1 1-8
R2PORT 1 2 10K
will be converted in the two following elements:
AS.R2PORT 1 2 3
R2PORT 3 0 10K
1 2
3
R2PORT
1
R2PORT
2
In particular for two-port capacitors this is equivalent to use by default the so
called "stub model" [2] which in turn means to apply the trapezoidal method of
integration.
By default the two-port inductance is NOT converted in this way. Instead a so
called "link-model" is used to deal with inductances [2]. In this way DWS by
default processes a two-port inductance as a unit-delay transmission line with
impedance Z0=L/TSTEP where TSTEP is the simulation time step. If the user
prefers the stub model (trapezoidal integration method), he can define the two-
port inductance in the source netlist file as a series adaptor with a one-port
inductance connected to its third port. For example, if the user specifies the
following statement:
L2PORT 1 2 1NH
DWS deals with the inductance as a unit-delay transmission line of
impedance Z0=1E-9/TSTEP; if he specifies instead the following statements:
ASL 1 2 3
L1PORT 3 0 1NH

Chapter 1 1-9
DWS deals with the inductance using the trapezoidal method equivalent to a
shorted stub of Z0=2E-9/TSTEP and TD=TSTEP/2 connected between nodes 1
and 2.
1
L2PORT
2
1 2
"link" model
1 2
3
"stub" model
Z0=2L/TSTEP
TD=TSTEP/2
Z0=L/TSTEP
TD=TSTEP
default
trapezoidal
For the balanced transmission line, the automatic conversion is carried out for both its
balanced ports, as shown below:
TBAL 1 2 3 4 Z0=50 TD=1NS
1
2
3
4
is automatically converted in:
AS.TBAL 1 2 10
TBAL 10 0 20 0 Z0=50 TD=1NS
AS.TBAL 3 4 20
1
2
3
4
10 20
Ports 10 and 20 assume the meaning of balanced ports corresponding to the
couples of nodes 1,2 and 3,4 respectively.

Chapter 1 1-10
During the automatic two-port conversion, DWS also carries out a search for
parallel connections involving elements belonging to the types previously
mentioned. If two or more elements of these types are found to be connected in
parallel, this configuration will be automatically converted by means of a single
series adaptor, so that all the converted 1-port elements will be connected in
parallel at the third port of it.
Example:
R 1 2 100 R N 0 100
C 1 2 1NF AS.P.R 1 2 N
D 1 2 DMOD C N 0 1NF
D N 0 DMOD
1 2
1 2
R
C
D
N
R
C D
AS.P.R
The identifier of the series adaptor will be AS.P.elname (P means parallel) where
elname is the name of the element connected in the parallel block that first has
been descripted in the netlist.
1.2.4 Reference Impedance
.
As previously mentioned each element's port needs to have its reference
impedance defined by DWS before starting the simulation run. Some elements
like the piecewise-linear resistor or the diode require that the value of the
reference impedance are defined by the rest of the network connected to them. In
some cases, DWS is unable to determine Z0 due to a particular topology of the
network. This can happen, for instance, when two or more non-linear elements
are directly connected together. In this case DWS stops before starting the
simulation and issues a message identifying the problem and the location of the

Chapter 1 1-11
involved elements. At this point the user can define Z0 directly in the nonlinear
element's statement or add unit-delay transmission lines to cut the direct
connection causing the problem. In both cases an element is added to the original
network and its additional effect vanishes decreasing the time step. In general
this additional effect is lower if the impedance is defined within the element's
statement.
1.2.5 Delay Discretization
Several DWS elements include an intrinsic delay whose value can be specified
by means of parameter TD. To perform the simulation, the input value will be
discretized on the basis of the selected simulation time step (TSTEP). No delay
error due to discretization will occur if all specified parameters TD are integer
multiple of simulation TSTEP.
Two delay discretization strategies are allowed depending on the DELAYMETH
option set by the user on the DWS input file:
- ROUNDING: this is also the default method if no DELAYMETH is
specified. If TD >_ 0.5 TSTEP the actual simulation delay
DTD (Discretized Time Delay) will be the nearest integer
multiple of the simulation timestep TSTEP, so that a
maximum error of 0.5 TSTEP will be caused by the delay
discretization.
- INTERPOLATION: if TD >_ 0.5 TSTEP the output of the actual delay block
will be obtained as linear interpolation between the outputs
generated by the two delays multiple of the time step
within which the given TD is comprised. This second kind
of approximation leads generally to an error lower than
pure rounding error.
In case the input parameter TD is set to a value < TSTEP including 0, the actual
discretized value for simulation will be set to TSTEP for both strategies.

Chapter 1 1-12
Y
N
Input
TD, TSTEP
TD < 0.5 TSTEP
DELAYMETH
DTD = n TSTEP
so that
| TD - DTD | < 0.5 TSTEP
*
rounding
DTD = TSTEP
linear interpolation between
the outputs On and On
corresponding to the nearest
integer multiples of time step
+1
interpolation
*

Chapter 1 1-13
1.2.6 DWS Operation
Starting from the circuit description contained in the input file, DWS creates
sequentially three temporary files each generated from the previous one:
filename.t0: compressed netlist generated from the source netlist where each
statement is contained within a single line of text. The source lines
separated by the continuation character "+" at the beginning of the
line are joined together.
filename.t1: netlist after the subcircuit and chain expansion (flattened netlist).
filename.t2: netlist after the conversion of two-port elements into one-port
elements connected to a series adaptor. DWS simulates the circuit
as described in this temporary file. The report file is related to the
information carried by this netlist.
Syntax checks are performed at source netlist level. If a syntax violation is
detected, DWS stops and an error message containing the identifier of the
incorrect line is issued at the standard output, like:
Fatal Error : error message
On the basis of the network description contained in the flattened and converted
netlist (filename.t2), DWS builds up a node table where each node is classified
according to the number of connected element's ports.
If nodes connected to only one port (excluding control nodes) are detected, DWS
stops, and the following message will be issued at the standard output:
Fatal Error : floating node N in element elname
where N is the node with only one port and elname is the name of the element
connected to N. If floating control nodes of controlled elements are detected,
DWS stops, and the following message will be issued at the standard output:
Fatal Error : floating control node N
Upon the completion of node table and memory allocation procedure, DWS
starts a simulation scheduler which assigns the reference impedance to each

Chapter 1 1-14
element port. If some port impedance cannot be assigned due to a particular
topology of the network, the problem is located and the following error message
is issued at the standard output:
Fatal Error : network topology not allowed due to element elname
At this point, the user can add decoupling elements in the source netlist as
previously described (see section 1.2.4). In this way the user has a complete
information about the actual network he is going to simulate.
Upon completion of the scheduling process a message is issued at the standard
output and the true simulation run can begin.
After a digital network setup phase during which the calculation parameters of
elements and nodes are set, as well as the user's initial conditions (if so specified
by the UIC parameter in the .TRAN statement), the simulation loop starts.
Due to the outstanding robustness of DWS's algorithms, a simulation allowed to
start will reach its end without incurring in troubles like convergence or
numerical problems, that typically affect other products. These considerations
apply as well in the most complex simulations involving a very large number of
elements, that other analog simulators based on conventional algorithms can't
afford.
At the begin of the simulation run a CIRCUIT SIMULATION STARTED
message is issued at the standard output. A message will be also issued during
the simulation loop upon completion of one tenth of the simulation time window
(TSTOP/10). The CPU time required by DWS to complete each tenth of the time
window is strictly constant, so that the user can easily evaluate the amount of
time that will be required to complete the run. At each loop, corresponding to a
TSTEP increment of time, the digital network status is updated. The outputs
regarding the signals specified by the user in the .TRAN statement are stored
starting from TSTART and ending with TSTOP which also stops the simulation
loop.
At this point DWS outputs regarding the user selected waveforms are stored in
the file identified as filename.g. If the user has specified an output time step (by
means of the .TRAN parameter LIMPTS) not coincident with TSTEP, the
filename.g will store waveform samples obtained performing a linear
interpolation on the calculated samples.
Upon simulation run completion, the CPU time information including Specific
Elapsed Time (SET, see also 1.6) will be printed out on the standard output.

Chapter 1 1-15
1.2.7 Memory Requirements
The maximum allowed network complexity (see also 1.6) that DWS can process
in a single run is determined by the amount of RAM space available.
Because each element and node type has different memory allocation
requirement, the maximum allowed net complexity also depends on the particular
element mix and on net topology. For a typical mix, each thousand of elements
requires about 1Mbyte of RAM space, so that a 8 Gbyte RAM personal computer
can roughly process 8 Million element nets (considering the memory used by the
system).
[1] Piero Belforte, Giancarlo Guaschino: “Electrical Simulation using digital
wave networks”, IASTED International Symposium, Paris June 1985.
[2] P.B.Johns,M.O'Brien:"Use of the transmission-line modeling (TLM) method
to solve nonlinear lumped networks", Radio & Electronic Eng., 1980, Vol.50,
No.1/2, pp.59-70.

Chapter 1 1-16
1.3 Circuit Description
DWS circuit description philosophy is derived from the standard simulator
SPICE. SPICE statement compatibility has been held as far as possible. In the
situations not dealt with by SPICE, DWS syntax is conceived as a superset of
SPICE syntax. The circuit to be analyzed is described to DWS by a set of
element statements, which define the circuit topology and element values, and a
set of control statements, which define the conditions of the simulation and the
simulation results the user wishes saved. Comments are statements which begin
with an asterisk "*" in column 1. They are for user documentation purposes only
and are ignored during simulation. Simulation control statements begin with a
dot "." in column 1. The last statement must be a .END statement. The order of
the remaining statements is arbitrary. Each element in the circuit is specified by
an element statement that contains the element name, the circuit nodes (port
identifiers, see also 1.2.2) to which the element is connected, and the values of
the parameters that determine the electrical characteristics of the element. The
first letter of the element name specifies the element type. The format for the
DWS element types is given in what follows. The strings XXXXXXX and
YYYYYYY denote arbitrary alphanumeric strings. For example, a resistor name
must begin with the letter R and can contain one or more characters. Hence, R,
R1, RS, ROUT, and R1TERM are valid resistor names.
Data fields that are enclosed in less than and greater than signs "< >" are
optional. All indicated punctuation (parentheses, equal signs, etc.) must be
specified.
Nodes names (port identifiers) must be positive integer numbers. The datum
(ground) node must be named "0". Every node must have at least two ports
except for control nodes. As mentioned in 1.2.4, the situations in which the
program cannot find the proper value for the reference impedance of an element
port are pinpointed and warning message containing involved element is issued.
In this case the user can insert an additional element, usually a unit-delay
transmission line, or specify the impedance within the element's statement.
Hierarchical circuit descriptions are possible through the use of subcircuits (see
also .SUBCKT statement) that operate exactly in the same way of SPICE.
An additional automatic description capability is offered by DWS by means of
chains (see also .CHAIN statement) allowing the user to build up a cascade
connection of whatever number of basic circuit cells defined in the same input
text.

Chapter 1 1-17
1.4 Input Format
The input format for DWS is of the free format type. Fields in a statement are
separated by one or more blanks, a comma, an equal "=" sign, or a left or right
parenthesis; extra spaces are ignored. A statement may be continued by entering
a + (plus) in column 1 of the following line; DWS continues reading beginning
with column 2.
A name field must begin with a letter (A through Z) and cannot contain any
delimiters.
A number field may be an integer field (12, -44), a floating point field (3.14159),
either an integer or floating point number followed by an integer exponent (1E-
14, 2.65E3), or either an integer or a floating point number followed by one of
the following scale factors:
T=1E12 G=1E9 MEG=1E6 K=1E3
M=1E-3 U=1E-6 N=1E-9 P=1E-12 F=1E-15
Letters immediately following a number that are not scale factors are ignored,
and letters immediately following a scale factor are ignored. Hence, 10, 10V,
10VOLTS, and 10HZ all represent the same number, and M, MA, MSEC, and
MMHOS all represent the same scale factor. Note that 1000, 1000.0, 1000HZ,
1E3, 1.0E3, 1KHZ, and 1K all represent the same number.

Chapter 1 1-18
1.5 Output File
The DWS outputs are stored in the file filename.g which has the following
structure:
FILE_NAME
NUMBER_OF_WAVEFORMS
NUMBER_OF_SAMPLES_PER_WAVEFORM
SAMPLING_TIMESTEP
<START_TIME>
WAVEFORM_NAME #1
LIST_OF_SAMPLES
.
.
.
WAVEFORM_NAME #N
LIST_OF_SAMPLES
<COMMENTS>
where:
FILE_NAME is the name of the file containing the simulated waveform(s)
(filename.g).
NUMBER_OF_WAVEFORMS is the number of waveforms included in the
file specified by FILE_NAME. NUMBER_OF_WAVEFORMS is a nonzero
unsigned integer.
NUMBER_OF_SAMPLES is the number of samples of each waveform
included in the file specified by FILE_NAME. NUMBER_OF_SAMPLES is the
same for each waveform belonging to this file.
SAMPLING_TIMESTEP is the time between two contiguous samples of each
stored waveform expressed in seconds. The samples are stored at fixed time step.
SAMPLING_TIMESTEP applies to all the waveforms included in the file and
depends on the TSTEP and LIMPTS values specified within the .TRAN

Chapter 1 1-19
statement of DWS. If LIMPTS is greater than (TSTOP-TSTART)/TSTEP, the
number of stored samples per waveform is limited to (TSTOP-TSTART)/TSTEP
and SAMPLING_TIMESTEP is equal to TSTEP.
If LIMPTS is smaller than (TSTOP-TSTART)/TSTEP, the stored output samples
are obtained by linear interpolation of the simulated values and
SAMPLING_TIMESTEP is equal to (TSTOP-TSTART)/LIMPTS. If LIMPTS is
omitted, SAMPLING_TIMESTEP is equal to TSTEP.
Usually the time is assumed as independent variable and all the waveforms are
given versus time. When necessary, sampling time step can be used with the
meaning of sample identifier. In this last case one of the waveforms can be
assumed as independent variable.
START_TIME is the time expressed in seconds at which DWS begins to save
the results of the simulation and applies to all the waveforms included in the
same file. START_TIME corresponds to TSTART specified within the .TRAN
statement. If START_TIME is not specified, it is assumed to be 0.
WAVEFORM_NAME is the identifier of the waveform specifying the variable
type (voltage, current, etc.) and the node or port (element and node) identifier to
which the waveform is related. The following WAVEFORM_NAME types are
available:
V(N) : voltage at node (port) N referenced to ground (node 0)
V(N1,N2) : voltage at node (port) N1 referenced to node (port) N2
I(ELEM,N) : input current at port N of element ELEM
P(ELEM,N) : instantaneous input power at port N of element ELEM
A(ELEM,N) : incident voltage wave at port N of element ELEM
B(ELEM,N) : reflected voltage wave at port N of element ELEM
Y(ELEM,N) : reference admittance of port N of element ELEM
Z(ELEM,N) : reference impedance of port N of element ELEM
(Z=1/Y)
Q(ELEM,N) : incident instantaneous power at port N of element ELEM
R(ELEM,N) : reflected instantaneous power at port N of element
ELEM
G(ELEM,N) : B/A wave ratio at port N of element ELEM
where the node/element identifiers are those specified in .TRAN statement.

Chapter 1 1-20
LIST_OF_SAMPLE is the list of samples of the waveform specified by
WAVEFORM_NAME. Each sample is given in exponential notation.
The user can add COMMENT in the DWS's output file after the last list of
samples. Each comment line must have an asterisk "*" as first character of the
line.
The DWS's output file format can be also used to describe directly the behavior
of independent sources, the dynamic transfer function of controlled elements and
scattering-parameter elements.

Chapter 1 1-21
1.6 Report File
The report file obtained with the -r option of DWS command is a summary of the
most important features of the simulation including:
- SIMULATION PARAMETERS specified by the user including temperature,
simulation time step and time window.
- NETWORK ELEMENT SUMMARY which classifies the expanded network
derived from the DWS input netlist. For each element type the number of
elements contained in the flattened input netlist (filename.t2) is reported
giving also the total number of elements (En.) and the total number of nodes
(Nn.). The sum of En and Nn is assumed to be an index of the complexity of
the network.
- OUTPUT VARIABLE SUMMARY. that lists all output waveforms (node
voltages, branch currents, waves at the element's ports, instantaneous powers,
etc.) specified in the .TRAN statement and saved in the graphic output file
(filename.g). The number of stored samples per waveform is also specified.
- SIMULATION STATISTICS SUMMARY. giving some figures related to
the complexity. of the simulation to be carried out. This complexity is
evaluated by means of a Complexity Factor (Cf.) defined as the product of
Network Complexity and the number of Calculated Time-Points.
- JOB STATISTICS SUMMARY giving the actual CPU time required for the
simulation run and shared into user and system components. DWS's execution
time is roughly proportional to the Complexity Factor multiplied by the
Specific Elapsed Time (SET.). The SET is defined as the ratio between the
actual Elapsed Time and Cf. SET only depends on the mix of elements
contained in the network and on the computer's power so that simulation time
growth is strictly linear versus the complexity of the network.

Chapter 1 1-22
1.7 Starting DWS
.
Before starting, make sure to have a user-account set up to run DWS. To start
DWS, enter the command:
DWS [-rs] filename
where the options and the arguments have the following meaning:
filename: name of the file containing the source netlist (max allowed length:
100 characters).
-r (report):. information related to running simulation, including circuit
statistics (number and type of elements/nodes of the circuit) and
execution times, is saved in a report file filename.r
-s (silent)..: no output message about the running simulation is issued (useful
in batch mode).

Passive Elements DWS
Chapter 2 2-1
Chapter 2
P a s s i v e E l e m e n t s .
2. 2
2.1 Linear Resistors
2.2 Piece-Wise Linear Resistors
2.3 Time-Controlled Linear Resistors
2.3.1 DC Resistor Function
2.3.2 Pulse Resistor Function
2.3.3 PulsePoly Resistor Function
2.3.4 PulseErfc Resistor Function
2.3.5 Erfc Resistor Function
2.3.6 Delta Resistor Function
2.3.7 Sinusoidal Resistor Function
2.3.8 Piece-Wise Linear Resistor Function
2.3.9 PulsePwl Resistor Function
2.3.10 File Resistor Function
2.3.11 PulseFile Resistor Function
2.4 Voltage-Controlled Resistors

Chapter 2 2-2
2.5 Current-Controlled Resistors
2.6 Static Transfer Function for Voltage or Current Controlled Resistors
2.6.1 Linear Static Transfer Function
2.6.2 Piece-Wise Linear Static Transfer Function
2.6.3 File Static Transfer Function
2.6.4 Threshold Static Transfer Function
2.6.5 Hysteresis Static Transfer Function
2.7 Dynamic Transfer Function for Voltage or Current Controlled Resistors
2.7.1 Unit-step Dynamic Response
2.7.2 S-plane Dynamic Transfer Function
2.7.3 Z-plane Dynamic Transfer Function
2.8 Linear Capacitors
2.9 Linear Inductors
2.10 Unbalanced Transmission Lines
2.11 Balanced Transmission Lines
2.12 Unit-Delay Transmission Lines
2.13 Ideal Transformers
2.14 Junction Diodes

Chapter 2 2-3
2.1 Linear Resistors
.
N1 N2
General form:
RXXXXXXX N1 N2 value
Examples:
R1 1 0 1K
RS 15 22 50
N1 and N2 are the two element nodes. Value is the resistance (in ohms) and may be
positive (1/GMAX  value  1/GMIN) or negative (-1/GMIN  value  -
1/GMAX). If the parameter value is set to zero, the default value 1/GMAX will be
assumed (see the .OPTIONS statement).

Chapter 2 2-4
2.2 Piece-Wise Linear Resistors
..
N -N +
General form:
PXXXXXXX N+ N- V1 I1 V2 I2 <V3 I3 ... <V200 I200>>
PXXXXXXX N+ N- V1 I1 V2 I2 <V3 I3 ... <V200 I200>> Z0=value
PXXXXXXX N+ N- V1 I1 V2 I2 <V3 I3 ... <V200 I200>> C=value
PXXXXXXX N+ N- V1 I1 V2 I2 <V3 I3 ... <V200 I200>> L=value
Examples:
P1 1 0 -1 -.01 0 0 1 .1 Z0=50
PRDR 10 20 0 0 .6 6UA .8 .5MA .85 2.5MA .9 10MA
N+ and N- are the positive and negative element nodes, respectively. The
nonlinear resistance. is described by pairs of values Vi,Ii (Fig.2.2.1). The number
of pairs (n) must be 2 n 200. For V < V1 the resistance keeps the value related
to V1 < V < V2. For V > Vn the resistance keeps the value related to Vn-1 < V <
Vn. The pairs must be written in order of increasing voltage values (Vi  Vi+1).
V
I
1
2
3
4
(V
1
, I
1
)
(V
2
, I
2
)
(V
3
, I
3
)
(V
4
, I
4
)
N-N+I
V
Fig.2.2.1 Voltage-current relationship for a 2-port PWL resistor.
If the optional parameters Z0, C or L are not given, the reference impedance at
the N+ and N- ports will automatically be set by the circuit elements connected
to the Piece-Wise Linear Resistor. If, due to network topology, the port reference
impedance cannot be defined, one of the three optional parameters must be

Chapter 2 2-5
specified. In this way an additional transmission line with a delay of TSTEP/2,
connected at the intrinsic Piece-Wise Linear Resistor, decouples it from the other
elements of the network.
intrinsic
PWL resistor
TD=TSTEP/2
Z0
N+
N-
N+
N-
C
N+
N-
L/2
L/2
Fig.2.2.2: Electrical equivalents of two-port PWL resistor when additional
parameters Z0, C, L are specified for decoupling..
The characteristic impedance of this line may be expressed in one of three forms:
directly as impedance Z0 (ohms), as capacitance C (Farads), so Z0 is set to
TSTEP/(2*C), or as inductance L (Henries), so Z0 is set to 2*L/TSTEP. If the
Piece-Wise Linear Resistor is described as two-port element (i.e. neither N+ nor
N- is ground node), the additional line is a true or capacitive or inductive
balanced transmission line (Fig.2.2.2); if the Piece-Wise Linear Resistor is
described as one-port element (i.e. either N+ or N- is ground node), the
additional line is a true or capacitive or inductive unbalanced transmission line
(Fig.2.2.3).
An alternative method is to use a Unit-Delay Transmission Line for decoupling.
purposes, but in this case an additional line with a delay of TSTEP is introduced
in the network, leading to a transient effect greater than that due to the internal
Z0 setting.
N
N
N
TD
Z0
L
TSTEP
2
=
intrinsic
PWL resistor
C
Fig.2.2.3: Electrical equivalents of one-port PWL resistor when additional
parameters Z0, C, L are specified for decoupling.

Chapter 2 2-6
2.3 Time-Controlled Linear Resistors
.
N1 N2
t
General form:
RXXXXXXX N1 N2 rsource
RXXXXXXX N1 N2 rsource Z0=value
RXXXXXXX N1 N2 rsource C=value
RXXXXXXX N1 N2 rsource L=value
N1 and N2 are the two element nodes. rsource is the time-controlled resistor
function. Resistance value may be positive or negative, but not zero. If positive
resistance value becomes < 1/GMAX, the default value 1/GMAX will be
automatically set; if negative resistance value becomes > -1/GMAX, the
default value -1/GMAX will be automatically set (see the .OPTIONS statement).
Eleven control functions are available: DC, Pulse, PulsePoly, PulseErfc, Erfc,
Delta, Sinusoidal, Piece-Wise Linear, PulsePwl, File and PulseFile. The Pulse,
Piece-Wise Linear and Sinusoidal functions have the same syntax and meaning
of corresponding functions used in SPICE for time-dependent sources. The
PulsePoly, PulseErfc, PulsePwl, PulseFile functions are extensions of the Pulse
function where the behavior of pulse edges can be expressed in several ways
including polynomial, piece-wise linear and generic behaviors described in a
DWS output file.
If one of the three optional parameters Z0, C or L is specified, an additional
transmission line with a delay of TSTEP/2, connected at the intrinsic Time-
Controlled Linear Resistor, decouples it from the other elements of the network.
In this way, if delay-free circuit elements are connected to the Time-Controlled
Linear Resistor, the reference impedance at their ports doesn't have to be
calculated at each simulation step, speeding up the run time.

Chapter 2 2-7
intrinsic
TCL resistor
TD=TSTEP/2
Z0
N1
N2
N1
N2
C
N1
N2
L/2
L/2
Fig.2.3.1: Electrical equivalents of two-port TCL resistor when additional
Time-Controlled Linear Resistor is described as two-port element (i.e. neither N1
nor N2 is ground node), the additional line is a true or capacitive or inductive
balanced transmission line (Fig.2.3.1); if the Time-Controlled Linear Resistor is
described as one-port element (i.e. either N1 or N2 is ground node), the
(Fig.2.3.2).
Z0 setting.
N
N
N
TD
Z0
L
TSTEP
2
=
intrinsic
TCL resistor
C
Fig.2.3.2: Electrical equivalents of one-port TCL resistor when additional
User note:
Time-Controlled Linear Resistors can be utilized to implement time-dependent
switches. Their use doesn't cause any numerical problem to DWS if Time-
Controlled Linear Resistors are not connected to Delay-Free Loops (DFLs). This
connection could cause problems in particular situations, especially if the

Chapter 2 2-8
dynamic range of resistance values is very large. In these cases (automatically
identified by DWS) the user can decouple the Time-Controlled Linear Resistor
from DFL defining the reference impedance in the element's statement or cut the
DFL by means of additional Unit-Delay Transmission Lines inserted in the
network.

Chapter 2 2-9
2.3.1 DC Resistor Function
.
Syntax: DC <(>RDC<)>
RDC
t
Example:
RIN 4 0 DC( 50 )
The resistor value is time-invariant. The value may optionally be enclosed by
round brackets. The previous statement is completely equivalent to :
RIN 4 0 50

Chapter 2 2-10
2.3.2 Pulse Resistor Function
.
Syntax: PULSE( R1 R2 <TD <TR <TF <PW <PER>>>>> )
R1
R2
0
TD TR PW
PER
TF t
Example:
RIN 4 0 PULSE( 1E6 1E-6 5NS 1NS 1NS 24NS 50NS )
parameters default values units
R1 (initial value) ohms
R2 (pulsed value) ohms
TD (delay time) 0.0 seconds
TR (rise time) TSTEP seconds
TF (fall time) TSTEP seconds
PW (pulse width) TSTOP seconds
PER(period) TSTOP seconds
A single pulse so specified is described by the following breakpoint table:
time value
0 R1
TD R1
TD+TR R2
TD+TR+PW R2
TD+TR+PW+TF R1
TSTOP R1
Intermediate points are determined by linear interpolation.

Chapter 2 2-11
2.3.3 PulsePoly Resistor Function
.
Syntax: PULSE( R1 R2 <TD <TR <TF <PW <PER>>>>> )
POLY( C0 C1 C2 C3 C4 C5 C6 )
R1
R2
0
TD TR PW
PER
TF t
Example:
RIN 4 0 PULSE( 1E6 1E-6 5NS 1NS 1NS 24NS 50NS )
POLY( 0 .13 -.3.24 23.45 -36.62 21.17 -3.89 )
This function is an extension of the basic Pulse function, when rise and fall edge
behaviors are not linear but can be fitted by a higher-degree polynomial.
The meaning and the default values of PulsePoly parameters are like those of the
corresponding parameters of Pulse, unless edge shape is described by a 6-degree
polynomial in PulsePoly source. C0, C1, ... C6 are the coefficients of the
polynomial. The polynomial is defined between 0 and 1 and, at the lower and
upper limits of this range, must assume the values 0 and 1 respectively in order
that the actual edge shape will reflect the polynomial shape. The polynomial
definition window will be automatically scaled to the actual windows TR, R1, R2,
and TF, R2, R1 (fig.2.3.3.1).

BASIC POLY DEFINITION WINDOW
0
1
0
1
RISE-EDGE WINDOW
R1
R2
TR
FALL-EDGE WINDOW
R1
R2
TF
t
POLY(t) POLY(t)=
6
n=0
Cn tn
=1
n=0
6
Cn
Fig.2.3.3.1: Mapping of basic poly definition window into rise and fall windows.

Chapter 2 2-12
2.3.4 PulseErfc Resistor Function
.
Syntax: PULSE( R1 R2 <TD <TR <TF <PW <PER>>>>> ) ERFC
R1
R2
0
TD TR PW
PER
TF t
Example:
RIN 4 0 PULSE(1E6 1E-6 5NS 1NS 1NS 24NS 50NS ) ERFC
This function is an extension of the basic Pulse function when rise and fall edges
can be fitted by a complementary error function (erfc) behavior. The meaning
and the default values of PulseErfc parameters are like those of the
corresponding parameters of Pulse, unless edge shape is that of erfc. The
definition window of erfc will be automatically scaled to the rise and fall edge
windows (fig.2.3.4.1).
BASIC ERFC DEFINITION WINDOW
0
1
0
1
RISE-EDGE WINDOW
R1
R2
TR
FALL-EDGE WINDOW
R1
R2
TF
t
erfc
Fig.2.3.4.1: Mapping of basic erfc definition window into rise and fall windows.

Chapter 2 2-13
2.3.5 Erfc Resistor Function
.
Syntax: ERFC( R1 R2 TD TR )
R1
R2
0
TD TR t
Example:
RIN 4 0 ERFC(1E6 1E-6 5NS 1NS )
parameters units
R1 (initial value) ohms
R2 (final value) ohms
TD (delay time) seconds
TR (rise time) seconds
The shape of the waveform is described by the following table:
time value
0 to TD R1
TD+TR to TSTOP R2
from TD to TD+TR the edge shape is like the shape of erfc function.

Chapter 2 2-14
2.3.6 Delta Resistor Function
.
Syntax: DELTA( <R <TD>> )
R
0
TD t
Example:
RIN 4 0 DELTA( 1E6 5NS )
R (impulse value) 1 ohms
TD (delay time) 0.0 seconds
This function implements a delayed Dirac's pulse behavior in according to the
following table.
time value
0 to TD- 0
TD R
TD+ to TSTOP 0

Chapter 2 2-15
2.3.7 Sinusoidal Resistor Function
.
Syntax: SIN( RO RA <FREQ <TD <THETA>>> )
0
TD
R0
RA
1/ FREQ
THETA
t
Example:
RIN 4 0 SIN( 1E3 1E3 100MEG 5NS 10MEG )
RO (offset) ohms
RA (amplitude) ohms
FREQ (frequency) 1/TSTOP Hz
TD (delay) 0.0 seconds
THETA (damping factor) 0.0 1/seconds
This function implements an exponentially decaying sinusoidal behavior
described by the following table:
time value
0 to TD R0
TD to TSTOP RO + RA*exp(-(t-TD)*THETA)*sin(2*FREQ*(t-TD))
The syntax is derived from SPICE sinusoidal source.

Chapter 2 2-16
2.3.8 Piece-Wise Linear Resistor Function
.
Syntax: PWL( T1 R1 T2 R2 <T3 R3 <T4 R4 ... <T199 R199
<T200 R200>>>> )
0
tT1 T2 T3 T4 T5
R1
R2
R3
R4 R5
Example:
RIN 4 0 PWL( 10NS 1E6 11NS 1E-6 15NS 1E-6 16NS 1E6 )
This function implements a piece-wise linear behavior containing up to 200
breakpoints. Each breakpoint is defined by a pair of values (Ti, Ri) that specifies
the resistance Ri (in ohms) of the time-controlled resistor at time=Ti (in
seconds). The number of pairs (n) must be 2 n 200. The value of the
resistance at intermediate values of time is determined by using linear
interpolation on the input values. For time < T1 the value of the resistance is R1,
for time > Tn the value of the resistance is Rn. The pairs must be written in order
of increasing time values (Ti  Ti+1), otherwise a specific error message is
issued on the standard output.

Chapter 2 2-17
2.3.9 PulsePwl Resistor Function
.
Syntax: PULSE( R1 R2 <TD <TR <TF <PW <PER>>>>> ) PWL( T1 Y1
T2 Y2 <T3 Y3 <T4 Y4 ... <T199 Y199 <T200 Y200>>>> )
R1
R2
0
TD TR PW
PER
TF t
tT1 T2 T3 T4 T5 Tn
Y1
Y2 Y3
Y4
Y5
Yn
Example:
RIN 4 0 PULSE(1E6 1E-6 5NS 2NS 2NS 23NS 50NS ) PWL( 0 1E6
.3NS 1E3 .6NS 100 1NS 10 1.4NS 1E-2 2NS 1E-6 )
can be fitted by a piece-wise linear behavior. The meaning and the default values
of PulsePwl parameters are like those of the corresponding parameters of Pulse,
unless edge shape is described by the pairs of values Ti, Yi in PulsePwl resistor.
The pairs, written in order of increasing time values (Ti  Ti+1), determine edge
shape, while the actual value of the resistance is defined by the parameters R1,
R2, TR, TF. The PWL definition window will be automatically scaled to the
actual rise and fall edge windows. The piece-wise linear swing Yn - Y1 (n:
number of pairs) will become the pulse swing R2 - R1, the time interval Tn - T1
will become TR for the rise edge and TF for the fall edge as explained in
section 2.3.4.

Chapter 2 2-18
2.3.10 File Resistor Function
.
Syntax: FILE( filename )
R1R0
0 t
R2
R3
Rn
T 2T 3T nT
Example:
RIN 4 0 FILE(ressamples )
This function implements a time-controlled resistor whose behavior is described
by a DWS-format file identified by the parameter filename. In this file a
sampling timestep (T) will be specified. If the simulation timestep (TSTEP in
.TRAN statement) is not coincident with the file timestep, the resistance values
will be determined using linear interpolation of the values contained in the file.
After the last sample contained in the file, the resistance value is assumed to be
equal to the value of the last sample. File name must begin with a letter. Strings
beginning with 'DC' or 'dc' are invalid file names since these strings are
interpreted as the DC parameter of an independent source.

Chapter 2 2-19
2.3.11 PulseFile Resistor Function
.
Syntax: PULSE( NC NC <TD <NC <NC <PW <PER>>>>> )
FILE(filename)
0
TD PW
PER
t
t0
Y1
Y0
n*T
Yn
T 2T
Y2
Example:
RIN 4 0 PULSE( 0 0 5NS 0 0 23NS 50NS ) FILE(ressamples )
can be described by a behavior contained in a DWS-format file identified by the
parameter filename. File name must begin with a letter. Strings beginning with
'DC' or 'dc' are invalid file names.
The meaning and the default values of the parameters TD, PW and PER are like
those of the corresponding parameters of Pulse, whereas initial value, pulsed
value, rise time, fall time and edge shape are determined by resistance samples
versus time contained in the file. For this reason the initial, pulsed, rise time and
fall time values specified in the PULSE syntax will be not considered.
parameter value
R1 Y0 (1st file sample)
R2 Yn (last file sample)
TR n*T
TF n*T

Chapter 2 2-20
If the simulation timestep (TSTEP in .TRAN statement) is not coincident with
the file timestep, the resistance values will be determined using linear
interpolation of the values contained in the file.

Chapter 2 2-21
2.4 Voltage-Controlled Resistors
.
-
NC+
NC-
DELAY
D.T.F. S.T.F.
Dynamic
Transfer
Function
Static
Transfer
Function
Control Link Chain
VCR
N1
N2
General form
RXXXXXXX N1 N2 NC+ NC- STATIC-TRANSFER-FUNCTION
<DYNAMIC-TRANSFER-FUNCTION> <TD>
<DYNAMIC-TRANSFER-FUNCTION> <TD> Z0=value
<DYNAMIC-TRANSFER-FUNCTION> <TD> C=value
<DYNAMIC-TRANSFER-FUNCTION> <TD> L=value
-
NC+
NC-
DELAY
D.T.F.S.T.F.
Dynamic
Transfer
Function
Static
Transfer
Function
Control Link Chain
VCR
N1
N2
General form
RXXXXXXX N1 N2 NC+ NC- <DYNAMIC-TRANSFER-FUNCTION>
STATIC-TRANSFER-FUNCTION <TD>
STATIC-TRANSFER-FUNCTION <TD> Z0=value

Chapter 2 2-22
STATIC-TRANSFER-FUNCTION <TD> C=value
STATIC-TRANSFER-FUNCTION <TD> L=value
This form is an extension of the syntax used in SPICE for voltage-controlled
sources. N1 and N2 are the two element nodes. NC+ and NC- are the
positive and negative controlling nodes, respectively. The controlling signal is
V(NC+) - V(NC-). Like the other voltage and current controlled elements, the
Voltage-Controlled Resistors can have two types of control link chain with
different positions of the transfer functions. The static transfer function must be
specified, while the dynamic transfer function is optional.
The optional parameter TD is a delay time expressed in seconds. The Delay
operator is the first block of the control link chain and acts on the controlling
signal. The minimum delay is corresponding to TSTEP (specified in the .TRAN
statement) even if the input parameter TD is omitted or set to a value < TSTEP.
This approximation can be considered when zero-delay control links are
simulated. Regarding the delay discretization process, both ROUNDING and
INTERPOLATION methods described in 1.2.5 are allowed depending on the
DELAYMETH option set by the user on the DWS input file.
Resistance value may be positive or negative, but not zero. If positive resistance
value becomes < 1/GMAX, the default value 1/GMAX will be automatically set;
if negative resistance value becomes > -1/GMAX, the default value -1/GMAX
will be automatically set (see the .OPTIONS statement).
transmission line with a delay of TSTEP/2, connected at the intrinsic Voltage-
Controlled Resistor, decouples it from the other elements of the network. In this
way, if delay-free circuit elements are connected to the Voltage-Controlled
Resistor, the reference impedance at their ports doesn't have to be calculated at
each simulation step, speeding up the run time.

Chapter 2 2-23
N1
N2
L/2
L/2
intrinsic
VCR
TD=TSTEP/2
Z0
N1
N2
NC+
NC-
N1
N2
C
NC+
NC-
NC+
NC-
Fig.2.4.1: Electrical equivalents of two-port VCR when additional parameters
Z0, C, L are specified for decoupling.
Voltage-Controlled Resistor is described as two-port element (i.e. neither N1 nor
N2 is ground node), the additional line is a true or capacitive or inductive
balanced transmission line (Fig.2.4.1); if the Voltage-Controlled Resistor is
(Fig.2.4.2).
Z0 setting.
N
N
N
TD
Z0
L
TSTEP
2
=
intrinsic
VCR
C
NC+
NC-
NC+
NC-
NC+
NC-
Fig.2.4.2: Electrical equivalents of one-port VCR when additional
Use note:
the Voltage-Controlled Resistors (VCR) can be utilized to implement controlled
switches that in turn can model logic functionality. The use of VCR doesn't cause

Chapter 2 2-24
any numerical problem to DWS if VCRs are not connected to Delay-Free Loops
(DFLs). This connection could cause some solution problems in particular
situations especially if the dynamic range of resistance values is very large. In
these cases (automatically identified by DWS) the user can decouple the VCR
network.

Chapter 2 2-25
2.5 Current-Controlled Resistors
.
DELAY
D.T.F. S.T.F.
Dynamic
Transfer
Function
Static
Transfer
Function
Control Link Chain
CCR
N1
N2
N
I
ELEM
C
General form:
RXXXXXXX N1 N2 I(ELEM,NC) STATIC-TRANSFER-FUNCTION
<DYNAMIC-TRANSFER-FUNCTION> <TD>
<DYNAMIC-TRANSFER-FUNCTION> <TD> Z0=value
<DYNAMIC-TRANSFER-FUNCTION> <TD> C=value
<DYNAMIC-TRANSFER-FUNCTION> <TD> L=value
DELAY
D.T.F.S.T.F.
Dynamic
Transfer
Function
Static
Transfer
Function
Control Link Chain
CCR
N1
N2
N
I
ELEM
C
General form:
RXXXXXXX N1 N2 I(ELEM,NC) <DYNAMIC-TRANSFER-FUNCTION>
STATIC-TRANSFER-FUNCTION <TD>

Chapter 2 2-26
STATIC-TRANSFER-FUNCTION <TD> Z0=value
STATIC-TRANSFER-FUNCTION <TD> C=value
STATIC-TRANSFER-FUNCTION <TD> L=value
This form is an extension of the syntax used in SPICE for current-controlled
sources. N1 and N2 are the two element nodes. The controlling current
I(ELEM,NC) is the current which enters the port of the element ELEM connected
to the node NC. Like the other voltage and current elements, the Current-
Controlled Resistors can have two types of control link chain with different
positions of the transfer functions. The static transfer function must be specified,
while the dynamic transfer function is optional.
The optional parameter TD is a delay time expressed in seconds. The Delay
operator is the first block of the control link chain and acts on the controlling
signal. The minimum delay is corresponding to TSTEP (specified in the .TRAN
statement) even if the input parameter TD is omitted or set to a value < TSTEP.
This approximation can be considered when zero-delay control links are
simulated. Regarding the delay discretization process, both ROUNDING and
INTERPOLATION methods described in 1.2.5 are allowed depending on the
DELAYMETH option set by the user on the DWS input file.
Resistance value may be positive or negative, but not zero. If positive resistance
value becomes < 1/GMAX, the default value 1/GMAX will be automatically set;
if negative resistance value becomes > -1/GMAX, the default value -1/GMAX
will be automatically set (see the .OPTIONS statement).
transmission line with a delay of TSTEP/2, connected at the intrinsic Current-
Controlled Resistor, decouples it from the other elements of the network. In this
way, if delay-free circuit elements are connected to the Current-Controlled
Resistor, the reference impedance at their ports doesn't have to be calculated at
each simulation step, speeding up the run time.

Chapter 2 2-27
N1
N2
L/2
L/2
intrinsic
TD=TSTEP/2
Z0
N1
N2
N1
N2
C
I II
CCR
Fig.2.5.1: Electrical equivalents of two-port CCR when additional parameters
Z0, C, L are specified for decoupling.
Current-Controlled Resistor is described as two-port element (i.e. neither N1 nor
N2 is ground node), the additional line is a true or capacitive or inductive
balanced transmission line (Fig.2.5.1); if the Current-Controlled Resistor is
(Fig.2.5.2).
Z0 setting.
N
N
N
TD
Z0
L
TSTEP
2
=
intrinsic
C
I I I
CCR
Fig.2.5.2: Electrical equivalents of one-port CCR when additional
Use note:

Chapter 2 2-28
the Current-Controlled Resistors (CCR) can be utilized to implement controlled
switches that in turn can model logic functionality. The use of CCR doesn't cause
any numerical problem to DWS if CCRs are not connected to Delay-Free Loops
(DFLs). This connection could cause some solution problems in particular
situations especially if the dynamic range of resistance values is very large. In
these cases (automatically identified by DWS) the user can decouple the CCR
network.

Chapter 2 2-29
2.6 Static Transfer Functions for Voltage or Current-Controlled
Resistors
.
The input signal of static transfer function (controlling signal) is a voltage
(expressed in Volts) for Voltage-Controlled Resistors or a current (expressed
in Amps) for Current-Controlled Resistors. The output signal of static transfer
function is a resistance (expressed in ohms).
Five static transfer functions are available: Linear, Piece-Wise Linear, File,
Threshold and Hysteresis. If parameters are omitted, the default values shown
will be assumed.
2.6.1 Linear Static Transfer Function
.
Syntax: value
R
V (V) for VCR
I (A) for CCR

Examples:
R1 4 0 10 20 5
R1 4 0 I(R2,10) 5
value is the transfer ratio expressed in ohms/Volt (A-1) for VCR or ohms/Amp for
CCR.

Chapter 2 2-30
2.6.2 Piece-Wise Linear Static Transfer Function
.
Syntax: PWL( X1 R1 X2 R2 <X3 R3 <X4 R4 ... <X199 R199
<X200 R200>>>> )
X1 X2
X3 X4 X5
R1
R2
R3 R4
R5

V (V) for VCR
I (A) for CCR
R
Examples:
RV1 4 0 10 20 PWL( -1 10 0 10 0 100 1 100 )
RI2 4 0 I(R2,10) PWL( -10MA 10 0 10 0 100 10MA 100 )
This function implements a PieceWise Linear (PWL) behavior containing up to
200 breakpoints. Each breakpoint is defined by a pair of values (Vi,Ri) for VCR
and (Ii,Ri) for CCR. Each pair of values (Xi, Ri) specifies that resistance value is
Ri (in ohms) at controlling signal = Xi. The number of pairs (n) must be
2n200. Resistance value at intermediate values of controlling signal is
determined by using linear interpolation on the input values.
For controlling signal < X1 the static transfer function keeps the slope related to
the first interval X1 X2, for controlling signal > Xn the static transfer function
keeps the slope related to the last interval Xn-1 Xn. The pairs must be written in
order of increasing controlling signal values (Xi  Xi+1) otherwise an error
message is issued.

Chapter 2 2-31
2.6.3 File Static Transfer Function
.
Syntax: FILE( filename )
R1
R0
0
R2
R3
Rn
X 2X 3X nX

V (V) for VCR
I (A) for CCR
R
Examples:
RV1 4 0 10 20 FILE( stfsamples )
RI2 4 0 I(R2,10) FILE( stfsamples )
This function implements a static transfer behavior described by a DWS-format
file identified by the parameter filename. In this file the sampling timestep value
is assumed to be the independent variable step (V for VCR and I for CCR).
Resistance value at intermediate values of controlling signal is determined by
using linear interpolation.
For controlling signal < controlling signal of the first sample the static transfer
function keeps the slope related to the interval between the first two samples, for
controlling signal > controlling signal of the last sample the static transfer
function keeps the slope related to the interval between the last two samples.
File name must begin with a letter. Strings beginning with 'DC' or 'dc' are invalid
file names since these strings are interpreted as the DC parameter of an
independent source.

Chapter 2 2-32
2.6.4 Threshold Static Transfer Function
.
Syntax:THR( <XT <R1 <R2>>> )
R2
V (V) for VCR
I (A) for CCR

R1
XT
R
Examples:
RV1 4 0 10 20 THR( 1 1E-6 1E9 ) 1NS
RI2 4 0 I(R2,10) THR( 10MA 1E-6 1E-9 ) 1NS
This function implements a static transfer behavior described by an ideal
threshold. For controlling signal < XT the resistance assumes the value R1, while
for controlling signal > XT the resistance assumes the value R2. For controlling
signal = XT the resistance assumes the value R2.
The default values of the parameters are the following:
XT (threshold) 0.0 Volts or Amps
R1 (resistance) 1/GMAX ohms
R2 (resistance) 1/GMIN ohms

Chapter 2 2-33
2.6.5 Hysteresis Static Transfer Function
.
Syntax: HYST( <XT1 XT2 <R1 <R2>>> )
R2
V (V) for VCR
I (A) for CCR

R1
XT2XT1
R
Examples:
RV1 4 0 10 20 HYST( 0 1 1E-6 1E9 ) 1NS
RI2 4 0 I(R2,10) HYST( 0 10MA 1E-6 1E9 ) 1NS
This function implements a static transfer behavior described by an ideal
hysteresis cycle. For controlling signal < XT1 the resistance assumes the value
R1, while for controlling signal > XT2 the resistance assumes the value R2. In
the interval XT1 XT2 the resistance assumes the value R1 if the controlling signal
is increasing from values < XT1 to values > XT1, while the resistance assumes
the value R2 if the controlling signal is decreasing from values > XT2 to values <
XT2.
The default values of the parameters are the following:
XT1 (threshold) 0.0 Volts or Amps
XT2 (threshold) 0.0 Volts or Amps
R1 (resistance) 1/GMAX ohms
R2 (resistance) 1/GMIN ohms

Chapter 2 2-34
2.7 Dynamic Transfer Functions for Voltage or Current-Controlled
Resistors
.
The dynamic transfer function is a linear, time-invariant transformation that can
be performed in the control link chain after the delay operator and before the
static function. Its behavior can be described in three different ways:
- In time-domain by means of its unit-step response s(t). This can implement the
so called BTM (Behavioral Time Modeling) technique to obtain models directly
in time-domain.
- In the s-plane by means of its transfer response H(s) defined with poles and
zeros in the complex frequency domain (s-plane).
- In the z-plane by means of its transfer response H(z) defined with poles and
zeros in the digital complex frequency domain (z-plane).
DWS transforms any of these description forms into discretized time transfer
functions with a time step corresponding to that chosen by the user for the
simulation (TSTEP).

Chapter 2 2-35
2.7.1 Unit-step Dynamic Response
.
The time-domain unit-step response can be described in the two DWS standard
ways: Piece-Wise Linear or File.
- Piece-Wise Linear
Syntax: s(t) = PWL( X1 Y1 X2 Y2 <X3 Y3 <X4 Y4 ...
<X199 Y199 <X200 Y200>>>> )
X1 X2 X3 X4 X5
Y1
Y2
Y3
Y4 Y5
t
s(t)
Y6
X6
Examples:
REX 4 0 10 20 1 s(t)=PWL( 0 .25 1US .5 3US 1 )
REY 4 0 I(R2,10) THR( 10MA ) s(t)=PWL( 0 .25 1US .5 3US 1 )
In this case the behavior of unit-step response s(t) is given by a PieceWise Linear
behavior containing up to 200 breakpoints. The pairs of values XiYi are the
breakpoint coordinates. Each pair specifies that the value of s(t) is Yi at time = Xi
expressed in seconds. The number of pairs (n) must be 2n200. The value of
s(t) at intermediate time values is determined by using linear interpolation on the
input values.
For time < X1 it is assumed that s(t)=0. For time > Xn it is assumed that s(t)=Yn.
The pairs must be written in order of increasing time values (Xi < Xi+1).
Use note:
As far as possible it is recommended to perform the BTM (Behavioral Time
Modeling) using the PWL fitting of dynamic behaviors because it is the fastest
approach in terms of simulation time. Simulation time is directly proportional to
the number of breakpoints n and inversely proportional to the simulation time

Chapter 2 2-36
step TSTEP. A further advantage (about a factor 2) in simulation speed can be
achieved if the values of time coordinates Xi are chosen as integer multiples of
TSTEP.
- File
Syntax: s(t) = FILE( filename )
t
s(t)
Extracted
pure
delay
T
TSTEP
file samples
sampled values
Examples:
REY 4 0 10 20 1 s(t) = FILE( srsamples )
REX 4 0 I(R2,10) 1 s(t) = FILE( srsamples )
In this case the behavior of unit-step response is given by its n samples s(kT),
0kn-1, at fixed step (T) contained in the DWS-format file identified by the
parameter filename. File name must begin with a letter. Strings beginning with
'DC' or 'dc' are invalid file names since these strings are interpreted as the DC
parameter of an independent source.
The value of s(t) after the last sample contained in the file is assumed to hold the
value of the last sample. During the simulation loop, DWS performs a time-
convolution process involving coefficients obtained sampling the file contents at
simulation time step (TSTEP). If TSTEP is not coincident with the file time step
T, these coefficients will be calculated by means of linear interpolation between
file samples.
User note:

Chapter 2 2-37
The file representation of dynamic behavior is the most direct and accurate way
to perform BTM, because DWS outputs coming from simulation or time-domain
measure can be utilized without processing. Nevertheless its use can become
more time-consuming than PWL due to time-convolution, that causes a quadratic
growth of simulation time versus the inverse of simulation time step (1/TSTEP).
Therefore, whenever possible, it is advisable to choose piece-wise-linear step
response descriptions, which guarantee linear growth of simulation time versus
sampling frequency.
In case the file description is utilized for accuracy reasons despite its computing
requirement, it is suggested to extract the possible pure delay component of s(t)
and place it into the delay operator provided in the control link chain, in order to
limit the number of convolution coefficients as far as possible.

Chapter 2 2-38
2.7.2 S-plane Dynamic Transfer Function
..
Syntax: H(s) = ZEROS( Rez1 Imz1 ... Rezm Imzm ) POLES( Rep1 Imp1 ...
Repn Impn ) H0=value
Examples:
REHS 4 0 10 20 1 H(s) = ZEROS( 0 1 ) POLES( -50K 0 -1K 25MEG )
H0=5
REHS 4 0 I(R2,10) 1 H(s) = ZEROS( 0 1 ) POLES( -50K 0
-1K 25MEG ) H0=5
The behavior of the dynamic response is described in the complex frequency
plane (s) through its pole/zero representation expressed in the following general
form:
H(s) = K
(s-s ) ... (s-s )(s-s )(s-s ) ... (s-s )(s-s )
(s-s ) ... (s-s )(s-s )(s-s ) ... (s-s )(s-s )
z1 zr z,r+1 z,r+1
*
zm zm
*
p1 pq p,q+1 p,q+1*
pn pn
*
where:
szi = Rezi is the generic real zero,
szi = Rezi + jImzi and szi* = Rezi - jImzi are the generic couple of complex
conjugate zeros,
spi = Repi is the generic real pole,
spi = Repi + jImpi and spi* = Repi - jImpi are the generic couple of complex
conjugate poles
j

Re ,Im
Re ,-Im
Re ,Im
Re ,-Im
Re ,0
Re ,0
pi
zi
pi
pi
pi pi
zi zi
zi zi
real zero
real pole
complex conjugate zeros
complex conjugate poles

Chapter 2 2-39
The zeros (poles) in the s-plane are defined by a maximum of 10 pairs of values.
No particular ordering of these values is required. Every pair (Rei,Imi) represents
either a real root (in which case Imi=0 and Rei is the root value expressed in
1/second) or a pair of complex roots Rei+jImi, Rei-jImi (Rei expressed in
1/second and Imi expressed in radians/second).
For stable systems all poles must lie in the left half-plane ( < 0) so that Repi < 0.
H0 is the steady state value of the dynamic transfer function. More precisely, if k
is the number of zeros in the origin, H(s)=H'(s)*sk with H'(0) not null neither
infinite, then:
= H'(0) = K
(-s ) ...(-s )|-s | ... |-s |
(-s ) ...(-s )|-s | ... |-s |
z1 z,r+1-k z,m-k
p1 pq p,q+1 pn
z,r-k
2
2 2
2
H0
As any H(s) transfer function is subject to a bilinear transformation with
sampling period T equal to the time step chosen for simulation TSTEP, the
frequency response of the filter actually simulated by DWS is a warped version
of that described by H(s), according to the nonlinear frequency transformation
 = 2/T * tan(T/2)
where  is the frequency (in radians/second) of the actually simulated filter and
 is the corresponding frequency of the filter with H(s) response. This nonlinear
relationship is to be taken into account whenever an H(s) description is used.
When working with small simulation time step (TSTEP), some well known
numerical troubles can arise due to rounding errors of signals and coefficients.
Before starting the simulation, DWS automatically evaluates this possibility and,
if potential troubles are detected, a specific warning message will be issued at
standard output.

Chapter 2 2-40
2.7.3 Z-plane Dynamic Transfer Function
..
Syntax: H(z) = ZEROS( Rez1 Imz1 ... Rezm Imzm ) POLES( Rep1 Imp1 ...
Repn Impn ) H0=value T=value
Examples:
REHZ 4 0 10 20 1 H(z) = ZEROS( 0 1 ) POLES( 50M 0 ) H0=5
T=1US
REHZ 4 0 I(R2,10) 1 H(z) = ZEROS( 0 1 ) POLES( 50M 0 ) H0=5
T=1US
The behavior of the dynamic response is described in the digital complex plane z
through its pole/zero representation expressed in the general form:
H(z) = K
(z-z ) ... (z-z )(z-z )(z-z ) ... (z-z )(z-z )
(z-z ) ... (z-z )(z-z )(z-z ) ... (z-z )(z-z )
z1 zr z,r+1 z,r+1
*
zm zm
*
p1 pq p,q+1 p,q+1
*
pn pn
*
where:
zzi = Rezi is the generic real zero,
zzi = Rezi + jImzi and zzi* = Rezi - jImzi are the generic couple of complex
conjugate zeros,
zpi = Repi is the generic real pole,
zpi = Repi + jImpi and zpi* = Repi - jImpi are the generic couple of complex
conjugate poles
Re ,0zi
Re ,-Impi pi
Re ,0pi
Re ,Impi pi
Re ,Imzi zi
Re ,-Imzi zi
real zero real pole
complex conjugate
complex conjugate
zeros
poles
z = -1
( = )
z = 1
 ( = 0 )
Im[z]
Re[z]

Chapter 2 2-41
The zeros (poles) in the z-plane are defined by a maximum of 10 pairs of values.
No particular ordering of these values is required. Every pair (Rei,Imi) represents
either a real root (in which case Imi=0 and Rei is the root value) or a pair of
complex roots Rei+jImi, Rei-jImi.
For stable systems all zeros and poles must lie within the unit circle.
H0 is the zero frequency value (z=1) of the dynamic transfer function. More
precisely, if k is the number of zeros for z=1, H(z)=H'(z)*(z-1)k with H'(1) not
null neither infinite, then H0=H'(1).
T is the sampling period (in seconds) that has been used to time discretize the
dynamic transfer function.

Chapter 2 2-42
2.8 Linear Capacitors
.
N -N +
V0
General form:
CXXXXXXX N+ N- value <IC=V0>
Examples:
C10 10 0 1NF
COSC 15 32 100P IC=2V
N+ and N- are the positive and negative element nodes, respectively. Value is the
capacitance in Farads.
The optional initial condition.. is the initial (time-zero) value of capacitor voltage
V0 (in Volts). Note that the initial conditions (if any) apply 'only' if the UIC
option. is specified on the .TRAN statement.
Note:
As already mentioned in 1.2.3, the default integration method for linear capacitor
is trapezoidal corresponding to the open stub model. Each one-port grounded
capacitor is dealt with as a "short" open stub:
stub model
C
N
Z0 =
TSTEP
2C
TD = TSTEP
2
N
Stub model of one-port grounded capacitor.

Chapter 2 2-43
In case of two-port capacitor, the automatic conversion (see 1.2.3) will apply
before the simulation loop.
Cxxx
Z0 =
TSTEP
2C
TD = TSTEP
2
N+ N-
Cxxx
AS.Cxxx
N+ N- AS.Cxxx
N+ N-
For grounded capacitors, a "link" transmission line model can be specified using
the unit-delay line equivalent (see also 2.12):
Z0 =
TSTEP
C
TD = TSTEP
TxxxVo
N+ N-Io N+ N-
unit-delay line
with the following syntax:
TXXXXXXX N+ N- C=value <IC=V0,I0>
This form can be used instead of normal SPICE-like form when decoupling
between ports N+ and N- is required.

Chapter 2 2-44
2.9 Linear Inductors
.
N -N +
I0
General form:
LXXXXXXX N+ N- value <IC=I0>
Examples:
L1 24 0 10NH
LOSC 32 65 1U IC=22.3MA
N+ and N- are the positive and negative element nodes, respectively. Value is the
inductance in Henries.
The optional initial condition is the initial (time-zero) value of inductor current I0
(in Amps) that flows from N+, through the inductor, to N-. Note that the initial
conditions.. (if any) apply 'only' if the UIC option. is specified on the .TRAN
statement.
Note:
The default integration method for one-port grounded inductor is trapezoidal,
corresponding to the shorted stub model. Each one-port grounded inductor is
dealt with as "short" shorted stub.
stub model
L
N
Z0 = TSTEP
2L
TD = TSTEP
2
N
Io Io
Stub model of one-port grounded inductor.

Chapter 2 2-45
As already mentioned in 1.2.3, the default integration method for two-port linear
inductor corresponds to the "link" transmission-line model.
This assures decoupling between ports N+ and N-.
Z0 = TSTEP
L
TD = TSTEP
Lxxx
N+ N-
Io
N+ N-
unit-delay line
Link transmission-line model of two-port inductor.
If a trapezoidal integration method is preferred, it is necessary to use the
following equivalent:
Lxxx
Z0 =
TSTEP
2L
TD = TSTEP
2
N+ N-
Lxxx
ASL
N+ N- ASLN+ N-
Io
Io Io
NS
ASL N+ N- NS
LXXX NS 0 value <IC=I0>

Chapter 2 2-46
2.10 Coupled Inductors
General form:
KXXXXXXX LYYYYYYY LZZZZZZZ value
Examples:
K43 LAA LBB 0.12345
KXFRMR L1 L2 0.87
LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and
value is the coupling coefficient, K, which must be greater than 0 and less than 1.
Using the 'dot' convention, place a 'dot' on the first node of each inductor.
Note that all the coupled inductors must have different names.
DWS groups together the coupled inductors and then converts each group into an
equivalent model.
Example
Two inductors LYYY and LZZZ, coupled by a coefficient of value value, will be
converted in the following elements:

Chapter 2 2-47
L ngroup
LYYY LZZZ M
LZZZ M
L ngroup
LYYY LZZZ M
LYYY M
L ngroup
LYYY LZZZ M
M
M value LYYY LZZZ
_ _
_ _
_ _ _
1
2
1 2
2
2
2

 


 


 
 
where ngroup identifies the group.
Note:
If a large number of coupled inductors is present, simulation results could be
unstable. In this case, if the circuit implements an actual configuration, the
simulation convergence could be reached by reducing the simulation time step.

Chapter 2 2-48
2.11 Unbalanced Transmission Lines
.
N+ N-
I
0
V0
Z T0 D
General form:
TXXXXXXX N+ N- Z0=value TD=value <IC=V0,I0>
TXXXXXXX N+ 0 N- 0 Z0=value TD=value <IC=V0,I0>
Examples:
T1 1 2 Z0=50 TD=10NS
TUNB 10 0 20 0 Z0=100 TD=1NS
This element statement defines a lossless unbalanced transmission line connected
between ports N+ and N-. Its syntax is SPICE compatible if the ground node 0 is
specified at both ports. A shorter DWS-syntax where ground node 0 is omitted at
both ports is also available.
Z0 is the characteristic impedance (ohms). The electrical length of the line is
expressed in the form of transmission delay time TD (s). The parameter TD will
be dealt with in two different modes according to the DELAYMETH option
statement, as shown in 1.2.5. If the parameter TD is set to a value < TSTEP, the
discretized delay will assume the value TSTEP. As default, the line delay will be
rounded to the integer multiple of TSTEP closest to TD. This element models
only one unbalanced propagation mode.
The optional initial condition specification consists of the initial (time-zero)
values of the voltage V0 (in Volts) at the transmission line ports and of the
current I0 (in Amps) that flows from N+, through the transmission line, to N-.

Chapter 2 2-49
The initial conditions (if any) apply 'only' if the UIC option is specified on the
.TRAN statement.
Unbalanced transmission line ports cannot be directly connected to ground by
specifying 0 as a port identifier: an external one-port linear resistor whose
conductance is Gmax must be used to short the grounded port. As specified for
all DWS element ports, a transmission line port cannot be left open. A resistor of
conductance Gmin must be used to terminate the open port.
Examples:
shorted line:
network
10 20
TSHORTED 10 20 Z0=50 TD=1NS
RSHORT 20 0 0
open line:
network
10 20
TOPEN 10 20 Z0=50 TD=1NS
ROPEN 20 0 1E9

Chapter 2 2-50
2.12 Balanced Transmission Lines
.
N1
N2
N3
N4
Z TD0V
I0
0
I0
General form:
TXXXXXXX N1 N2 N3 N4 Z0=value TD=value <IC=V0,I0>
Example:
TBAL 1 2 3 4 Z0=100 TD=1NS
This element statement defines a 4-port lossless transmission line carrying only
one propagating mode (balanced mode) between balanced ports formed by the
pairs N1, N2 and N3, N4. If both N2 and N4 are defined as ground (0) node, this
element becomes an unbalanced transmission line propagating only one
unbalanced mode (see 2.10). Z0 is the balanced characteristic impedance.
(ohms). The electrical length of the line is expressed in the form of transmission
delay time.. TD (s).
As already pointed out at 1.2.3, balanced ports are automatically converted
during the two-port conversion, so that the balanced transmission line is
converted to two series adaptors and an unbalanced transmission line of
impedance Z0 and delay TD. All the considerations regarding TD already made
in 2.10 apply as well in this case. The parameter TD will be dealt with in two
different modes according to the DELAYMETH option statement, as shown in
1.2.5. If the parameter TD is set to a value < TSTEP, the discretized delay will
assume the value TSTEP.
Since this element models only one propagating mode, in steady state the
differential voltage VN1-VN2 is equal to VN3-VN4, while, in general, VN1VN3

DWS 8.5 USER MANUAL

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