DCDCコンバータによる昇圧回路
ESR
IN
L
1 2
Rload
OUT
R1
R2
Q1
QN_SW
V+
0
Cout
D1
PWM Control
CircuitPWM output
pulse
VOUT=9V
tON tOFF
VIN=5V
L: IL
12Copyright(C) MARUTSU ELEC 2015
3. 回路解析シミュレーションの活用事例
詳細設計
CLP
100pF
Rf
560k
ESR
0.103
Cin
220uF
L
150u
1 2
Rload
180
R1
9.1k
R2
150k
Q1
Q2SD2623
OUT
R3
0.8
U1
NJM2377
-IN
FB
GND
OUTV+
CS
CT
REF
Rt
24k
Ct
470pF
IC = 0
D1
HRU0302A
0
V+
5V
0
IN
Cout
220uF
Rsf
160k
CS
4.7uF
IC = 0
0
Rsr
180k
0
トポロジー(回路方式)
詳細設計
13.
Time
86.810ms 86.816ms 86.822ms86.828ms
I(L)
0A
50mA
100mA
150mA
200mA
(86.818m,140.985m)
(86.821m,40.531m)
• PSpice is used to verify the circuit design.
• IL, PK=140.985mA and
IL,PK=140.985m-40.531m=100.454mA
• IL, PK is calculated as below.
• And the current ripple - IL, PK is calculated
as below
140mA2.96μ
150μ2
5
5
0.059
2
ON
IN
IN
OUTOUT
L,PK t
L
V
V
IV
I
mA992.96μ
150μ
5
ON
IN
L,PK t
L
V
ΔI
• Add trace I(L)
• Zoom to check the peak value.
IL, PK
13Copyright(C) MARUTSU ELEC 2015
3. 回路解析シミュレーションの活用事例
詳細設計(昇圧用コイル)
14.
• PSpice isused to verify the circuit design.
• IL,PK=101.168mA, ton=3μs.
• Vripple =14.8mVp-p
• Irms
*=53.856mArms.
Irms is larger than calculated value due to feedback loop
response ripple current.
Time
87.5484ms 87.5684ms
V(OUT)
9.06V
9.07V
9.08V
9.09V
SEL>>
(87.556m,9.0792)
(87.553m,9.0644)
I(L) rms(I(Cout))
0A
100mA
200mA
(87.556m,141.564m)
(87.553m,40.396m)
• COUT is determined from the Vripple Spec
(30mVp-p).
• If COUT >> IOUTton/Vripple
(50m2.96μ/30m=4.933μF), Vripple will
mainly caused by ESR.
• Select the capacitor that can handle the
ripple current Irms.
• COUT=220μF, ESR=103m is selected.
m103
99m
30m
)(
L
ppripple
I
V
ESR
IL, PK
13mArms
6.67μ
2.96μ
32
99m
32
t
tonI
I
L
rms
Irms
Vripple
14Copyright(C) MARUTSU ELEC 2015
3. 回路解析シミュレーションの活用事例
詳細設計(出力電解コンデンサのリップル現象)
15.
• Simulation resultshows output start-up time of the circuit. This circuit needs
55ms to reach steady state.
Time
0s 20ms 40ms 60ms 80ms 90ms
V(OUT)
4V
5V
6V
7V
8V
9V
10V
I(Rload)
20mA
30mA
40mA
50mA
SEL>>
V(OUT)
I(Rload)
15Copyright(C) MARUTSU ELEC 2015
3. 回路解析シミュレーションの活用事例
詳細設計
出力電流
出力電圧
16.
Time
60ms 65ms 70ms75ms 80ms 85ms 90ms
V(OUT)
9.05V
9.06V
9.07V
9.08V
9.09V
9.10V
SEL>>
Time
89.90ms 89.91ms 89.92ms 89.93ms 89.94ms 89.95ms 89.96ms 89.97ms 89.98ms 89.99ms
V(OUT)
9.060V
9.065V
9.070V
9.075V
9.080V
• Simulation result shows output ripple voltage caused by switching(18mVP-P) and
F.B loop oscillation(25mVP-P).
V(OUT)
全体図
V(OUT)
拡大図 18mVP-P
25mVP-P
16Copyright(C) MARUTSU ELEC 2015
3. 回路解析シミュレーションの活用事例
詳細設計(出力電圧のリップル波形)
17.
• Efficiency ofthe converter at load IOUT=50mA is 75.5%.
Time
70ms 75ms 80ms 85ms 90ms
100*W(Rload)/rms(-W(V+))
0
25
50
75
100
(90.000m,75.500)
Efficiency
17Copyright(C) MARUTSU ELEC 2015
3. 回路解析シミュレーションの活用事例
詳細設計(電源回路の効率シミュレーション)
18.
• Simulation resultshows the transient response of the circuit, when load currents
are 50mA to 10mA to 50mA steps .
V(OUT)
I(L)
I(Load)
負荷電流
Time
60ms 65ms 70ms 75ms 80ms 85ms 90ms
V(OUT)
9.050V
9.075V
9.100V
9.125V
I(L)
0A
100mA
200mA
I(I1)
0A
20mA
30mA
40mA
50mA
SEL>>
18Copyright(C) MARUTSU ELEC 2015
3. 回路解析シミュレーションの活用事例
詳細設計(負荷応答性のシミュレーション結果)
19.
• Simulation resultshows voltage and current of the devices.
• Select L and Cout that can handle their Irms value.
• The absolute maximum value of Q1 and D1 are compared to simulation result for stress analysis.
Time
0s 20ms 40ms 60ms 80ms 90ms
1 V(Cout:1) 2 rms(I(Cout))
0V
5V
10V
1
0A
50mA
100mA
2
SEL>>SEL>>
1 V(D1:2)- V(D1:1) 2 I(D1) avg(I(D1))
0V
10V
20V
1
100mA
200mA
300mA
2
>>
1 V(Q1:c) 2 I(Q1:c)
0V
5V
10V
15V
20V
1
250mA
500mA
2
>>
I(L) rms(I(L))
0A
200mAI(L) peak,
rms
I(L) = 261.054mA(peak) , 94.1399mA(rms)
V(Q1:C),
I(Q1:C)
Q1 2SD2623: VCEO=20V, ICMAX=0.5A
V(D1:K,D1:A),
IF(D1)
D1 HRU0302A: VRRM=20V, IO=0.3A(avg), IFSM=3A
V(Cout),
I(Cout) rms
I(Cout) = 50.255mA(rms)
100% of Rated Value
100% of Rated Value
19Copyright(C) MARUTSU ELEC 2015
3. 回路解析シミュレーションの活用事例
詳細設計
20.
Time
89.964ms 89.966ms 89.968ms89.970ms 89.972ms 89.974ms
1 V(Q1:c) 2 I(Q1:c)
0V
5V
10V
15V
20V
1
>>
0A
100mA
200mA
300mA
2
1 V(Q1:c)*I(Q1:c) 2 avg(W(Q1))
0W
200mW
400mW
600mW
1
SEL>>
0W
50mW
100mW
150mW
2
SEL>>
• Simulation result shows waveforms of IC and VCE of transistor Q1.Loss in peak and
average values are also shown.
100% of Rated Value (PC, max.=150mW)
PC, avg.=17.254mW
turn-on loss
Conduction loss
turn-off loss
V(Q1:C),
I(Q1:C)
P(Q1)
peak, avg
20Copyright(C) MARUTSU ELEC 2015
3. 回路解析シミュレーションの活用事例
詳細設計(損失計算)
Switching Transistor Losses
21.
Schottky Barrier DiodeLosses
Time
89.964ms 89.965ms 89.966ms 89.967ms 89.968ms 89.969ms 89.970ms 89.971ms 89.972ms 89.973ms
1 V(D1:1,D1:2) 2 I(D1)
-10V
-5V
0V
5V
10V
1
-200mA
-100mA
0A
100mA
200mA
2
SEL>>SEL>>
W(D1) avg(W(D1))
-100mW
-50mW
0W
50mW
100mW
• Simulation result shows waveforms of IF and VAK of diode D1.Loss in peak and
average values are also shown.
PD, avg.=18.45mW
Reverse
recovery loss
Conduction loss
V(D1:A,D1:K),
I(D1
P(D1)
peak, avg
Reverse
leakage loss
Reverse recovery
characteristic
21Copyright(C) MARUTSU ELEC 2015
3. 回路解析シミュレーションの活用事例
詳細設計(損失計算)