1660 S M Tec R5

Technical Handbook

Alcatel 1660SM
STM 64 Multiservice Metro Node

1660SM Rel. 5.2

Version B

3AL 91669 AAAA Ed.03

1660SM REL.5.2 TECHNICAL HANDBOOK
not permitted without written authorization from Alcatel.
All rights reserved. Passing on and copying of this
document, use and communication of its contents

TABLE OF CONTENTS

LIST OF FIGURES AND TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

HANDBOOK GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1 HANDBOOK STRUCTURE AND CONFIGURATION CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Handbook applicability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 Product-release handbooks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4 Handbook Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5 Handbook Configuration Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.1 List of the editions and of modified parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.2 Notes on Ed.01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5.3 Notes on Ed.02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5.4 Notes on Ed.03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2 SAFETY NORMS AND LABELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 First aid for electric shock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2 Safety Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.1 General Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.2 Labels Indicating Danger, Forbiddance, Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.3 Dangerous Electrical Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.4 Harmful Optical Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.5 Risks of Explosions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.6 Moving Mechanical Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.7 Heat–radiating Mechanical Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.8 Specific safety rules in this handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3 OTHER NORMS AND LABELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.1 General Norms – Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.2 General Norms – Turn–up & Commissioning, Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1.3 General Norms – Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 Electrostatic Dischargers (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3 Suggestions, notes and cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.4 Labels affixed to the Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

03 051118 ECR 25074 M.SEVERI ITAVE P. GHELFI ITAVE
S. MAGGIO – C. FAVERO
02 050414 ECR 23081 J. MIR ITAVE P. GHELFI ITAVE
01 041112 J. MIR ITAVE P. GHELFI ITAVE
ED DATE CHANGE NOTE APPRAISAL AUTHORITY ORIGINATOR
1AA 00014 0004 (9007) A4 – ALICE 04.10

1660SM REL. 5.2
Version B
TECHNICAL HANDBOOK

ED 03

3AL 91669 AA AA 1 / 706

706

4 LIST OF ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5 GENERAL ON ALCATEL CUSTOMER DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1 Products, product-releases, versions and Customer Documentation . . . . . . . . . . . . . . 57

5.2 Handbook supply to Customers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3 Aims of standard Customer Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.4 Handbook Updating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.4.1 Changes introduced in the same product-release (same handbook P/N) . . . . . . . . . . . . 58
5.4.2 Changes due to new product version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.5 Customer documentation on CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.5.1 Contents, creation and production of a CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.5.2 Use of the CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.5.3 CD–ROM identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.5.4 CD–ROM updating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

1 GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
1.1 Introduction to the equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
1.2 Insertion of the equipment into the network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
1.2.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
1.2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
1.2.3 SDH / CWDM integration in “ring” network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1.2.4 SDH / CWDM integration in “linear” network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1.2.5 Network protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

2 PHYSICAL CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.1 Equipment front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.1.1 1660SM Shelf “without fans” front view (SR60M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.1.2 19” Fans subrack front view (SRFAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.1.3 1660SM Shelf “with fans” front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.2 Part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.2.1 Equipment Shelf part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.2.2 Fans Subrack 19” part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.2.3 Explanatory notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.3 Relationship between Port Card and Access Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
2.4 Units front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.4.1 Port cards front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
2.4.2 Access cards front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.4.3 FAN subrack cover front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
2.4.4 Assembled Fans unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
3.2 Connections sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
3.3 SIGNAL MANAGEMENT SUB–SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
3.3.1 Signal management referred to ”G.783 1994” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
3.3.2 SDH port signal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
3.3.3 PDH port signal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
3.3.4 SIGNAL MANAGEMENT referred to ”G. 783” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
3.3.5 ATOMIC FUNCTION NAMING CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
3.3.6 SDH PORT FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
1AA 00014 0004 (9007) A4 – ALICE 04.10

3.3.7 PDH PORT FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
3.4 ISA (Integrated Service Adapter) introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
3.5 ISA – ATM management sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

ED 03

3AL 91669 AA AA 2 / 706

706

3.5.1 ATM ( Asynchronous Transfer Mode) basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
3.5.2 ATM in1660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
3.6 ISA – PR_EA (MPLS) sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
3.6.1 PR_EA (MPLS) generalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

3.6.2 PR_EA (MPLS) service in 1660SM equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

3.7 ISA – PR Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
3.7.1 PR Generalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
3.7.2 PR in 1660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
3.8 ISA – ETHERNET management sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
3.8.1 LAN to LAN transport service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
3.8.2 LAN to LAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
3.8.3 Main features description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
3.8.4 Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
3.8.5 Ethernet boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
3.9 ISA – ES (Ethernet Switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
3.9.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
3.9.2 ISA–ES series modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
3.10 4 x ANY HOST C subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
3.11 Coarse WDM sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
3.11.1 Equipment facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
3.11.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
3.11.3 “Ring” node functional scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
3.11.4 “Terminal” node functional scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
3.11.5 Optical span design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
3.12 Controller sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
3.12.1 Network management interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
3.12.2 ATM/IP/MPLS over SDH Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
3.13 Protection sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
3.13.1 EPS Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
3.13.2 MS linear trail Protection (1+1 linear APS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
3.13.3 MS linear trail Protection (1:N linear dual–ended APS) . . . . . . . . . . . . . . . . . . . . . . . . . . 337
3.13.4 SNCP (Sub–Network Connection Protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
3.13.5 Drop & Continue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
3.13.6 Collapsed dual node ring interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
3.13.7 Collapsed single node ring interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
3.13.8 MS–SPRING protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
3.14 Synchronizing sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
3.15 Auxiliary and DCC sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
3.16 Power supply sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
3.17 Remote inventory Sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
3.18 Frames Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
3.18.1 Synchronous 2048 Kb/s frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
3.18.2 ATM cells mapping into SDH/PDH frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

4 UNITS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
4.1 21 x 2 Mbit/s access card (A21E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
4.2 3 X 34 Mbit/s access card (A3E3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
4.3 3 X 45 Mbit/s access card (A3T3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
4.4 2 x 140/STM–1 O/E adapter (A2S1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
4.5 4 x STM–1 electrical access card (A4ES1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
4.6 Optical Access 12xSTM–1 (A12OS1E or A12OS1SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
1AA 00014 0004 (9007) A4 – ALICE 04.10

4.7 Electrical Access 16xSTM–1 (A16ES1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
4.8 High Speed protection access card (HPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
4.9 ISA – Ethernet access card (ETH–ATX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

ED 03

3AL 91669 AA AA 3 / 706

706

4.10 ISA – Gigabit Ethernet access Card (GETH–AG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
4.11 ISA –16 FEA–PR Fast Ethernet Access Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
4.12 ISA – 2 GBA–PR Fast Ethernet Access Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
4.13 Optical booster (BST10, BST15, BST17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

4.14 Optical 2.5 Gbit/s Preamplifier (PR16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

4.15 Electrical module (ICMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
4.16 STM–1 optical modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
4.17 STM–4 optical modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
4.18 4 x ANY plug–in modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
4.19 SFP optical modules: 1000B and 100B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
4.20 63 x 2 Mbit/s port card (P63E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
4.21 63 x 2 Mbit/s / G703 / ISDN–PRA port card ( P63E1N–M4) . . . . . . . . . . . . . . . . . . . . . . . . 435
4.22 3 x 34/45 Mbit/s port card (P3E3T3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
4.23 4 x STM–1 electrical/optical port card (P4S1N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
4.24 4 X 140/STM1 switchable O/E port card (P4E4N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
4.25 4 x STM–1 port (P4ES1N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
4.26 Port 16xSTM1 – 4xSTM4 (P16S1–4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
4.27 4 x OC3 AU3/TU3 CONVERSION port (P4OC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
4.28 STM–4 optical ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
4.29 4 x STM–4 optical port (P4S4N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
4.30 ISA – ATM MATRIX 4X4 (ATM4X4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
4.31 ISA – ATM MATRIX 4X4 ENHANCED (ATM4X4D3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
4.32 ISA – ATM MATRIX 4X4 ENHANCED (ATM4X4V2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
4.33 ISA – ATM MATRIX 8X8 (ATM8X8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
4.34 ISA–Packet Ring Edge Aggregator Unit (PREA1GBE, PREA4ETH) . . . . . . . . . . . . . . . 501
4.35 ISA – Packet Ring unit (ISA–PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
4.36 STM–16 optical port (two slots wide) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
4.37 STM–16 optical slim port (one slot wide) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
4.38 STM–64 optical port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
4.39 ISA – Ethernet/Fast Ethernet port (ETH–MB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
4.40 ISA –Giga Ethernet Main Board (GETH–MB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
4.41 ISA– Ethernet switch (ES1–8FE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
4.42 ISA– Ethernet switch (ES1–8FX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
4.43 ISA– Ethernet switch (ES4–8FE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
4.44 ISA ES–16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
4.45 4 X ANY HOST C card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
4.46 COADM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
4.47 COADM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
4.48 COMDX8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
4.49 2xCH Transponder SFP without optics (COWLA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
4.50 PQ2/EQC card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
4.51 MatrixE card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
4.52 CONGI card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
4.53 SERVICE card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
4.54 FAN SHELF 19” AND RELEVANT FAN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
4.55 ASSEMBLED FANS UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

5 TECHNICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
5.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
5.1.1 Optical Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
5.1.2 Electrical Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
1AA 00014 0004 (9007) A4 – ALICE 04.10

5.2 Electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
5.2.1 21 X 2 Mbit/s 75 Ohm electrical characteristics (A21E1) . . . . . . . . . . . . . . . . . . . . . . . . . . 601
5.2.2 21 X 2 Mbit/s 120 Ohm electrical characteristics (A21E1) . . . . . . . . . . . . . . . . . . . . . . . . . 601

ED 03

3AL 91669 AA AA 4 / 706

706

5.2.3 21 X 2 Mbit/s 120 Ohm K20 electrical characteristics (A21E1) . . . . . . . . . . . . . . . . . . . . . 601
5.2.4 3 X 34 Mbit/s electrical characteristics (A3E3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
5.2.5 3 X 45 Mbit/s electrical characteristics (A3T3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
5.2.6 STM–1 electrical characteristics (A4 ES1 and ICMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

5.2.7 140 Mbit/s electrical characteristics (ICMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

5.2.8 Engineering Order Wire characteristics (SERVICE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
5.2.9 AUX channels characteristics (SERVICE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
5.3 ATM interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
5.3.1 ATM matrix 4x4 switching capability (ATM4X4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
5.3.2 ATM matrix 4x4V2 switching capability (ATM4X4V2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
5.3.3 ATM matrix 4x4 D3 switching capability (ATM4X4D3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
5.3.4 ATM matrix 8x8 switching capability (ATM8X8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
5.4 PR_EA characteristics and MPLS data traffic management (PREA4ETH, PREA1GBE) 609
5.5 PR characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
5.5.1 ISA–PR port card interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
5.5.2 16FEA–PR access card interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
5.5.3 2GBA–PR access card interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
5.6 ETHERNET interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
5.6.1 Ethernet 10/100Base–T interface characteristics (ETH–MB + ETH–ATX) . . . . . . . . . . 612
5.6.2 Ethernet switch port card characteristics (ES1–8FE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
5.6.3 Ethernet switch port card characteristics (ES1–8FX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
5.6.4 Ethernet switch port card characteristics (ES4–8FE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
5.6.5 Ethernet switch port card characteristics (ISA ES–16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
5.6.6 Access Card Gigabit Ethernet interfaces characteristics (GETH–AG) . . . . . . . . . . . . . . 617
5.6.7 Gigabit Ethernet ports card interfaces characteristics (GETH–MB) . . . . . . . . . . . . . . . . . 618
5.7 4 x ANY clients characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
5.7.1 Gigabit Ethernet LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
5.7.2 Gigabit Ethernet SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
5.7.3 Fiber Channel 100–SM–LL–I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
5.7.4 Fiber Channel 100–M5–SL–I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
5.7.5 Fast Ethernet (100BASE FX)/FDDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
5.7.6 ESCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
5.7.7 Digital Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
5.8 Optical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
5.8.1 Example of a link using 1660SM with L–16.2 JE2 Port and 15 dBm Booster . . . . . . . . 640
5.8.2 Example of a link using 1660SM with L–64.2b “Extended” . . . . . . . . . . . . . . . . . . . . . . . . 641
5.8.3 Example of a link using 1660SM with L–64.2b “Reduced” . . . . . . . . . . . . . . . . . . . . . . . . 643
5.9 Coarse WDM subsystem units characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
5.9.1 COADM–1 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
5.9.2 COADM–2 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
5.9.3 MUX/DEMUX 8 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
5.9.4 2 Channels TRANSPONDER SFP without optical modulle . . . . . . . . . . . . . . . . . . . . . . . . 647
5.9.5 CWDM optical PLUGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
5.10 Power Supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
5.10.1 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
5.11 Alarm Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
5.12 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
5.12.1 1660SM subrack without fans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
5.12.2 1660SM subrack with fans shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
5.12.3 Fans shelf 19” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
1AA 00014 0004 (9007) A4 – ALICE 04.10

5.13 Environmental conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
5.13.1 Electromagnetic Compatibility (EMC) norms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
5.13.2 Waste from Electrical and Electronic Equipment (WEEE) . . . . . . . . . . . . . . . . . . . . . . . 655
5.13.3 Acoustical noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

ED 03

3AL 91669 AA AA 5 / 706

706

5.13.4 Climatic for operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
5.13.5 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
5.13.6 Transportation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

MAINTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

6 MAINTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
6.1 General safety rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
6.2 General rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
6.3 Maintenance Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
6.4 Instruments And Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
6.5 Routine Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
6.5.1 Routine maintenance every three months . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
6.5.2 Routine maintenance every year . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
6.5.3 Routine Maintenance every five year . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
6.6 Corrective Maintenance (Trouble/Shooting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
6.6.1 Fan unit substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
6.7 Set of spare parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
6.7.1 Suggested Spare Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
6.7.2 General rules on spare parts management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
6.7.3 Particular rules on spare parts management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
6.8 Repair Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

DISMANTLING & RECYCLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

7 DISMANTLING & RECYCLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
7.1 WEEE general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
7.2 How to disassembly equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
7.2.1 Tools necessary for disassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
7.2.2 Subrack disassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
7.2.3 Unit disassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
7.2.4 Hazardous materials and components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
7.3 Eco declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

HARDWARE SETTING DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

UNITS DOCUMENTATION LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
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LIST OF FIGURES AND TABLES

FIGURES

Figure 1. Subrack label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 4. Labels on units with standard cover plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 5. Modules label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 6. Internal label for Printed Board Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7. Back panels internal label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 8. Label specifying item not on catalogue (P/N. and serial number) . . . . . . . . . . . . . . . . . . . . 48
Figure 9. Label specifying item on catalogue (P/N. and serial number) . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 10. Item identification labels – item on catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 11. Label identifying the equipment (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 12. CE label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 13. WEEE label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 14. Example of SDH/DATA/CWDM integration in “metro area” . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 15. Example of ATM Transport management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 16. ISA–PR Deployment Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 17. Ethernet service application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 18. Terminal multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 19. Add/Drop Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 20. ”HUB” STM–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 21. Point–to–point links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 22. Linear drop–insert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 23. Ring structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 24. Meshed topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 25. SDH/CWDM integration in “ring” with COADM units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 26. SDH/CWDM integration in “ring” with COADM unit: detailed view . . . . . . . . . . . . . . . . . . 76
Figure 27. SDH/CWDM integration in “ring” with MUX/DEMUX unit . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 28. SDH/CWDM integration in “ring” with MUX/DEMUX unit: detailed view . . . . . . . . . . . . . . 78
Figure 29. SDH/CWDM integration in “linear” network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 30. SDH/CWDM integration in “linear” network (MUX/DEMUX): detailed view . . . . . . . . . . . 79
Figure 31. SDH/CWDM integration in “linear” network (COADM unit): detailed view . . . . . . . . . . . . 80
Figure 32. 1660SM units positioning in “SR60M” subrack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 33. 19” Fans subrack unit slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 34. 1660SM units positioning in 1660 subrack with fans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 35. PDH, SDH electrical ports front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 36. 4 x STM–1, 4 x OC3 port : front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 37. 16xSTM–1 – 4xSTM–4 port front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 38. STM–4 optical port front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 39. 4 x STM–4 port card – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 40. STM–16 optical front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 41. I–16 PORT SFF (intra–office) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 42. STM–16 SFP SLIM port optical front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 43. ATM 4X4 and ATM 4X4V2 card – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 44. ATM 8X8 card – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 45. STM–64 optical port front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 46. ISA – Ethernet port front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 47. ISA– Gigabit ETHERNET board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 48. ISA – ES4–8FE port front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 49. ISA – ES1–8FE port front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 50. ISA ES1–8FX front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

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Figure 51. ISA ES–16 front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 52. ISA– PRE_EA Matrix 4x Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 53. ISA– PRE_EA Matrix 1 x GB–ETH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 54. ISA– PR Matrix 4x4STM4 PLUG–IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 55. COWLA2 front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 56. 4xANY Host C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 57. MATRIXE card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 58. EQUICO (PQ2/EQC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 59. Control and General interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 60. SERVICE interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 61. 21 x 2 Mbit/s 75 ohm access card 1.0/2.3 connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 62. 21 X 2 Mbit/s 120 Ohm access card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 63. 3 X 34 Mbit/s 75 ohm access card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 64. 3 X 45 Mbit/s 75 ohm access card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 65. 4 X STM–1 access card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 66. High Speed protection – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 67. 2 x 140/STM–1 O/E adapter (access card)– front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 68. Optical access 12xSTM1 unit front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 69. Optical access 12xSTM1 SLIM unit front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 70. Electrical access 16xSTM1 unit front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 71. ISA – Ethernet access front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 72. ISA – Gigabit Ethernet access card front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 73. ISA PR 2XGBE 1000 access card front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 74. ISA PR16XETH 10/100 access card front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 75. COADM1 front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 76. COADM2 front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 77. COMDX8 front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 78. STM–1/STM–4 optical module front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 79. STM–1 or 140 Mbit/s electrical module front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 80. Relationship between SFP modules and housing boards . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 81. 4XANY plug–in module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 82. Optical Booster card front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 83. PREAMPLIFIER 2.5 GB/S front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 84. 19” Fans subrack cover front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 85. Assembled Fans unit front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 86. LOI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 87. HOI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 88. TTF and HOA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 89. 1660SM Block diagram – ( SDH and PDH boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 90. 1660SM Block diagram – (SDH and PDH boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 91. 1660SM Block diagram – (SDH boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 92. 1660SM Block diagram – (SONET and 4xANY HOSTC boards) . . . . . . . . . . . . . . . . . . . 190
Figure 93. 1660SM Block diagram – (CWDM boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 94. 1660SM Block diagram – (CWDM boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 95. 1660SM Block diagram – ( Common units and ISA boards) . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 96. 1660SM Block diagram – (ISA boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 97. 1660SM Block diagram – (ISA – ES boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 98. 1660SM Block diagram – (ISA – ETHERNET boards) . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 99. 1660SM Block diagram – (ISA–PR board) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 100. MATRIXE– Cross connection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 101. SDH signal management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 102. 2Mbit/s, 34 Mbit/s, 45 Mbit/s signal management block diagram . . . . . . . . . . . . . . . . . . 204
Figure 103. 140Mbit/s signal management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 104. 1660SM Block Diagram: signal management (SDH port) . . . . . . . . . . . . . . . . . . . . . . . . 216

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Figure 105. 1660SM Block Diagram: signal management ( 2Mbit/s PDH ports) . . . . . . . . . . . . . . . 218
Figure 106. 1660SM Block Diagram: signal management ( 34 Mbit/s and 45 Mbit/s PDH ports) . 220
Figure 107. 1660SM Block Diagram: signal management ( 140 Mbit/s PDH ports) . . . . . . . . . . . . 222
Figure 108. Example of technology convergency with ISA boards in OMSN . . . . . . . . . . . . . . . . . . . 224

Figure 109. Relationship between the VC, the VP and the TP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 110. Basic format of an ATM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 111. ATM network interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 112. UNI and NNI ATM cell header and payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 113. 1660SM with ATM Matrix architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 114. Leased line service versus Data transport service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 115. MPLS subsystem, protocol stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 116. Framing for MPLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 117. MPLS label format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 118. PPP frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 119. HDLC frame with PPP encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 120. Ethernet MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 121. Ethernet “Tagged” MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 122. Ethernet frame format for “MPLS over Ethernet” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 123. MPLS Tunnelling Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 124. Generic MPLS aggregation scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 125. MPLS subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 126. ISA–PR Sub–System Architecture (Overlay Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 127. ISA–PR Sub–System Architecture (Independent Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 128. Traffic flow and processing in 1660 SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 129. ISA–PR Policing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 130. ISA–PR Traffic Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 131. Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 132. Bottlenecks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 133. RPR protection mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 134. Packet protection (and QoS assurance) in multiring network : MPLS over RPR . . . . . 260
Figure 135. Customer Edge Dual Homing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 136. Relationship with other ISA Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 137. Example of an Ethernet stream transport through a SDH network . . . . . . . . . . . . . . . . . 263
Figure 138. LAN to LAN service block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 139. GFP frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 140. GFP encapsulation of the MAC frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 141. Flow control mechanism: input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 142. Flow control mechanism: output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 143. Flow control mechanism: External control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 144. Messages dispatching via Virtual Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 145. Messages dispatching via Packet Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 146. Board Ethernet 10/100: System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 147. Example of Ethernet service application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 148. Gigabit Ethernet System architecture: Gigabit access with Fast Ethernet board . . . . . 279
Figure 149. Gigabit Ethernet System architecture:Gigabit Ethernet main board . . . . . . . . . . . . . . . . 280
Figure 150. Ethernet Private Line service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 151. Ethernet Virtual Private Line service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Figure 152. Ethernet Virtual LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Figure 153. Broadband Access service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 154. ISA–ES access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 155. Traffic flow and processing in ISA–ES series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 156. ISA–ES series ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 157. ISA–ES series traffic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 158. WRED Congestion avoidance mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

ED 03

3AL 91669 AA AA 9 / 706

706

Figure 159. ISA–ES series operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 160. Ethernet Multiplexing Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 161. Multiple customers on a single NNI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 162. 4xANY HOST–C: Client allocation grid in “enhanced” slot . . . . . . . . . . . . . . . . . . . . . . . . 295

Figure 163. 4xANY HOST–C: module configuration in “enhanced” slot . . . . . . . . . . . . . . . . . . . . . . . 295

Figure 164. Client allocation grid in “HS slots” with GE/FC/FICON . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 165. Client allocation grid in “HS slots” with FE/FDDI/ESCON/DV . . . . . . . . . . . . . . . . . . . . . 298
Figure 166. module configuration in “HS” slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 167. COADM functionality: example of equipment shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 168. MUX/DEMUX functionality: example of shelf equipment . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 169. 1660SM signal flow diagram with WDM application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 170. 1660SM (WDM application) ’ring’ node functional scheme (1) . . . . . . . . . . . . . . . . . . . . 304
Figure 174. 1660SM (WDM application)’end’ node functional scheme (Mux/Demux) . . . . . . . . . . . 307
Figure 175. 1660SM (WDM application) ’end’ node functional scheme (COADM) . . . . . . . . . . . . . . 308
Figure 176. Passive optical operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 177. COMDX8 insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Figure 178. COADM2 insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Figure 179. COADM1 insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 180. 1660SM Control Sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 181. 1660SM general management architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 182. Connection Mode for TMN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 183. Protocol stack for SDH/ATM management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Figure 184. Example of management of a network with SDH and ATM/IP/MPLS traffic . . . . . . . . . 320
Figure 185. Low Speed Link Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Figure 186. Example of EPS protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 187. High Speed connections (3x34, 3x45, 4x155 Mbit/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 188. High Speed connections (16xSTM–1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 189. Examples of ATM MATRIX EPS protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Figure 190. Messages exchanged between the EC and the ISA–ATM boards in EPS group . . . . . 330
Figure 191. Examples of MPLS (PR_EA..) boards protection scheme . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 192. Messages exchanged between EC and ISA–PR_EA Matrix... boards in EPS group . 333
Figure 193. Linear 1+1 single ended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Figure 194. Linear 1+1 dual ended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Figure 195. MSP Linear 1:N Dual–Ended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Figure 196. Typical ring network with SNCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Figure 197. Failure examples in SNCP ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Figure 198. SNCP example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Figure 199. Drop and Continue D/C A INS A (called “Normal” on C.T.) . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 200. Drop and Continue D/C A INS B (called “Inverse” on C.T.) . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 201. Drop and Continue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 202. Drop and Continue – 1st failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 203. Drop and Continue – 2nd failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 204. Collapsed dual node interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Figure 205. Collapsed dual node interconnection – 1st failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 206. Collapsed dual node interconnection – 2nd failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 207. Collapsed single node ring interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Figure 208. Collapsed single node ring interconnection –1st failure . . . . . . . . . . . . . . . . . . . . . . . . . . 352
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 209. Collapsed single node ring interconnection –2nd failure . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 210. 2F MS SPRING Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 211. Effect of a BRIDGE “B side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Figure 212. Effect of a BRIDGE “A side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

ED 03

3AL 91669 AA AA 10 / 706

706

Figure 213. Effect of SWITCH “B side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 214. Effect of SWITCH “A side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 215. Line break recovering operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Figure 216. 2F MS–SPRING example of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Figure 217. Squelching on isolated Node connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

Figure 218. MS SPRING Drop and Continue, Insert Continues (protected) . . . . . . . . . . . . . . . . . . . 362
Figure 219. Synchronization function : block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Figure 220. AUX and DCC management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Figure 221. 1660SM –Input power stage and distributed power supply . . . . . . . . . . . . . . . . . . . . . . . 369
Figure 222. Remote Inventory sub–system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 223. 1660SM: SDH multiplexing structure and AU–3/TU–3 conversion . . . . . . . . . . . . . . . . . 371
Figure 224. VC–12 Structure (asynchronous mapping of 2048 Kbit/s) . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 225. TU–12 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Figure 226. VC–3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 227. TU–3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 228. VC–4 Structure and POH byte contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Figure 229. STM–1 structure and SOH byte contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Figure 230. STM–4 structure and SOH byte contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Figure 231. Structure of STM–16 and SOH bytes contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Figure 232. STM–64 structure and SOH byte contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 233. Synchronous 2048 Kb/s signal: basic frame overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Figure 234. Synchronous 2048 Kb/s signal: CRC–4 multiframe overhead . . . . . . . . . . . . . . . . . . . . . 381
Figure 235. Mapping of ATM cells into VC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Figure 236. Mapping of ATM cells into VC4/VC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Figure 237. Mapping of ATM cells into 2048 kb/s frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 238. Mapping of ATM cells into 34368 kb/s frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 239. 21 x 2 access card – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Figure 240. 3 x 34 access card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Figure 241. 3 x 45 access card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Figure 242. 2 x 140/STM–1 O/E adapter (access card) block diagram . . . . . . . . . . . . . . . . . . . . . . . 392
Figure 243. 4 x STM–1 access card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Figure 244. 12 x STM–1 optical access card block diagram (A12OS1E or A12OS1SE ) . . . . . . . . 397
Figure 245. 16 x STM–1 electrical access card block diagram (A16ES1E) . . . . . . . . . . . . . . . . . . . . 400
Figure 246. HPROT access card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Figure 247. Ethernet Access –Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Figure 248. Gigabit Ethernet Access card –Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Figure 249. 16FEA–PR Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Figure 250. 2GBA–PR Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Figure 251. BSTxx – optical block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Figure 252. BSTxx – card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Figure 253. PR16 optical path and control signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Figure 254. PR16 card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Figure 255. STM–1 Electrical module –block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Figure 256. STM–1 Optical module – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Figure 257. STM–4 optical module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Figure 258. SFP optical modules general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Figure 259. 63 x 2 Mbit/s card – Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Figure 260. 63 x 2 Mbit/s G.703/ISDN–PRA, Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Figure 261. Functional Diagram of the NT ISDN–PRA block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Figure 262. 3x34/45 port card –Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 263. 4 x STM–1 Electrical/Optical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Figure 264. 4 x 140/STM–1 Electrical / Optical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Figure 265. Mapper /Demapper 140–PDH / 155–STM1 block diagram . . . . . . . . . . . . . . . . . . . . . . . 454
Figure 266. 4 x STM–1 Electrical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

ED 03

3AL 91669 AA AA 11 / 706

706

Figure 267. 16x STM–1 – 4x STM–4 port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Figure 268. 4 x OC3 AU3/TU3 conversion port(P40C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Figure 269. AU3/TU3 conversion block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Figure 270. STM–4 –block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Figure 271. 4xSTM–4 optical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

Figure 272. ATM 4X4 card – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Figure 273. ATM4X4V2 card – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Figure 274. ATM 8X8 card – Block diagram part A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Figure 275. ATM 8X8 card – Block diagram part B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Figure 276. MPLS+4FE Unit (PREA4ETH) – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Figure 277. MPLS+1GbE Unit (PREA1GBE) – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Figure 278. PR unit functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Figure 279. STM–16 optical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Figure 280. STM–16 slim port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Figure 281. STM–64 optical port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Figure 282. ETHERNET port (ETH–MB) – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Figure 283. Gigabit Ethernet Unit – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Figure 284. ISA ES1–8FE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 285. ISA ES4–8FE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Figure 286. ISA ES16 unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Figure 287. 4 x ANY HOST C card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Figure 288. COADM1 unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
Figure 289. COADM2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Figure 290. MUX/DEMUX8 (COMDX8) block diagram and LOS detection in ’passive’ boards . . . 559
Figure 291. 2xCH Transponder SFP Without optics COWLA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Figure 292. 1660SM PQ2/EQC Card Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Figure 293. MATRIXE card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Figure 294. CONGI – Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Figure 295. SERVICE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Figure 296. Fans shelf 19” general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Figure 297. Fans unit for fan shelf 19” block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Figure 298. Assembled Fans unit power supply and alarms general block diagram . . . . . . . . . . . . . 588
Figure 299. Assembled Fans unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Figure 300. Example of a link using 1660SM with L–64.2b “Extended” . . . . . . . . . . . . . . . . . . . . . . . 641
Figure 301. Example of a link using 1660SM with L–64.2b “Reduced” . . . . . . . . . . . . . . . . . . . . . . . . 643
Figure 302. Climatogram for Class 3.2 : Partly temperature controlled locations . . . . . . . . . . . . . . . 657
Figure 303. Climatogram for Class 1.2: not temperature controlled storage location . . . . . . . . . . . . 659
Figure 304. Repair form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Figure 305. Subrack front and rear view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Figure 306. Handle removing and disassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
Figure 307. Rear cover removing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Figure 308. Back Panel removing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Figure 309. Upper and lower guides plane removing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Figure 310. Side wall removing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Figure 311. Optical fiber duct, guides and contact spring removing . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Figure 312. Side coverplate removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Figure 313. Levers removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Figure 314. Optical connectors support removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Figure 315. Side coverplate and contact spring removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Figure 316. Internal connectors removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
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Figure 317. Dissipator removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Figure 318. Modules removal from dissipator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Figure 319. Daughter boad removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Figure 320. Gold connector removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

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Figure 321. Internal cables removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Figure 322. Connector metal support removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

TABLES

Table 1. Handbooks related to the specific product hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 2. Handbooks related to the specific product SW management and local product control . . 18
Table 3. Handbooks related to ATM specific product SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Handbooks related to PR_EA specific product SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Handbooks related to PR specific product SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Handbooks related to ISA ES specific product SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Handbooks common to Alcatel Network Elements using 1320CT platform . . . . . . . . . . . . 21
Table 8. Optional handbooks common to 16xxSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Documentation on CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Handbook configuration check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. IEC 950 –Table 16: Overtemperature limits, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12. Label references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 13. List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 14. Network application versus configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 15. Main part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 16. Accessories list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 17. Fans Subrack 19” part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 18. Explanatory notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 19. Relationship between P63E1, P63E1N–M4 (63 X 2 Mbit/s unit) port card and A21E1 access
card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 20. Relationship between P3E3T3 (3X34/45 Mbit/s Switchable unit) port card and A3E3 access
card (3X34 Mbit/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 21. Relationship between P3E3T3 (3X34/45 Mbit/s Switchable unit) port card and A3T3 access
card (3X45 Mbit/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 22. Relationship between P4S1N, P4E4N, P4OC3 port card and A2S1 access card . . . . 113
Table 23. Relationship between P16S1–4E port card and A12OS1E access card . . . . . . . . . . . . 114
Table 24. Relationship between P16S1–4E port card and A12OS1SE access card . . . . . . . . . . . 115
Table 25. Relationship between P16S1–4E port card and A16ES1E access card . . . . . . . . . . . . . 116
Table 26. Relationship between P4ES1N (4xSTM–1 Electrical) port card and A4ES1 access card. 117
Table 27. Relationship between ETH–MB (11x10/100 Mb/s Ethernet) port card and ETH–ATX access
card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 28. Relationship between ETH–MB (10/100Mb) port card and GETH–AG (1.25 Gb/s) access
card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 29. Relationship between ISA ES–16 port card and and ETH–ATX access card. . . . . . . . . . 120
Table 30. Relationship between ISA ES–16 port card and and GETH–AG access card. . . . . . . . . . 121
Table 31. Relationship between ISA–PR port card and 16FEA–PR or 2GBA–PR access cards. . . 122
Table 32. Interfaces acceding to the MPLS functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 33. Sub–systems & involved cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 34. High Order/Low Order connections for 1660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 35. ATM transport network layered model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 36. ATM traffic contracts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 37. MPLS layer stack over SDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 38. MPLS layer stack over ETHERNET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 39. Interfaces acceding to the MPLS functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 40. Relationship between 4xANY optical modules and client type . . . . . . . . . . . . . . . . . . . . . . 293
Table 41. 4xANY HOST C client type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 42. Modules configuration in “Enhanced HS” slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
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Table 43. Modules configuration in “HS” slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 44. CWDM channels grid supported by 1660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Table 45. Boards insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

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Table 46. Fiber technical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Table 47. Optical transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Table 48. MSP protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Table 49. Example of SNCP protected groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Table 50. 16FEA–PR card LEDs designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

Table 51. 16FEA–PR interface LED designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Table 52. 2GBA–PR card LED designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Table 53. 2GBA–PR interface LED designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Table 54. PR unit LED designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Table 55. CONGI A and CONGI B interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Table 56. Remote alarm provided by the AND/OR block available on CONGI in slot 10 . . . . . . . . . 573
Table 57. Remote alarm provided by the AND/OR block available on CONGI in slot 12 . . . . . . . . . 574
Table 58. Rack lamps signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Table 59. L1, L2 LEDs status for selective call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Table 60. L1, L2 LEDs status for omnibus call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Table 61. Hazard level classification of different optical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Table 62. ATM4X4 board: configurable TPs type and max, number . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Table 63. ATM4X4V2 board: configurable TPs type and max, number . . . . . . . . . . . . . . . . . . . . . . . . 606
Table 64. ATM4X4D3 board: configurable TPs type and max, number . . . . . . . . . . . . . . . . . . . . . . . . 607
Table 65. ATM8X8 board: configurable TPs type and max, number . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Table 66. Parameters specified for STM–1 Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Table 67. Parameters specified for STM–4 Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Table 68. STM–16 Optical interfaces (Single Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Table 69. STM–16 Optical interfaces (Multi Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Table 70. Parameters specified for STM–64 optical interfaces (Single Channel) . . . . . . . . . . . . . . . 634
Table 71. Parameters specified for 1000B–SX Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Table 72. Parameters specified for 1000B–LX Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Table 73. Parameters specified for 1000B–ZX Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Table 74. Parameters specified for Optical Booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Table 75. L–64.2b “Extended” characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Table 76. L–64.2b “Reduced” characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Table 77. Relation between Alarm severity terminology displayed on C.T./O.S. and alarm severity ter-
minology used for the EQUICO leds and CONGI remote alarm connector pins. . . . . . . . . . . . . . . 650
Table 78. Transportation climatic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Table 79. List of hazardous materials and components present in the equipment . . . . . . . . . . . . . . 694
Table 80. Example of correspondence between CS and ’suffix + ICS’ . . . . . . . . . . . . . . . . . . . . . . . . 701
Table 81. Hardware presetting documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
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1 HANDBOOK STRUCTURE AND CONFIGURATION CHECK

1.1 General information

WARNING

ALCATEL makes no warranty of any kind with regards to this manual, and specifically disclaims the
implied warranties of merchantability and fitness for a particular purpose. ALCATEL will not be liable
for errors contained herein or for damages, whether direct, indirect, consequential, incidental, or
special, in connection with the furnishing, performance, or use of this material.

NOTICE

The product specification and/or performance levels contained in this document are for information
purposes only and are subject to change without notice. They do not represent any obligation on the
part of ALCATEL.

COPYRIGHT NOTIFICATION

The technical information of this manual is the property of ALCATEL and must not be copied,
reproduced or disclosed to a third party without written consent.

1.2 Handbook applicability

This handbook applies to the following product-releases:

PRODUCT ANV P/N FACTORY P/N
1660SM 3AL 36301 AAAA 521.203.300

PRODUCT RELEASE VERSION ANV P/N FACTORY P/N
1660SM 5.2 3AL 81407 ACAA ––.––.––
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1.3 Product-release handbooks

The list of handbooks given here below is valid on the issue date of this Handbook and
can be changed without any obligation for ALCATEL to update it in this Handbook.

Some of the handbooks listed here below may not be available on the issue date of this
Handbook.

The standard Customer Documentation in the English language for the equipment whose
product-release-version is stated in para.1.2 on page 17 consists of the following handbooks:

Table 1. Handbooks related to the specific product hardware

THIS
REF HANDBOOK ANV Part No.
HDBK

1660SM Rel.5.2
3AL 91669 AAAA
Technical Handbook
[1]
Provide information regarding Equipment description, Maintenance , Hardware
setting documentation

1660SM Rel.5.2
3AL 91669 BAAA
Installation Handbook
[2]
Provide information regarding Equipment Installation, according to A–Installation
Engineering Department rules.

1660SM Rel.5.2
3AL91669 CAAA
Turnup & Commissionig Handbook
[3]
Provide information regarding Equipment Turn–On, Test and Operation,
according to A–Installation Engineering Department rules.

Table 2. Handbooks related to the specific product SW management and local product control

THIS
REF HANDBOOK ANV Part No. HDBK
or note

Metro OMSN Rel.4.4/5.2
3AL 91670 AAAA
CT Operator’s Handbook
[4]

Provides 1660SM “SDH” Craft Terminal screens and operational procedures
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Table 3. Handbooks related to ATM specific product SW

THIS

or note

ATM Rel.1.2
[5] 3AL 80814 AAAA
Operator’s Handbook

ATM Rel.2.0
[6] 3AL 81826 AAAA

ATM Rel.2.1
[7] 3AL 89777 AAAA

ATM Rel.2.2
[8] 3AL 91714 AAAA

Provides ATM Craft Terminal screens and operational procedures

Table 4. Handbooks related to PR_EA specific product SW

THIS
or note

PR_EA Rel.1.1
[9] 3AL 81062 BAAA

Provides PR_EA Terminal screens and operational procedures

Table 5. Handbooks related to PR specific product SW

THIS
or note

PR Rel.1.0
[10] 3AL 81771 AAAA

PR Rel.1.1
[11] 3AL 91658 AAAA

PR Rel.1.2
[12] 3AL 91715 AAAA

Provides PR Craft Terminal screens and operational procedures
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Table 6. Handbooks related to ISA ES specific product SW

THIS

HDBK

or note

ES1 Rel.1.0
[13] 3AL 89872 AAAA

ES1/ES4 Rel.1.1
[14] 3AL 89871 AAAA

ES1/ES4 Rel.1.2
[15] 3AL91804 AAAA

ES16 Rel.2.0
[16] 3AL 89870 AAAA

ES16 Rel.2.1
[17] 3AL 91716 AAAA

Provides ISA–ES Craft Terminal screens and operational procedures
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Table 7. Handbooks common to Alcatel Network Elements using 1320CT platform

FACTORY THIS
Part No. HDBK

1320CT 3.x
3AL 79551 AAAA 957.140.042 N
Basic Operator’s Handbook
[18]
Provides general information and operational procedures common to all
1320CT (Craft terminal) of Alcatel InfoModel Network Elements.

1330AS Rel.6.5
3AL 88876 AAAA ––––––––

Provides detailed information and operational procedures regarding the alarm
[19]
Surveillance software embedded in the 1320CT software package.
Information about Historical Alarms an Network Element Symbols
Management ( Physical Network Management) are not valid for Craft Terminal.
They are only used by Network Management.

ELB Rel.2.x Operator’s Handbook 3AL 88877 AAAA ––––––––

[20]
Provide detailed information and operational procedures regarding the Event
Log Browser software embedded in the 1320CT software package.
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Table 8. Optional handbooks common to 16xxSM

FACTORY THIS
Part No. HDBK

S9–16xxSM
3AL 78901 AAAA 955.100.692 N
System Installation Handbook
[21]
Provides general installation rules necessary to install the Optinex family
equipment in the S9 Rack.

Optinex RACK–16xxSM
3AL 38207 AAAA 955.110.202 L
System Installation Handbook
[22]
Provides general installation rules necessary to install the Optinex family
equipment in the Optinex Rack.

N.B. Handbooks REF. [21] and [22] are available only on paper support

Table 9. Documentation on CD–ROM
See para. 5.5 on page 59

REF CD–ROM TITLE ANV Part No. FACTORY Part No.

1660SM Rel.5.2 CD–ROM–DOC EN 3AL 91671 AAAA ––.––.––
[23]
Contains, in electronic format, the following handbooks: REF. [1] to [4]

1320CT 3.x BASIC CD–ROM–DOC EN 3AL 79552 AAAA 417.100.032
[24]
Contains, in electronic format, the following handbooks: REF. [18] to [20]

ATM 1.2 CD–ROM–DOC EN 3AL 80815 AAAA ––.––.––
[25]
Contains, in electronic format, the following handbooks: REF. [5]

[26]
Contains, in electronic format, the following handbook: REF. [6]

[27]

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REF CD–ROM TITLE ANV Part No. FACTORY Part No.

PR_EA 1.1 CD–ROM–DOC EN 3AL 81063 BAAA ––.––.––

[29]


PR 1.0 CD–ROM–DOC EN 3AL 81769 AAAA ––.––.––
[30]

[31]

[32]

ES1 1.0 CD–ROM–DOC EN 3AL 89875 AAAA ––.––.––
[33]

ES1/ES4 1.1 CD–ROM–DOC EN 3AL 89874 AAAA ––.––.––
[34]

ES1/ES4 1.2 CD–ROM–DOC EN 3AL91805 AAAA ––.––.––
[35]

[36]

[37]
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1.4 Handbook Structure

This handbook has been edited according to the Alcatel standardized “drawing–up guides” complying with
such suggestion.

This handbook is divided into the following main topics as described in the table of contents:

HANDBOOK GUIDE: It contains general information on safety norms, EMC and type
of labels that might be affixed to the equipment. Furthermore,
it describes the handbook structure and the customer
documentation. The abbreviation list is supplied too.

DESCRIPTION: It contains all the equipment’s general and detailed system
features including its application in the telecommunication
network. Furthermore, it supplies the equipment description and
specifications (i.e., system, mechanical,electrical and/or
optical).

MAINTENANCE: It contains all the details for periodic checks, fault location and
repair procedures and restore to normal operation through the
withdrawal of faulty units and their replacement with spares (*)

DISMANTLING & RECYLING It contains information for subrack/units dismantling and
recycling and list of hazardous materials.

APPENDICES: Section envisaged (but not necessarily included) to describe
possible alternative unit.

HARDWARE SETTING It encloses the documents related to unit hardware setting
DOCUMENTATION: operations, if envisaged.

ANNEXES: Section envisaged (but not necessarily included) containing
additional documentation or general information on other topics
not inherent to the chapters making up the handbook.

(*) If the equipment is software integrated and man–machine interfaced (through a PCD, PC, Work
Station or other external processing/displaying system) the maintenance carried out with such
system is described in the Operator’s Handbook (see para.1.3 on page 18 )
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1.5 Handbook Configuration Check

1.5.1 List of the editions and of modified parts

The following table indicates the handbook parts new and modified with respect to the previous edition.

Legenda

n = new part p =proposal part
m = modified part PR =proposal edition

Table 10. Handbook configuration check

EDITION 01 02 03 04 05 06
DESCRIPTION n
1. GENERAL n
2. PHYSICAL CONFIGURATION n m m
3. FUNCTIONAL DESCRIPTION n m
4. UNITS DESCRIPTION n m m
5. TECHNICAL SPECIFICATION n m m
MAINTENANCE n
6. MAINTENANCE n
DISMANTLING & RECYCLING n
7. n
APPENDICES
Nothing envisaged
HARDWARE SETTING DOCUMENTATION n
Unit documentation list n m
ANNEXES
Nothing envisaged

Note: the edition of the enclosed documents (sections HARDWARE SETTING DOCUMENTATION
and ANNEXES) is not subjected to configuration check.
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1.5.2 Notes on Ed.01

Ed.01 created on June 2004 is the first validated and officially released issue of this Handbook.


Ed.02 created on April 2005 has been edited for:

– New Hardware setting document (MSZZQ) has been added

– Correction of CWDM units characteristics

– A12OS1SE access cad added.


Ed.03 created on September 2005 has been edited for:

– Dismantling & Recycling procedures introduction

– Added new STM64 PORT XFP

– Added new Optical Modules LC

– Added new SFP “DDM” module

– Added 16xSTM1 High Speed Protection module

– Added Optical Compensation Device

– Correction on ISA PR_EA figures about data frame structure

– Correction for COADM “Loss of signal” detection not managed

– Editing corrections
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2 SAFETY NORMS AND LABELS

2.1 First aid for electric shock

Do not touch the patient with bare hands until the circuit has been opened.

Open the circuit by switching off the line switches. If that is not possible, protect yourself with dry
material and free the patient from the conductor.

ARTIFICIAL RESPIRATION

It is important to start mouth to mouth resuscitation at once and seek medical help immediately.

TREATMENT OF BURNS

This treatment should be used after the patient has regained consciousness. It can also be employed while
the artificial respiration is being applied (in this case there should be at least two persons present).

WARNING:

• Do not attempt to remove his clothing from the burnt parts;

• Apply dry gauze on the burns;

• Do not apply ointments or other oily substances.
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Mouth to mouth resuscitation method

Lay the patient supine with his arms parallel with the body, if the patient is laying

1 on an inclined plane, make sure that his stomach is slightly lower than his chest.

Open the patient’s mouth and check that there are no extraneous bodies in his
mouth (dentures, chewing–gum etc.),

Kneel beside the patient level with his head. Put
a hand under the patient’s head and one under
2
his neck (see fig.) Lift the patient’s head and let
it recline backwards as far as possible

Shift the hand from the patient’s neck to is chin:
place your thumb between his chin and his
mouth, the index along his jawbone, and keep the
3 other fingers closed together (see fig.). While
performing these operations take a good supply
of oxygen by taking deep breaths with your
mouth open.

With your thumb between the patient’s chin and
4 mouth keep his lips together and blow into his
nasal cavities (see fig.)

While performing these operations observe if the
patient’s chest rises (see fig.) If not it is possible
that his nose is blocked: in that case open the
patient’s mouth as much as possible by pressing
on his chin with your hand, place your lips around
5 his mouth and blow into his oral cavity. Observe
if the patient’s chest heaves. This second
method can be used instead of the first even
when the patient’s nose is kept closed by
pressing the nostrils together using the hand you
were holding his head with. The patient’s head
must be kept sloping backwards as much as
possible.

6 Start with ten rapid expirations, hence continue at a rate of twelve/fifteen
expirations per minute. Go on like this until the patient has regained
consciousness, or until a doctor has ascertained his death.
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2.2 Safety Rules

2.2.1 General Rules

• Before carrying out any installation, turn–up & commissioning, operation and maintenance
operations carefully read the relevant Handbook and chapters.

• Observe safety rules

– When equipment is operating nobody is allowed to have access inside on the equipment
parts which are protected with Cover Plate Shields removable with tools

– In case of absolute need to have access inside, on the equipment parts when it is operating
this is allowed exclusively to service personnel, where for Service Personnel or Technical
assistance is meant :

”personnel which has adequate Technical Knowledge and experience necessary to be
aware of the danger that he might find in carrying out an operation and of the necessary
measurements to reduce danger to minimum for him and for others”.

The Service Personnel can only replace the faulty units with spare parts.
The Service Personnel is not allowed to repair: hence the access to the parts no specified
is not permitted.

The keys and/or the tools used to open doors, hinged covers to remove parts which give
access to compartments in which are present high dangerous voltages must belong
exclusively to the service personnel.

– For the eventual cleaning of the external parts of the equipment, absolutely do not use any
inflammable substance or substances which in some way may alter the markings,
inscriptions ect.

– It is recommended to use a slightly wet cleaning cloth.

• The Safety Rules stated in the handbook describe the operations and/or precautions to observe
to safeguard service personnel during the working phases and to guarantee equipment safety,
i.e., not exposing persons, animals, things to the risk of being injured/damaged.

• Whenever the safety protection features have been impaired, REMOVE POWER.
To cut off power proceed to switch off the power supply units as well as cut off power station
upstream (rack or station distribution frame).

• The safety rules described at the beginning of the handbook are distinguished by the following
symbol and statement:

SAFETY RULES
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2.2.2 Labels Indicating Danger, Forbiddance, Command

It is of utmost importance to follow the instructions printed on the labels affixed to the units and assemblies.

The labels are fully compliant with International Norms ISO 3846–1984. The symbols or statements are

enclosed in geometric shapes: ISO 3864–1984.

CONTAINS A SYMBOL STATEMENT
INDICATES FORBIDDANCE (WHITE BACKGROUND
WHIT RED RIM–BLACK SYMBOL OR STATEMENT)
IT IS A COMMAND (BLUE BACKGROUND–WHITE
SYMBOL OR STATEMENT).

CONTAINS A SYMBOL
INDICATES WARNING OR DANGER (YELLOW
BACKGROUND–BLACK SYMBOL AND RIM)

CONTAINS A STATEMENT PROVIDING INFORMATION
OR INSTRUCTION.
(YELLOW BACKGROUND–BLACK STATEMENT AND RIM)

The labels have been affixed to indicate a dangerous condition. They may contain any standard–known
symbol or any statement necessary to safeguard users and service personnel against the most common
ones, specifically:

• dangerous electrical voltages

• harmful optical signals

• risk of explosion

• moving mechanical parts

• heat–radiating mechanical parts

Pay attention to the information stated in the following, and proceed as instructed
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The symbols presented in para.2.2.3 through 2.2.7 are all the possible symbols that could be
present on Alcatel equipment, but are not all necessarily present on the equipment this
handbook refers to.

2.2.3 Dangerous Electrical Voltages

2.2.3.1 Labelling

The following warning label is affixed next to dangerous voltages (>42.4 Vp; >60 Vdc).

If it is a Class 1 equipment connected to mains, then the label associated to it will state that the equipment
will have to be grounded before connecting it to the power supply voltage, e.g.:

WARNING !
Ground protect the equipment before
connecting it to mains
Make sure that power has been cut off
before disconnecting ground protec-
tion.

2.2.3.2 Electrical safety: general rules

DANGER! Possibility of personal injury: carefully observe the specific
procedures for installation / turn–up and commissioning / maintenance of equipment parts where a.c. or
d.c. power is present, described in the relevant installation / turn–up and commissioning / maintenance
documents and the following general rules:

a) Personal injury can be caused by –48 V dc (or by 220 V ac if envisaged in the equipment). Avoid
touching powered terminals with any exposed part of your body.

b) Short circuiting, low-voltage, low-impedance, dc circuits can cause severe arcing that can result in
burns and/or eye damage. Remove rings, watches, and other metal jewelry before working with
primary circuits. Exercise caution to avoid shorting power input terminals.
1AA 00014 0004 (9007) A4 – ALICE 04.10

2.2.3.3 Electrical safety: equipment specific data

Refer to para.5.1.2 on page 600.

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2.2.4 Harmful Optical Signals

2.2.4.1 Labelling

If the assembly or unit is fitted with a LASER, the labels must comply with the IEC 60825–1 and –2

International Norms.

The symbol indicates the presence of a LASER beam. Danger level is stated within a rectangular label:

If the LASER is a Hazard Level 1, 1M product, the label depicting the symbol within a triangle is not
compulsory.

If the LASER is a Hazard Level 3A product, the label depicting the symbol within a triangle is compulsory.

NOTE: the equipment may be provided with labels of a type other than the illustrated one
(reason: previous standard).

The rectangular shaped label bears all the information needed, i.e.:

• LASER class
• Power emitted
• Wave length
• Ref. Norm
• Precautionary measures taken depend on LASER class
• Indications given on openings, panels and safety interlockers
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2.2.4.2 Optical safety: general rules

On handling optical equipments or units or cables always check that laser labels are properly affixed and
that the system complies with applicable optical standards.

DANGER! Possibility of eyes damage: invisible infrared radiations emitted by
the fiber optic transmitters can cause eyes damages. Carefully observe the specific procedures for
installation / turn–up and commissioning / maintenance of units containing laser devices or cables
transporting optical signals, described in the relevant installation / turn–up and commissioning /
maintenance documents and the following general rules:

a) Laser radiation is not visible by the naked eye or with laser safety glasses. Although it cannot be seen,
laser radiation may be present.

b) Never look directly into an unterminated fiber optic connector or into a broken optical fiber cable,
unless it is absolutely known that no laser radiation is present.

c) Never look at an optical fiber splice, cable or connector, unless it is absolutely known that no laser
radiation is present.

d) All optical connectors, terminating either fibers and transmitters/receivers, are provided with
protective covers that must always be used, as soon as possible, when any optical link is
disconnected for installation/test/maintenance purposes or whatever operation.

e) Never look directly into an unterminated fiber optic connector or into a broken optical fiber cable by
means of magnifiers/microscopes, unless it is absolutely known that no laser radiation is present. A
magnifier/microscope greatly increases the damage hazard to the eyes.

f) Never point an unterminated optical fiber splice, cable or connector to other persons, unless it is
absolutely known that no laser radiation is present.

g) Always remove electrical power from near and far optical transmitters before disconnecting optical
links between the transmitter and the receiver.

h) Wearing of laser safety goggles or eyes shields is recommended for every person working on optical
devices, whenever the above listed rules cannot be followed.

2.2.4.3 Optical safety: equipment specific data

Refer to paragraph 5.1.1 on page 595 .
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2.2.5 Risks of Explosions

2.2.5.1 Labelling and safety instructions

This risk is present when batteries are used, and it is signalled by the following label:

Therefore, slits or apertures are made to let air circulate freely and allow dangerous gasses to downflow
(battery–emitted hydrogen). A 417–IEC–5641 Norm. compliant label is affixed next to it indicating that the
openings must not be covered up.

2.2.6 Moving Mechanical Parts

The following warning label is affixed next to fans or other moving mechanical parts:

Before carrying out any maintenance operation see that all the moving mechanical parts have been
stopped.
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2.2.7 Heat–radiating Mechanical Parts

The presence of heat–radiating mechanical parts is indicated by the following warning label in compliancy
with IEC 417 Norm, Fig.5041:

As stated by IEC 950 Norm., para.1.4.7 mechanical parts which carry the above pictured label and that
could inadvertently be touched, have a temperature T established by the following formula:

(T–Tamb) (DTmax + 25° – Tmra)
where:

T Temperature of the mechanical part measured at ambient temperature Tamb.

Tamb Ambient temperature during the test

DTmax Value defined by IEC 60950 Norm, Table 16 part 2a, para.5.1, and specified in
the table below.

Tmra The maximum room ambient temperature permitted by the equipment
specification or 25°C, whichever is greater.

Table 11. IEC 950 –Table 16: Overtemperature limits, Part 2

Maximum overtemperature (°C )
Operator–accessible parts
Glass, Plastic,
Metal
porcelain rubber

Handle knob, ect., held or touched
35 45 60
for short periods

Handles, knobs, ect., regularly held 30 40 50

Outer surface of the equipment that
45 55 70
can be touched

Inner surface of the equipment that
45 55 70
can be touched

DANGER! Possibility of personal injury: carefully observe the specific
procedures for installation / turn–up and commissioning / maintenance of equipment parts where
heat–radiating mechanical parts are present, described in the relevant installation / turn–up and
commissioning / maintenance documents and the following general rule:
1AA 00014 0004 (9007) A4 – ALICE 04.10

a) Personal injury can be caused by heat. Avoid touching powered terminals with any exposed part of
your body.

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2.2.8 Specific safety rules in this handbook

• The safety rules are specified in the following chapters:

– Chapter 6 paragraph 6.1 on page 665

– Chapter 6 paragraph 6.5.2.1 on page 669

– Chapter 6 paragraph 6.6.1 on page 670
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3 OTHER NORMS AND LABELS

3.1 Electromagnetic Compatibility

The equipment’s EMC norms depend on the type of installation being carried out (cable termination,
grounding etc.,) and on the operating conditions (equipment, setting options of the electrical/electronic
units, presence of dummy covers, etc.).

• Before starting any installation, turn–up commissioning, operation and maintenance work
refer to the relevant Handbook and chapters.

• The norms set down to guarantee EMC compatibility, are distinguished inside this handbook
by the symbol and term:

ATTENTION EMC NORMS.

3.1.1 General Norms – Installation

• All connections (towards the external source of the equipment) made with shielded cables use
only cables and connectors suggested in this technical handbook or in the relevant Plant
Documentation, or those specified in the Customer’s”Installation Norms.” (or similar
documents)

• Shielded cables must be suitably terminated

• Install filters outside the equipment as required

• Ground connect the equipment utilizing a conductor with proper dia. and impedance

• Mount shields (if utilized), previously positioned during the installation phase, but not before
having cleaned and degreased it.

• Before inserting the shielded unit proceed to clean and degrease all peripheral surfaces
(contact springs and connection points, etc.)

• Screw fasten the units to the subrack.

• To correctly install EMC compatible equipment follow the instructions given.
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3.1.2 General Norms – Turn–up Commissioning, Operation

• Preset the electrical units as required to guarantee EMC compatibility

•

Check that the equipment is operating with all the shields properly positioned (dummy covers,

ESD connector protections, etc.)

• To properly use EMC compatible equipment observe the information given

3.1.3 General Norms – Maintenance

• Before inserting the shielded unit, which will replace the faulty or modified unit, proceed to clean
and degrease all peripheral surfaces (contact springs and connection points, etc.)

• Clean the dummy covers of the spare units as well.

• Screw fasten the units to the subrack.
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3.2 Electrostatic Dischargers (ESD)

Before removing the ESD protections from the monitors, connectors etc., observe the precautionary
measures stated. Make sure that the ESD protections have been replaced and after having terminated

the maintenance and monitoring operations.

Most electronic devices are sensitive to electrostatic dischargers, to this concern the following warning
labels have been affixed:

Observe the precautionary measures stated when having to touch the electronic parts during the
installation/maintenance phases.

Workers are supplied with antistatic protection devices consisting of:

ELASTICIZED BAND

COILED CORD

• an elasticized band worn around the wrist

• a coiled cord connected to the elasticized band and to the stud on the subrack.
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3.3 Suggestions, notes and cautions

Suggestions and special notes are marked by the following symbol:

Suggestion or note....

Cautions to avoid possible equipment damage are marked by the following symbol:

TITLE...

(caution to avoid equipment damage)
statement....

3.4 Labels affixed to the Equipment

This chapter indicates the positions and the information contained on the identification and serial labels
affixed to the equipment.

Figure 1. thru’ Figure 7. illustrate the most common positions of the labels on the units, modules and
subracks.

Figure 8. thru’ Figure 13. illustrate the information (e.g., identification and serial No.) printed on the
labels.

The table below relates the ref. numbers stated on the figures to the labels used.

Labelling depicted hereafter is for indicative purposes and could be changed without any notice.

Table 12. Label references

Ref. No. Name of Label

1 label specifying item not on catalogue (P/N. and serial number)

2 label specifying item on catalogue (P/N. and serial number)
Refer to Figure 9. on page 48

3 item identification label – item on catalog

4 label identifying the equipment

5 label identifying compliancy with CE and WEEE Directives.
Refer to Figure 12. and Figure 13. on page 50

On contract basis, customized labels can be affixed to the equipment.
Standard labels can be affixed to any position on the equipment, as required by the Customer.
However, for each of the above are applied the rules defined by each individual Customer.
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4

03
Figure 1. Subrack label
2

ABCD

NOTE : The above reference numbers are detailed on Table 12. on page 40

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5

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ABC

2


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42 / 706

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NB.1
2

NB.1 = The label is present on the support side
ABC


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ABC

xxxxxx
xxxxxx
xxxxxxxxx
2


Figure 4. Labels on units with standard cover plate

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ABC

Figure 5. Modules label

706
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NB.1
1

ABC

NB.1 = The label is present on the p.c.s. component side


Figure 6. Internal label for Printed Board Assembly
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NB.1
ABC

1

NB. 1 = The label is present on p.c.s. components side or rear side on the empty spaces.

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Figure 7. Back panels internal label

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FACTORY P/N + CS

FACTORY SERIAL NUMBER

SERIAL NUMBER BAR CODE
(format 128; Module = 0,166; EN 799; Subset B/C)

Figure 8. Label specifying item not on catalogue (P/N. and serial number)

ANV ITEM PART NUMBER + space + ICS
ALCATEL FACTORY PART
ANV ITEM PART NUMBER + ICS BAR CODE NUMBER + SPACE + CS
(format ALFA 39 (+ * start, stop); Module = 0,166; Ratio = 2)

ACRONYM

SERIAL NUMBER BAR CODE
SERIAL NUMBER (format ALFA 39 (+ * start, stop); Module = 0,166; Ratio = 2)

Figure 9. Label specifying item on catalogue (P/N. and serial number)
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FREQUENCY ACRONYM

(Optional)

ANV ITEM PART NUMBER

Figure 10. Item identification labels – item on catalog

EQUIPMENT NAME

Figure 11. Label identifying the equipment (example)
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equipment.
Figure 12. CE label

Figure 13. WEEE label

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4 LIST OF ABBREVIATIONS

Table 13. List of Abbreviations

ABBREVIATION MEANING

ABIL Enabling

ABN Abnormal

ADM Add/Drop Multiplexer

AIS Alarm indication Signal

ALS Automatic Laser Shutdown

APD Avalanche Photodiode

APS Automatic Protection Switching

AND Alarm on both station batteries

ANSI American National Standards International

ASIC Application Specific Integrated Circuit

ATM Asynchronous Transfer Module

ATTD Attended (alarm storing)

AU Administrative Unit

AUG Administrative Unit Group

AUOH AU Pointer

AUX Auxiliary

AU4 Administrative unit – level 4

BATT Battery

BER Bit Error Rate

BIP Bit Interleaved Parity

BNC Bayonet Not Coupling

C Storing command

CE European Conformity

CO Central Office

CPE Customer premises equipment
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CT Craft Terminal

CMI Code Mark Inversion

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COAX Coaxial

CPI Incoming parallel contacts

CPO Outgoing parallel contacts

Central Processing Unit (referred to Controller equipment unit
CPU
or Microprocessor)

C12/C3/C4 1st, 3rd and 4th level container

DC Direct Current

DCC Data Communication Channel

DCE Data Circuit Terminating Equipment

DCU Optical Compensation Device

DPLL Digital Phase Locked Loop

DTE Data Terminal Equipment

EBU European Broadcasting Union

EC Equipment Controller

ECC Embedded Control Channel

ECMA Standardizing information and communication system
(Formerly ”European Computer Manufacturers Association”).

ECT Equipment Craft Terminal

EMC Electromagnetic compatibility

EMI Electromagnetic interference

EOW Engineering Order Wire

EPS Equipment Protection Switching

ESD Electrostatic discharges

ETSI European Telecommunication Standards Institute

E2PROM Electrically erasable programmable read only memory

F Interface F (for Craft Terminal) or Fuse

FEBE Far End Block Error

FEPROM Flesh Electrically erasable programmable read only memory

FERF Far End Receive Failure
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FPGA Field Programmable Gate Array

GA Gate Array

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GND Ground

HDBK Handbook

HDB3 High Density Bipolar Code

HIGHREFL High Optical reflections

HOA High Order Adaptation

HOI High Order Interface

HPC High order Path Connection

HPT Higher Order Path Termination

HPOM High order Path Overhead Monitoring

HSUT High order Supervisory Unequipped Termination

HW Hardware

ICS Item Change Status

ID Identification signals

IEC International Electrotechnical Committee

IEEE Institute of Electrical and Electronic Engineering

IN Input

IND Indicative alarm

INT Internal Local Alarms

IP Internet Protocol

ISO International Organism for standardization

International Telecommunication Union–Telecommunication
ITU–T (*)
Sector

JE1 Joint Engineering

LAN Local Area Network

LDSSHUT Command for ALS

LED Light emitting diode

LOF Loss of alignment

LOI Low Order Interface

LOM Loss Of Multiframe
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LOP Loss Of Pointer

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LOS Loss of signal

LPA Lower order path adaption

LPC Lower order path connection

LPOM Lower Order Path Monitoring

Lower order path termination or Loopback equipment side
LPT
(local)

LSUT Lower order Supervisory Unequipped Termination

M Tagblock or Alarm storing

MCF Message Communication Function

MLM Multi Longitudinal mode

MSA Multiplex section adaptation

MSOH Multiplex Section Overhead

MSP Multiplex section protection

MST Multiplex section termination

NRZ No return to zero

NURG Not urgent alarm

OH–BUS Dedicated housekeeping stream

OMSN Optinex MultiService Node

OOF Out Of Frame

OR Logic sum/Loss of only one station battery

OS Operating system

OUT Output

P/S Parallel/Serial converter

PC Personal Computer

PDH Plesiochronous Digital Hierarchy

PFAIL Power supply failure

PI Physical interface

PJE Pointer Justification Event

PPI Plesiochronous Physical interface
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POH Path Overhead

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PMMF Physical Machine Management Function

PPS Path Protection Switching

PRBS Pseudo Random Binary Signal

PR_EA Packet Ring Edge Aggregator

PWALM Power supply alarm

PWANDOR ANDOR/3 failure

TMN Interface with B2 protocol. Interface towards plesiochro-
Q2/QB2
nous equipment

Q3/QB3 TMN Interface with B3 protocol. Interface towards TMN

R Reset command /General alarm

RAI Remote Alarm Indication

RECC Recommendation

RAM Random Access Memory

RDI Remote Defect Indication

REI Remote Error Indication

RCK Received clock

REF Reference

REL Release

RIBUS Remote Inventory BUS

RMS Root Mean Square

Not urgent Alarm command. Lights up the relative rack red
RNURG
LED

RSOH Regenerator Section Overhead

RST Regenerator Section Termination

RURG Urgent Alarm command. Lights up the relative rack red LED

Rx Reception

SC Shelf Controller

SDH Synchronous Digital Hierarchy

SETG Synchronous Equipment Timing Generation function
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SLM Single Longitudinal Mode

SM Single Mode/Synchronous Mux

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SNCP/I (** ) Subnetwork Connection Protection Inherent

SOH Section Overhead

S/P Serial/Parallel Converter

SPI Synchronous Physical Interface

SSF Server Signal Fail

SQ Squelch

STM–0/STM–1 Synchronous Transport Module, levels 0 etc.

SW Software

TANC Remote alarm due to failure of all power supply units

TD Layout drawing

TIM Trace Identifier Mismatch

TMN Telecommunication Management Network

TOR Remote alarm indicating loss of one of the station batteries

TORC Remote alarm due to a faulty/missing power supply unit

TSD Trail Signal Degrade

TSF Trail Signal Fail

TTF Transport Terminal Function

TUG2/3 Tributary unit group, level 2,3

TUOH Tributary Unit Overhead

TUP/UP Equipment Controller remote alarm

TU12/TU3 Tributary unit level 12, 3

TX Transmission

URG Urgent

VCXO/VCO Voltage controlled oscillator

VC12/VC3/VC4 Virtual Container, levels 12,3,4

VMMF Virtual Machine Management Function

WAN Wide Access Network

NOTES –
(*) Owing to change of name all documents issued by the two ITU committees (CCIR ND
name,
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CCITT) in 1992 (and in some cases even before then) are classified as ITU–R and ITU–T,
respectively
respectively.
(**) Substitutes PPS

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5 GENERAL ON ALCATEL CUSTOMER DOCUMENTATION

5.1 Products, product-releases, versions and Customer Documentation

A ”product” is defined by the network hierarchical level where it can be inserted and by the whole of
performance and services for which it is meant.
A ”product” evolves through successive ”product-releases” which are the real products marketed for
their delivery at a certain ”product-release” availability date.

So, a ”product–release” defines a set of hardware components and a software package which, as a whole,
identify the possible network applications and the equipment performance which the specific
”product-release” has been designed, engineered and marketed for.

In some cases a ”product-release” has further development steps, named ”versions”, that are born to
improve or add some performance (mainly software) with respect to the previous version, or for bug fixing
purposes.

A ”product-release” has its own standard Customer Documentation, composed by one or more
handbooks.

A new ”version” of a ”product-release” may or may not produce a change in the status of the Customer
Documentation set, as described in para. 5.4 on page 58.

5.2 Handbook supply to Customers

Handbooks are not automatically delivered together with the equipment they refer to.
The number of handbooks per type to be supplied must be decided at contract level.

5.3 Aims of standard Customer Documentation

Standard Customer Documentation, referred to hereafter, must be always meant as plant-independent.
Plant-dependent documentation, if envisaged by the contract, is subjected to commercial criteria as far
as contents, formats and supply conditions are concerned (plant-dependent documentation is not
described here).

Standard hardware and software documentation is meant to give the Customer personnel the possibility
and the information necessary for installing, commissioning, operating and maintaining the equipment
according to Alcatel–Telecom Laboratory design choices.
In particular: the contents of the handbooks associated to the software applications focus on the
explanation of the man-machine interface and of the operating procedures allowed by it; maintenance is
described down to faulty PCB location and replacement.

Consequently, no supply to the Customers of design documentation (like PCB hardware design and
production documents and files, software source programs, programming tools, etc.) is envisaged.

The handbooks concerning hardware (usually the ”Technical Handbook”) and software (usually the
”Operator’s Handbook”) are kept separate in that any product changes do not necessarily concern their
contents.
For example, only the Technical Handbook might be revised because of hardware configuration
changes (e.g., replacing a unit with one having different P/N but the same function).
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On the other hand, the Operator’s Handbook is updated because of a new software version but which
does not concern the Technical Handbook as long as it does not imply hardware modifications.
However, both types of handbooks can be updated to improve contents, correct mistakes, etc..

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5.4 Handbook Updating

The handbooks associated to the ”product–release” are listed in para.1.3 on page 18.

Each handbook is identified by:

– the name of the ”product-release” (and ”version” when the handbook is applicable to the versions
starting from it, but not to the previous ones),
– the handbook name,
– the handbook P/N,
– the handbook edition (usually first edition=01),
– the handbook issue date. The date on the handbook does not refer to the date of print but to the date
on which the handbook source file has been completed and released for the production.

5.4.1 Changes introduced in the same product-release (same handbook P/N)

The edition and date of issue might change on future handbook versions for the following reasons:

– only the date changes (pointed out in the Table of Contents) when modifications are made to the
editorial system not changing the technical contents of the handbook.

– the edition, hence the date, is changed because modifications made concern technical contents. In
this case:

• the chapters modified with respect to the previous edition are listed in Table 10. on page 25.;
• in affected chapters, revision bars on the left of the page indicate modifications in text and
drawings.

Changes concerning the technical contents of the handbook cause the edition number increase (e.g. from
Ed.01 to Ed.02). Slight changes (e.g. for corrections) maintain the same edition but with the addition of
a version character (e.g. from Ed.02 to Ed.02A). Version character can be used for draft or proposal
editions.

NOTES FOR HANDBOOKS RELEVANT TO SOFTWARE APPLICATIONS

Handbooks relevant to software applications (typically the Operator’s Handbooks) are not
modified unless the new software ”version” distributed to Customers implies man–machine
interface changes or in case of slight modifications not affecting the understanding of the
explained procedures.

Moreover, should the screen prints included in the handbook contain the product-release’s
”version” marking, they are not replaced in the handbooks related to a subsequent version, if
the screen contents are unchanged.

5.4.1.1 Supplying updated handbooks to Customers

Supplying updated handbooks to Customers who have already received previous issues is submitted to
commercial criteria.
By updated handbook delivery it is meant the supply of a complete copy of the handbook new issue
(supplying errata–corrige sheets is not envisaged).
1AA 00014 0004 (9007) A4 – ALICE 04.10

5.4.2 Changes due to new product version

A new product version changes the handbook P/N and the edition starts from 01.
In this case the modified parts of the handbook are not listed.

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5.5 Customer documentation on CD–ROM

In the following by ’CD–ROM’ it is meant ’Customer Documentation on CD–ROM’

5.5.1 Contents, creation and production of a CD–ROM

In most cases, a CD–ROM contains in read–only eletronic format the documentation of one
product–release(–version) and for a certain language.
In some other cases, the same CD–ROM can contain the documentation of different
product–release(–version)s for a certain language.

As a general rule:

– CD–ROMs for Network Management products do not contain:

• the Installation Guides

• the documentation of system optional features that Customers could not buy from Alcatel
together with the main applicative SW.

– CD–ROMs for Network Elements products do not contain:

• the documentation of system optional features (e.g. System Installation Handbooks related to
racks that Customers could not buy from Alcatel together with the main equipment).

A CD–ROM is obtained collecting various handbooks and documents in .pdf format. Bookmarks and
hyperlinks make the navigation easier. No additional information is added to each handbook, so that the
documentation present in the CD–ROMs is exactly the same the Customer would receive on paper.

The files processed in this way are added to files/images for managing purpose and a master CD–ROM
is recorded.

Suitable checks are made in order to have a virus–free product.

After a complete functional check, the CD–ROM image is electronically transferred to the archive of the
Production Department, so that the CD–ROM can be produced and delivered to Customers.
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5.5.2 Use of the CD–ROM

The CD–ROM can be used both in PC and Unix WS environments.

The CD–ROM starts automatically with autorun and hyperlinks from the opened “Index” document permit

to visualize the .pdf handbooks
Other hyperlinks permit to get, from the Technical handbooks, the specific .pdf setting documents.

In order to open the .pdf documents Adobe Acrobat Reader Version 4.0 (minimum) must have been
installed on the platform.
The CD–ROM doesn’t contain the Adobe Acrobat Reader program. The Customer is in charge of getting
and installing it.
ReadMe info is present on the CD–ROM to this purpose.

Then the Customer is allowed to read the handbooks on the PC/WS screen, using the navigation and
zooming tools included in the tool, and to print selected parts of the documentation through a local printer.

5.5.3 CD–ROM identification

Each CD–ROM is identified:

1) by the following external identifiers, that are printed on the CD–ROM upper surface:
– the name of the ”product–release(s)” (and ”version” if applicable)
– a writing indicating the language(s),
– the CD–ROM P/N (Factory P/N and ANV P/N),
– the CD–ROM edition (usually first edition=01)

2) and, internally, by the list of the source handbooks and documents (P/Ns and editions) by whose
collection and processing the CD–ROM itself has been created.

5.5.4 CD–ROM updating

The list of source handbook/document P/Ns–editions indicated in previous para. 5.5.3 point 2 ) , in
association with the CD–ROM’s own P/N–edition, is also loaded in the Alcatel–Information–System as a
structured list.
Whenever a new edition of any of such handbooks/documents is released in the Alcatel archive system,
a check in the Alcatel–Information–System is made to identify the list of CD–ROMs that must be updated
to include the new editions of these handbooks/documents.
This causes the planning and creation of a new edition of the CD–ROM.
Updating of CD–ROMs always follows, with a certain delay, the updating of the single handbooks
composing the collection.
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1 GENERAL

1.1 Introduction to the equipment

The Alcatel 1660SM is a synchronous Optical Multi Service Node (OMSN); it complies with the
Synchronous Digital Hierarchy (SDH) defined in ITU–T Recommendation G.707.

The integration of SDH and WDM technology represents the chance to enhance the network capacity with
no impact on the starting physical means (i.e. fibers): the presence of a wavelength grid allows the user to
multiply the capacity with limited costs, if compared to the cable laying; on the other side the SDH network
(specifically configured with OMSN’s equipment) represents the most flexible and reliable way to handle
different types of clients, both TDM and data.
The availability of Coarse WDM technology in the 1660SM matches a second driver for network
integration, i.e. ’cost reduction’.
CWDM optical devices represent a cost effective solution, if compared to the Dense WDM technology and
fit most of the network scenarios in area ’metro’(refer to Figure 14. on page 67).
1660SM, makes available up to 8 channels for traffic transport according the ITU –T G.694.2 wavelength
grid: 1470 – 1490 – 1510 – 1530 – 1550 – 1570 – 1590 – 1610 nm.
The 1660SM with CWDM technology fulfits both ’ring’ and ’linear’ applications (refer to paragraph 1.2.3
on page 75 and paragraph 1.2.4 on page 79).

Compatible with existing plesiochronous systems as well as with the installed SDH networks, the 1660SM
is a transmission equipment operating at 155 (STM–1), 622(STM–4), 2488(STM–16) and 9953 (STM–64)
Mbit/s bit rates.

It can be configured as a Multiple Line Terminal Multiplexers or as a Multiple Add/Drop Multiplexers
or mini cross connect for applications in linear links, network rings and meshed networks.

A wide range of ports can be added/dropped/connected by the equipment according to the traffic type to be
managed:

– 2.048 Mbit/s signal (with asynchronous mapping)
Processing of unstructured and structured (ISDN–PRA) 2Mb/s signal.

– 34/45 Mbit/s

– STM–1 Electrical/Optical

– STM–4 Optical Signal



– OC3 Electrical/Optical

– A mixing of SDH and Data Services is possible by inserting the 4xANY board in the 1660SM
subrack.
It allows to multiplex in the time domain up to 4 client signals into one single 2.5Gb/s optical channel
(server signal). Server STM–16 signal is connected to SDH matrix through 1660SM backpanel.
Multiplexing scheme delivers a fully compliant SDH frame. The signal can hence be directly
connected to a SDH ADM/DXC without requiring prior de–concentration.

The clients signals can be independently handled among the following types:
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• Fast Ethernet
• FDDI (125Mbps)

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• ESCON (200Mbps)
• Digital Video (270Mbps)
• Fiber Channel (1.0625Gbps)
• FICON (1.0625Gbps)

• Gigabit Ethernet (1.25Gbps)

– ISA (Integrated Service Adapter)

Alcatel’s Integrated Service Adapter (ISA) series of plug–in cards are specially designed to enhance
the optical transport network by adding data–aware features that are easy to introduce, allowing
carriers to efficiently and cost–effectively aggregate, switch and transport the expanding amount of
data services in their metropolitan network.
1660SM equipped with ISA plug–in cards give telecom operators a new generation modular platform
for multi–service SDH transport and further strengthen Alcatel’s leading position in the supply of
optical multi–technology transmission networks.
The ISA system is modular and the plug–ins can be chosen according to the specific application the
1660SM needs to manage; the following ISA boards are available:

• ISA–ATM (Asynchronous Transfer Module); the ATM cells, mapped into SDH G707 payloads
(VC4, VC4–C, VC3, VC12) or PDH G704/G832/G804 frames (E1, E3), can be processed,
routed and switched, using the dedicated unit.
Such functionalities are particularly useful in urban and local access ring to consolidate data
traffic from different users onto the same SDH Virtual Containers, thereby optimizing the
utilization of transmission bandwidth (see Figure 15. on page 68).

• ISA–PR_EA (Packet Ring Edge Aggregator) also called MPLS (Multi Protocol Label
Switching); the packets data services of level 3 of the protocol stack, transported over Ethernet,
are routed into the SDH network by means of MPLS labels.
Topology can be either meshed or ring networks. It is expecially made as interface aggregator.

• ISA–PR (Packet Ring); the packets data services of level 3 of the protocol stack, transported
over Ethernet, are routed into the SDH network by means of MPLS labels.
PR is for ring network topology, with dedicated data protector scheme.
The role of PR functionality is to provide a shared carrier–class Ethernet Packet Ring either
embedded physically into the SDH infrastructure, in which case the embedded Packet Ring is
provided in a flexible manner over SDH Virtual Containers (VC–4–Xv), or alternatively the PR
can be connected directly to independent fibers to create a Packet Ring over single or dual
STM4.
PR Deployment Scenario is presented on Figure 16. on page 69.

• ISA–Ethernet: the ethernet MAC frames are accessed at 10/100BaseT format, and then
mapped into SDH G707 payloads (VC4, VC3, VC12); they can be transparently linked,
point–to–point, in the SDH network to allow LAN to LAN connections as depicted in the
example of Figure 17. on page 70.
If the customer has N sites to be interconnected, each Customer Box uses N–1 Point to Point
Ethernet interfaces.
Ethernet frames are mapped over a SDH VC using Generic Framing Procedure encapsulation.
As SDH Network is transparent, the customer Boxes see them as directly connected in a mesh.

• ISA–Gbit/s Ethernet: the ethernet signals are accessed at 1.25Gb/s over optical fiber medium,
and then mapped into SDH G707 payloads VC4; they can be transparently linked,
point–to–point, in the SDH network to allow LAN to LAN connections as depicted in the
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example of Figure 17. on page 70

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Ethernet frames are mapped over a SDH VC using Generic Framing Procedure encapsulation.
As SDH Network is transparent, the customer Boxes see them as directly connected in a mesh.

• ISA–ES (Ethernet Switching).

ISA–ES series modules provide ETH 10/100/1000 interfaces connectivity for LAN based clients
premises inside the metro area.
Beyond mapping ETH flows onto the SDH metro network by means of standard mechanisms
(as specified in ITU G.7071, ITU G.7042 and ITU G.707) the ISA–ES series cards introduce wire
speed classifying, policing and scheduling capability empowered by carrier class Ethernet
switching engine.
Per customer traffic flow management with low bandwidth granularity, segregation and QoS are
just few of the value added arguments that these series of modules offer to the carrier operators
at a competitive price.

When 1660SM is used as Add/Drop Multiplexer, mixed STM–N ports can be used in the same
configuration thus allowing to manage in the same equipment and at the same time STM–1 , STM–4,
STM–16 and STM–64 rings (multiring).

A large variety of STM–N optical plug–in modules operating at 1300 nm and 1550 nm is available to cover
short and long haul systems. Dedicated optical interfaces are also available to inter–work with boosters
and optical pre–amplifiers at all STM–N levels.

1660SM also features “coloured” STM–16 interfaces for direct interworking with WDM equipment without
intermediate wavelength adapters.

All the electrical units (traffic ports) and the common units can be optionally EPS protected with different
modularity (1+1; 1+N with 1 v N v15 as far as regards the traffic ports ):

– The EPS protection of the High Speed electrical traffic units ( 34 Mbit/s, 45 Mbit/s and155 Mbit/s) is
implemented using a dedicated access module.

– The EPS protection of the ATM/PR_EA units is implemented.

– The EPS protection of the ISA–ES16 units is implemented.

According to the network topology, network protection mechanisms are provided:

– Single ended and dual ended MSP (Multiplex Section Protection) can be implemented at any STM–N
level.

– MS–SPRing (Multiple Section Shared Protection Ring) on two fibers bidirectional rings can be
implemented at STM–16 level.

A centralized matrix implements the cross–connect function and can be protected in 1+1 EPS scheme.
The maximum matrix cross connection capability can be 256x256 STM–1 equivalent port at VC–12 /
VC–3 level + 384x384 equivalent port at VC–4 level.

A wide auxiliary capacity, in accordance with SDH standards, is available for embedded services. An
Engineering Order Wire channel, with DTMF signalling, can be accessed by a microtelephone for
maintenance facility.

The clock reference function, housed in the centralized unit (MATRIX), synchronizes the 1660SM and
provides generation and distribution of a synchronism clock. The distributed clock can be locked to an
1AA 00014 0004 (9007) A4 – ALICE 04.10

external 2MHz or 2Mbit/s source, to any STM–N or 2Mbit/s tributary signal.
The SSM (Synchronization Status Message) and priority algorithms are supported.

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The Equipment Controller function provides unit configuration and collects unit alarms, statuses and
performance monitoring data. A Local software download facility is available in order to update the
complete software of the control subsystem.

Traffic ports have no on–board processor and may be reused from one equipment to another or retrieve

from stocks with no worries about software version.

The system can be managed either by a Personal Computer through the F interface or by a Network
Management System through the Q interface.

Moreover, the 1660SM can work as a Mediation Device for Alcatel NE accessible through Q2/RQ2
interface. In this way, it can be possible to transport information about alarms and configurations of PDH
and/or Access Systems to/from a centralized TMN using the standard SDH DCC network.

A DC/DC converter, located on each board, guarantees the powering of the system. The distribution
of Power Supplies inherently guarantees protection.

Other functionalities :

• Bidirectional Transmission
For the Optinex 1660SM optical interface a bidirectional transmission on single fiber function
is implemented, using an external passive optical coupler.

• Remote Equipment Control
This function allows a centralized management system for small SDH networks, similar to that
offered by an OS.
That means that it is possible to perform management functionalities , from one of the NEs of
the network, toward the other NEs (up to 31), like configuration modification and remote
control.

• Dual OS
O.S. Spare is foreseen to protect the Main one.
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Link: up
to 100 Km

Metro Access Ring
PACKET
VC–4/3/12

Core
CWDM

CWDM

OMSN Metro G
OMSN 2.5/nx2.5G CWDM
network Metro VC–4/3/12
CWDM OMSN PACKET
2.5/nx2.5G CWDM
VC–4/3/12

PACKET
VC–4/3/12
network

CWDM
Metro Core PACKET
Ring/Mesh Metro Edge SDH@STM–16
CWDM Ring (up to 100–X Km)
1–N x STM–16

E1/DS1 1–N x STM–16
E3/DS3
10/100/GbE

E1/DS1

E3/DS3
STM–n/10GbE 10/100/GbE

E1/DS1
STM–n/10GbE
E3/DS3
E/FE
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 14. Example of SDH/DATA/CWDM integration in “metro area”

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ED
SDH Interfaces:
1640FOX TDM
ATM
PR_EA

03
1660SM
PDH Interfaces:
TDM
ATM

ÌÑ
ÑÑ
ÑÑ
PR_EA
Ethernet:

ÌÌÌÌ
ÌÌÌÌ
ÌÌÑÌ
1650SMC 10/100 Base T
Consolidated
bandwidth Full Duplex
1000 BASE –LX
1000 BASE –SX

ÓÔÑ
ÑÑ
ÓÔ
ÓÓ
Ó
SDH Network

ÌÌÌ
ÌÌÌ Ô
ÌÌÌ Ó
ÌÌÌ Ó Ñ
ÑÑ
ÑÓ
ÑÓ

ÓÔ
ÌÔ
ÌÔ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ

ÌÌÓÌ
ÌÌÓÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ Ñ
ÌÌÌÌ Ñ
ÌÌÌÌ

1650SMC
1640FOX 1640FOX

Bandwidth control:
– ATMM QoS

ATM
Switch

Figure 15. Example of ATM Transport management
Traffic engineering:

706
3AL 91669 AA AA
MPLS Routing
ATM switching
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ

1640FOX

68 / 706


Legend :

1660SM with ISA –PR
–

Ethernet/IP
Customer Switch/Router
Core
Hand –off of aggregated packet L3 Router
traffic to core network

1640FOX GbE

Overlay MPLS Packet Ring
created over VC –4–Xv
STM16 SDH Ring
Bandwidth

1650 Fe or
GbE
1640FOX

ISA –PR does not have to
1640FOX be installed in all ring
End –to–end Metro
nodes
Ethernet Service created
with QoS/SLA
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 16. ISA–PR Deployment Scenario

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
03
Ethernet frames
are mapped in SDH
VC–12. VC–3, VC–4 Site to Site Traffic is
mapped on a dedicated
SDH VC

SDH RING NETWORK

Figure 17. Ethernet service application

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Legenda:

3AL 91669 AA AA
SDH level
The LAN to LAN
Customer box:
protection board is present
either LAN Switch or Router
only at each
terminating node
1660SM
with LAN to LAN board

70 / 706

1.2 Insertion of the equipment into the network

The 1660SM equipment belongs to the Alcatel Optinex family product, compliant with the SDH
Synchronous Digital Hierarchy defined by the ITU–T Recs.

The equipment 1660SM can be utilized in local, regional and metropolitan networks configured for

standard plesiochronous or synchronous systems.
The product can be suitably employed on linear, ring and hub networks and on protected or unprotected
line links.

The equipment applications depends on the different types of networks available.

1.2.1 Configuration

• Terminal multiplexer (see Figure 18. ).
The NE is provided with an STM–N (with N=1÷64 ) a station interface (eventually stand–by too)
to be connected to a Digital Electronic Cross–Connect or to a higher hierarchical line system.

SDH PORT

PDH PORTS NE
SDH PORT
(SPARE)

Figure 18. Terminal multiplexer

• Add/Drop Multiplexer ( see Figure 19. )
The NE can be programmed to drop (insert) signals from (into) the STM–N (with N=1÷64 )
stream.
Part of the signal pass–through between the line sides, defined A and B in Figure 19. on page
71.

SDH PORT SDH PORT
Side A NE Side B
SDH PORT SDH PORT
(SPARE) (SPARE)

SDH, PDH PORTS

Figure 19. Add/Drop Multiplexer
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• ”HUB” STM–N (see Figure 20. )
The NE permits to drop/insert STM–N tributaries into a multiple stream and then branch them
off in HUB structures.

SDH PORT SDH PORT
NE
SDH PORT SDH PORT
(SPARE) (SPARE)

SDH PORT

Figure 20. ”HUB” STM–1

• Mixed Configuration

The NE can handle in the same node all the previously configuration thus performing a mixed
configuration.

1.2.2 Application

For each of the above configurations different network topologies may be used. The most important
network topologies are:

Point to Point

Linear

Ring and multiring topology

Meshed topology

• Point–to–point link (see Figure 21. )
In this case the NE can be connected to another multiplexer through the line

SDH PORT SDH PORT

PDH PORTS NE NE PDH PORTS

SDH PORT SDH PORT
SPARE SPARE

Figure 21. Point–to–point links
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• Linear Drop–insert (see Figure 22. )
The NE can be programmed to drop (insert) PDH and SDH ports from (into) the STM–N (with
N=1÷64 ) stream or terminate PDH ports

SDH PORT SDH PORT SDH PORT

NE NE NE NE
SPARE SPARE SPARE
PDH PORTS PDH PORTS

SDH AND PDH SDH AND PDH
PORTS PORTS

Figure 22. Linear drop–insert

• Ring structure (see Figure 23. )
The drop–insert function permits to realize ring structures.
The VC can be automatically rerouted if the optical splice breaks down or one of the equipment
nodes fails

SDH AND PDH
PORTS

NE
STM–4 STM–4

RING 1
NE NE
PORTS SDH AND PDH PORTS
PORTS

STM–4 STM–4

NE

STM–1 STM–1

PDH
PORTS
NE NE
PORTS PORTS
RING 2

STM–1 NE STM–1

SDH AND PDH
1AA 00014 0004 (9007) A4 – ALICE 04.10

PORTS

Figure 23. Ring structure

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• Meshed Topology (see Figure 24. on page 74)

The Meshed topology may be used in case of collection of traffic in peripheral nodes or
customer premises sites. 1+1 line protection may be used to protect against line failure and,

in some cases, node failure could be protected using dual hub topology too. For this type of

network topologies the mini digital cross connect system is very useful and SNCP/I is used.

PDH PORT

NE
SDH AND PDH
STM–N STM–N PORTS PDH PORT
STM–1 STM–1
NE RING NE NE
PDH PORT NE

STM–N STM–N
PDH PORT

NE

STM–N

SDH AND PDH
PORTS

STM–N NE
STM–N

STM–N

PDH PORT NE STM–N
NE RING NE PDH PORT

SDH AND PDH
PORTS
STM–N
STM–N NE

PDH PORT

Figure 24. Meshed topology
1AA 00014 0004 (9007) A4 – ALICE 04.10

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1.2.3 SDH / CWDM integration in “ring” network

NOTE: in this paragraph and in the following 1.2.4 on page 79 , 1660SM equipped with Coarse WDM
units will be called 1660OADM.

• COADM 1 (2) channel;

• MUX/DEMUX 8 channels.

The use of COADM unit for interfacing WDM ring, allows the operator to duplicate/triplicate the starting
network capacity based on a ’single optical channel’ provided by ’pure’ STM–N interfaces.

Figure 25. SDH/CWDM integration in “ring” with COADM units

According to the amount of traffic to be handled at a node of the ring, 1(2) channels (λx, λy) out of the 8
specified by ITU–T grid are added/dropped in order to be handled by 1660SM; the remaining channels
possibly not terminated, are by–passed, from one side to the opposite one of the node (W to E, E to W)
through a specific link (at WDM level) between COADM’s units.
1AA 00014 0004 (9007) A4 – ALICE 04.10

COADM unit is specifically devoted to application in a ’ring’ network (due to WDM pass–through link) and
requires the use of two separate units respectively for West side interfacing and East side interfacing.

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In Figure 25. the representation of a ’ring’ network using COADM as ring interface is provided; while in
Figure 26. the functional parts related to each node of the ring are detailed.

Figure 26. SDH/CWDM integration in “ring” with COADM unit: detailed view

In the showed example, ’added/dropped’ wavelengths ( λ1, λ2, ) are terminated by STM16 ’CWDM’
interfaces operating in compliance with the ITU–T grid. Traffic streams terminated are, then,
cross–connected at SDH level and made available to the relevant ’client’ interfaces
(SDH/PDH/MPLS/Ethernet).

The use of MUX/DEMUX unit for interfacing WDM ring, allows the operator to terminate the whole pool
of optical channels available. MUX/DEMUX unit is required when the traffic matrix is larger than the
capacity provided by COADM 1(2) channel/s.
The application in a ’ring’ network, requires the use of two MUX/DEMUX units respectively for West side
interfacing and East side interfacing.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Figure 27. SDH/CWDM integration in “ring” with MUX/DEMUX unit

Up to 8 channels may be added/dropped at a node of the ring, according to the amount of traffic to be
terminated; while wavelengths not terminated at a node, are by–passed, from one side to the opposite
one of the node (W to E, E to W) through a specific link (at channel level) between MUX/DEMUX units.

In Figure 27. the representation of a ’ring’ network using MUX/DEMUX as ring interfaces is provided.

In Figure 28. the functional parts related to each node of the ring are detailed.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Figure 28. SDH/CWDM integration in “ring” with MUX/DEMUX unit: detailed view

In the showed example, 4 wavelengths ( λ1, λ2, λ3, λ4, ) are ’added/dropped’ at a generic node, then
terminated by STM16 ’CWDM’ interfaces operating in compliance with the ITU–T grid. As for previous
COADM application, traffic streams terminated are cross–connected at SDH level and made available
to the relevant ’client’ interfaces (SDH/PDH/MPLS/Ethernet).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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1.2.4 SDH / CWDM integration in “linear” network

The use of 16660SM with “Coarse WDM units” in linear network is properly based on MUX/DEMUX unit
deployment.

As, already seen for ’ring’ application, the use of MUX/DEMUX allows the termination of 8 available
channels. Nevertheless, the use of COADMn unit may be considered for those network scenarios whose
traffic demand is satisfied by 1 or 2 wavelengths.

Figure 29. SDH/CWDM integration in “linear” network

Figure 29. shows a ’linear’ network application for 1660SM.

In Figure 30. a detailed vision of a node in this kind of network is also provided; wavelength multi/
demultiplexing is supposed to be performed by MUX/DEMUX unit.

Figure 30. SDH/CWDM integration in “linear” network (MUX/DEMUX): detailed view

In the showed example, the whole pool of 8 wavelengths is terminated at the end of the link by STM16
1AA 00014 0004 (9007) A4 – ALICE 04.10

’CWDM’ interfaces operating in compliance with the ITU–T grid: two shelves are considered in order to
allow the equipment of ’colored’ interfaces needed.

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In Figure 8, the possible use of an COADM unit for wavelength multi/demultiplexing is considered; for this
functionality, COADM ’pass–through’ link is not used.

Figure 31. SDH/CWDM integration in “linear” network (COADM unit): detailed view
1AA 00014 0004 (9007) A4 – ALICE 04.10

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1.2.5 Network protection

The relationship between the network application with their own protection and the configuration modes
is summed up in Table 14. on page 81.

Table 14. Network application versus configuration modes

Network Protection NE Configuration
Network application
Scheme TM ADM

Point to Point MSP

Linear MSP

Ring SNCP

Hub and Meshed MSP SNCP
1AA 00014 0004 (9007) A4 – ALICE 04.10

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03

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3AL 91669 AA AA
82 / 706

2 PHYSICAL CONFIGURATION

In all this document, three types of cards will be distinguished :

• access card : it is a board containing the signal physical interfaces ( electrical connectors)

• ports card : it is the board that performs the SDH elaboration of the signal

• module (electrical or optical) : It is a particular plug–in card ( of small dimensions ) that is
inserted on the front panel of some particular boards.

This Chapter illustrates the physical structure, layout and composition, coding and partition of the
Equipment and Fans subrack.

EQUIPMENT:

The Equipment Shelf front view is illustrated in Figure 32. on page 84 (“SR60M” subrack) and in
Figure 34. on page 85 (1660 subrack with fans).
1660SM is composed of one shelf containing 21 slots in the access area and 20 slots in the basic area.
The two areas are located on different “lines” inside the shelf.

The main part code and partition are listed in Table 15. on page 87.

The accessories codes and partition are listed in Table 16. on page 102.

For the relationship between access cards and port cards refer to paragraph 2.3 on page 110.

FANS SUBRACKS:

The Fans subracks front view is illustrated in Figure 33. on page 84.

The main part code and partition are listed in Table 17. on page 104.

NOTES:

The explanatory notes are reported in Table 18. on page 105.

UNITS FRONT VIEW:

For the units front view refer to para 2.4 on page 123.

N.B. Table 15. on page 87 contains the units of current equipment release. Units belonging to
previous equipment releases/versions (e.g. for configuration updating) are not here listed but
still supported, if compatible with the current one. (For eventual units belonging to previous
equipment releases/versions refer to the relative Technical Handbook).

N.B. The Personal Computer (Craft Terminal) utilized for Initial Turn–on and Maintenance operations
is not listed as an item of the equipment, but it can be supplied by Alcatel. See Operator’s
Handbook for PC hardware configuration.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
I
E
S
S
E

A
R
A
C
C
A

E
S

A
R
A
C
A
B

03
W = mm width
1
ACCESS LS W20

22
W20 PQ2/EQC

SLOT 0
2
ACCESS LS – HS W20
W35 MATRIXE A

23
TBUS

3

24
W20 PORT LS – HS W20
4
ACCESS LS – HS

SLOT 1
W20 PORT ENHANCED – HS W20
5
ACCESS LS – HS
2.1 Equipment front view

Left side
6

ACCESS LS – HS
W20

SLOT 4
PORT LS – HS W20
7

ACCESS LS – HS
W20

25 26 27 28
PORT ENHANCED – HS W20
8

ACCESS LS – HS
W20

2.1.2 19” Fans subrack front view (SRFAN)
ACCESS LS – HS
W20 PORT LS – HS
9 10

CONGI A W20
W20 PORT HS
11

SERVICE W30
W20 PORT LS SPARE – HS
2.1.1 1660SM Shelf “without fans” front view (SR60M)

W20 PORT LS – HS CONGI B W20


SLOT 2
W20 PORT ENHANCED – HS

W20 PORT ENHANCED – HS ACCESS LS – HS W20

Figure 33. 19” Fans subrack unit slots
W20 PORT LS – HS

SLOT 3
W20

706
W20 PORT ENHANCED – HS ACCESS LS – HS

3AL 91669 AA AA
Figure 32. 1660SM units positioning in “SR60M” subrack

Right side

SLOT 5
29 30 31 32 33 34 35 36 37 38 39

W20 PORT LS – HS
40

W35 TBUS MATRIXE B
W20
41

ACCESS LS W20
12 13 14 15 16 17 18 19 20 21

84 / 706

1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
I

F

E
S
E
S
E
S
S
E

A
R
A
N
A
A
R
A
C
A
B
A
R
A
C
C
A

03
1
W20 ACCESS LS

22
W20 PQ2/EQC

2
W20 ACCESS LS – HS

W = mm width
MATRIXE A

23
W35 TBUS 3

24
4

ACCESS LS – HS
5

ACCESS LS – HS
6

ACCESS LS – HS
7

ACCESS LS – HS
W20

25 26 27 28

F1
8

ACCESS LS – HS
2.1.3 1660SM Shelf “with fans” front view


F2
W20 PORT LS – HS
9 10

W20 CONGI A
W20 PORT HS
11

W30 SERVICE
W20 PORT LS SPARE – HS
W20 PORT LS – HS W20 CONGI B

PORT ENHANCED – HS W20 ACCESS LS – HS
W20
PORT ENHANCED – HS W20 ACCESS LS – HS
W20

FILTER
W20 PORT LS – HS
W20

706
PORT ENHANCED – HS ACCESS LS – HS

3AL 91669 AA AA
W20
29 30 31 32 33 34 35 36 37 38 39

PORT LS – HS

Figure 34. 1660SM units positioning in 1660 subrack with fans
W20
40

W35 TBUS MATRIXE B
W20
41

W20 ACCESS LS
12 13 14 15 16 17 18 19 20 21

85 / 706

2.2 Part list

In the tables of the following paragraphs are listed, named and coded the items and units making up the
Equipment Shelf (see para. 2.2.1 on page 87) and Fans subrack (see para 2.2.2 on page 104).

Furthermore, for any item the position and the maximum quantity that can be allocated inside the subracks

are indicated too.

Such tables report the following information :

• Item Name

• The ”Acronym” identifying the units is silk–screen printed on the front cover plate. The same
Acronym, not provided with the point (e.g. L–4.1 becomes L–41), is used by the Craft Terminal
to distinguish the unit.
There is in exception to this rule for the P3E3T3; the unit is identified as P3E3T3 on the front
cover plate and as P3E3/T3 on the Craft Terminal.

• Factory and ANV part numbers (e.g. 411.XXX.XXX ; 3ALXXXXX XXXX)

• Maximum quantity

• Position of the unit inside the equipment. Refer to Figure 32. at page 84 for slot numbering.

• Number of explanatory notes

Table 18. on page 105 (see para 2.2.3 on page 105) reports all the explanatory notes .
1AA 00014 0004 (9007) A4 – ALICE 04.10

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2.2.1 Equipment Shelf part list

Table 15. Main part list

ANV Part Number Max.
NAME ACRONYM SLOT NOTES
(Factory Part Number) Qty

1660SM MECHANICAL STRUCTURE “without” integrated Fans subrack (SR60M)

3AL 78834 AA––
1660SM SHELF – 1
(593.155.059E)

It contains:

3AL 79157 AA––
1660SM SHELF SR60M 1 – 2
(593.155.073 U)

1660SM MECHANICAL STRUCTURE “with” integrated Fans subrack

1660SM SUBRACK WITH
–– 3AL 89794AB–– – 3
FANS

It contains:

1660SM SUBRACK AND
–– 8DG 15205 AA–– 1 – 2
FAN

It contains:

METALLIC FAN GRID FOR 3AL 89559 AA––
–– 1 FILTER 4
ASSEMBLED FANS UNIT ––

ASSEMBLED FANS UNIT –– 3AL 89561AB–– 2 F1, F2

DUST FILTER FOR 8DG 15264 AA––
–– 1 FILTER 4
ASSEMBLED FANS UNIT ––

Parts contained in the subracks

3AL 79088 AC––
TERMINATION BUS/2 TBUS 2 23, 40 5
(487.166.408 B)

SFP EXTRACTOR 3AL 81728 AA–– 1 –– 6

OPTICAL COMPENSATION DEVICE
LOW LOSS SMF C + 1AB 210830005
–– 1 –– 7
BAND DCM–20KM ––

LOW SPEED PORTS (PDH) 8

3AL 79092 AA–– 24, 27,
63x2 MBIT/S PORT 1.0/2.3 P63E1 9
(474.166.425 V )
1AA 00014 0004 (9007) A4 – ALICE 04.10

30, 32,
7
63x2 MBIT/S G703/ISDN– 3AL 79092AC–– 33, 36, 9
P63E1N–M4 39
PRA–FS PORT (474.166.046 C) 10

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HIGH SPEED PORTS (PDH) 11

3AL 78864 AA––
3x34/45 MBIT/S SWIT. PORT P3E3T3 16 24 to 39 12
(474.156.339L)

HIGH SPEED PORTS : STM–1 (SDH) and 140 Mbit/s (PDH) 13

4 x STM–1 ELECTRICAL 3AL 78823 AA––
P4ES1N 14
PORT/1 (474.166.423T)

4 X 140/STM1 SWITCH. O/E 3AL 79263 AA–– 15
P4E4N 16 24 to 39
PORT/1 (474.156.371L) 16

3AL 78821 BA––
4x STM–1 PORT/1 P4S1N 16
(474.156.375 Q)

16xSTM1 – 4xSTM4 P16S1–4E 3AL89668 AA–– 16 24 to 39 17

HIGH SPEED PORTS : OC3 (SONET)

4 x OC3 AU3/TU3 CONV. 3AL 81736 AA––
P4OC3 16 24 to 39 16
PORT (474.156.186 U)

4 x ANY CONCENTRATOR

25+26
28+29
3AL 81635 AA–– 34+35
4 x ANY HOST C 4XANYC 6 18
(411.102.533 K) 37+38
30+31
32+33
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HIGH SPEED PORTS : STM–4 (SDH) 13

3AL 78856 BA––
S–4.1 PORT/1 FC/PC S–4.1N
(474.156.376 R)

3AL 78856 BB––
S–4.1 PORT/1 SC/PC S–4.1N
(474.156.377 J)

3AL 78856 BC––
L–4.1 PORT/1 FC/PC L–4.1 N
(474.156.378 T)
19
16 24 to 39
3AL 78856 BD–– 20
L–4.1 PORT/1 SC/PC L–4.1 N
(474.156.379 U)

3AL 78856 BE––
L–4.2 PORT/1 FC/PC L–4.2N
(474.156.380 J)

3AL 78856 BF––
L–4.2 PORT/1 SC/PC L–4.2N
(474.156.381 F)
25,26,
3AL 79176 AA–– 28,29,
4 x STM–4 PORT P4S4N 4 21
411.101.062 V 34,35,
37,38
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HIGH SPEED PORTS : STM–16 (SDH) 13

3AL 78894 CA––
S–16.1 PORT FC/PC/16C S–16.1ND
(411.101.308 R)

3AL 78895 CA––
S–16.1 PORT SC /16C S–16.1ND
(411.101.309 J)

3AL 78896 CA–– 25+26
L–16.1 PORT FC/PC/16C L–16.1ND
(411.101.310 E) 28+29 19
4
3AL 78897 CA–– 34+35 20
L–16.1 PORT SC/16C L–16.1ND 37+38 22
(411.101.311 T)

3AL 78898 CA––
L–16.2 PORT FC/PC/16C L–16.2ND
(411.101.312 U)

3AL 78899 CA––
L–16.2 PORT SC/16C L–16.2ND
(411.101.313 V)

3AL 79029 CA––
L–16.2 JE2 PORT FC/PC/16C L–16.2ND
(411.101.316 Y)

3AL 79029 CB––
L–16.2 JE2 PORT SC/PC/16C L–16.2ND 25+26 19
(411.101.317 Z)
4 28+29 20
L–16.2 JE3 PORT FC/PC/16C 3AL 79030 DA–– 34+35 23
L–16.2ND 37+38 22
CH34 (411.102.549 B)

L–16.2 JE3 PORT SC/PC/16C 3AL 79030 DB––
L–16.2ND
CH34 (411.102.550 G)

25+26
19
I–16.1 PORT /SFF 3AL 80881AA–– 28+29
I–16.1ND 4 22
(Intra office) (411.102.022 N) 34+35
24
37+38

3AL 81289 AA––
STM–16 SLIM PORT UP/SFP O–16ES 16 24 to 39 25
(411.102.508 B)

(Table continues)
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ANV Part Number
Max.
NAME ACRONYM (Factory Part Num- SLOT NOTES
Qty
ber)

STM16 195.7 PORT 6400 3AL 79187 BA––
L–16.2ND
SC/PC/16C (411.101.320 G)
STM16 195.5 PORT 6400 3AL 79187 BB––
L–16.2ND
SC/PC/16C (411.101.321 V)
STM16 195.3 PORT 6400 3AL 79187 BC––
L–16.2ND
SC/PC/16C (411.101.322 W)
STM16 195.1 PORT 6400 3AL 79187 BD–– 25+26 19
L–16.2ND
SC/PC/16C (411.101.323 X) 4 28+29 22
STM16 194.9 PORT 6400 3AL 79187 BE–– 34+35 26
L–16.2ND 37+38
SC/PC/16C (411.101.324 Y)
STM16 194.7 PORT 6400 3AL 79187 BF––
L–16.2ND
SC/PC/16C (411.101.325 Z)
STM16 194.5 PORT 6400 3AL 79187 BG––
L–16.2ND
SC/PC/16C (411.101.326 S)
STM16 194.3 PORT 6400 3AL 79187 BH––
L–16.2ND
SC/PC/16C (411.101.327 T)
STM16 193.7 PORT 6400 3AL 79187 BL––
L–16.2ND
SC/PC/16C (411.101.328 C)
STM16 193.5 PORT 6400 3AL 79187 BM––
L–16.2ND
SC/PC/16C (411.101.329 D)
STM16 193.3 PORT 6400 3AL 79187 BN––
L–16.2ND
SC/PC/16C (411.101.330 A)
STM16 193.1 PORT 6400 3AL 79187 BP–– 25+26
L–16.2ND 19
SC/PC/16C (411.101.331 X) 28+29
4 22
STM16 192.9 PORT 6400 3AL 79187 BQ–– 34+35
L–16.2ND 27
SC/PC/16C (411.101.332 Y) 37+38
STM16 192.7 PORT 6400 3AL 79187 BR––
L–16.2ND
SC/PC/16C (411.101.333 Z)
STM16 192.5 PORT 6400 3AL 79187 BS––
L–16.2ND
SC/PC/16C (411.101.334 S)
STM16 192.3 PORT 6400 3AL 79187 BT––
L–16.2ND
SC/PC/16C (411.101.335 T)

(Table continues)
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 91 / 706

706

ANV Part Number
Max.
Qty
ber)

STM16 195.7 PORT 12800 3AL 79188 BA––
L–16.2ND
SC/PC/16C (411.101.336 U)
STM16 195.5 PORT 12800 3AL 79188 BB––
L–16.2ND
SC/PC/16C (411.101.337V)
STM16 195.3 PORT 12800 3AL 79188 BC––
L–16.2ND
SC/PC/16C (411.101.338 E)
STM16 195.1 PORT 12800 3AL 79188 BD–– 25+26
L–16.2ND 19
SC/PC/16C (411.101.339 F) 28+29
4 22
STM16 194.9 PORT 12800 3AL 79188 BE–– 34+35
L–16.2ND 26
SC/PC/16C (411.101.340 L) 37+38
STM16 194.7 PORT 12800 3AL 79188 BF––
L–16.2ND
SC/PC/16C (411.101.341 H)
STM16 194.5 PORT 12800 3AL 79188 BG––
L–16.2ND
SC/PC/16C (411.101.342 A)
STM16 194.3 PORT 12800 3AL 79188 BH––
L–16.2ND
SC/PC/16C (411.101.343 B)
STM16 193.7 PORT 12800 3AL 79188 BL––
L–16.2ND
SC/PC/16C (411.101.344 C)
STM16 193.5 PORT 12800 3AL 79188 BM––
L–16.2ND
SC/PC/16C (411.101.345 D)
STM16 193.3 PORT 12800 3AL 79188 BN––
L–16.2ND
SC/PC/16C (411.101.346 E)
STM16 193.1 PORT 12800 3AL 79188 BP–– 25+26
L–16.2ND 19
SC/PC/16C (411.101.347 F) 28+29
4 22
STM16 192.9 PORT 12800 3AL 79188 BQ–– 34+35
L–16.2ND 27
SC/PC/16C (411.101.348 Q) 37+38
STM16 192.7 PORT 12800 3AL 79188 BR––
L–16.2ND
SC/PC/16C (411.101.349 R)
STM16 192.5 PORT 12800 3AL 79188 BS––
L–16.2ND
SC/PC/16C (411.101.350N)
STM16 192.3 PORT 12800 3AL 79188 BT––
L–16.2ND
SC/PC/16C (411.101.351 B)
HIGH SPEED PORTS : STM–64 (SDH)
STM 64 PORT 3AL 80802 AA––
S–642E
S–64.2E FC (474.156.064 C)
STM 64 PORT 3AL 80802 AB––
L–642E
L– 64.2 B FC ––.––.–– 25+26
STM 64 PORT 3AL 81249 AA–– 28+29
I–641E 4 28
I 64.1E FC (474.156.158 P) 34+35
STM 64 PORT 3AL 91884 AA–– 37+38
S–642E
XFP S–64.2 FC ––.––.––
STM 64 PORT 3AL 91885 AA––
I–641E
1AA 00014 0004 (9007) A4 – ALICE 04.10

XFP I–64.1 FC ––.––.––

ED 03

3AL 91669 AA AA 92 / 706

706

ANV Part Number
Max.
Qty
ber)

ISA – ETHERNET PORT

3AL 80407 AA–– 29
ETHERNET PORT ETH–MB 6 24 to 39
(474.156.038 A)

3AL 80702 AB––
GIGABIT ETHERNET PORT/2 GETH–MB 8 24 to 39 30
––.––.––

ISA – ATM PARTS

3AL 79093 AA––
ATM MATRIX 4X4 ATM4X4 31
(411.101.035 J)

ATM MATRIX 4X4 3AL 81185 AA–– 24 to 39
ATM4X4V2 32
ENHANCED (411.102.475 Z)
4
3AL 89917 AA––
ATM MATRIX 4X4 D3 ATM4X4D3 33
––.––.––

3AL 79094 AA––
ATM MATRIX 8X8 ATM8X8 24 to 38 34
(411.101.036 K)

ISA – PR_EA PARTS

PR_EA MATRIX 3AL 79631 AA––
PREA4ETH 4 24 to 39 35
4X ETHERNET (411.101.281 W)

PR_EA MATRIX 3AL 81275 AA––
PREA1GBE 4 24 to 39 36
1XGB–ETH (411.102.505 Y)

ISA – PR PARTS

PR MATRIX 3AL 89677 AA––
ISA–PR 3 25 to 38 37
4X4 STM4 PLUG–IN ––.––.––

ISA – ES PARTS

3AL 98128AA––
ISA–ES1 8FE ES1–8FE 8 24 to 39
––.––.––

3AL 98150AA––
ISA–ES1 8FX ES1–8FX 8 24 to 39 38
––.––.––

3AL81879 AA––
ISA–ES4 8FE +1GE ES4–8FE 8 24 to 39 39
(474.156.195 V)

3AL81915 AA––
ISA–ES16 BOARD ISA–ES16 8 24 to 39
––.––.––

CWDM PORTS
1AA 00014 0004 (9007) A4 – ALICE 04.10

2xCH TRANSPONDER SFP 3AL 81427 AA––
COWLA2 16 24 to 39 40
W/O OPTICS (411.102.520 S)

ED 03

3AL 91669 AA AA 93 / 706

706


LS (LOW SPEED) ACCESS CARDS

21x2 MBIT/S PROT. 75 OHM 3AL78831AA––
A21E1
1.0/2.3 (474.156.323C)
41
3AL78832AA–– 1 to 9,
21x2 MBIT/S PROT. 120 OHM A21E1 18
(474.156.324D) 13 to 21

21x2 MBIT/S PROT. 120 OHM 3AL 79163 AA––
A21E1 41, 42
K20 (474.156.366 P)

HS (HIGH SPEED) ACCESS CARDS

3AL78865AB––
3x34 MBIT/S 75 OHM A3E3 43
(474.156.181 X)

3AL78866AB–– 2 to 9,
3x45 MBIT/S 75 OHM A3T3 16 44
(474.156.182 Y) 13 to 20

4xSTM–1 ELECTRICAL 75 3AL78835AA––
A4ES1 45
OHM (474.156.325E)

3AL 78849 AA–– 2 to 9,
HIGH SPEED PROTECTION HPROT 8 46
(474.156.127 Y) 13 to 20

16xSTM1 HIGH SPEED 3AL 36306 AA–– 2 to 9,
HPROT 8 47
PROTECTION ––.––.–– 13 to 20

3AL78818AA–– 2 to 9,
2x140/STM–1 O/E ADAPTER A2S1 16 48
(474.166.421Z) 13 to 20

OPTICAL ACCESS 2 to 8,
A120S1E 3AL 89669 AA–– 8 49,50
12xSTM1 13 to 20

OPTICAL ACCESS 2 to 9,
A120S1SE 3AL 91880 AA–– 16
12xSTM1 SLIM 13 to 20

ELECTRICAL ACCESS 2 to 9,
A16ES1E 3AL 89670 AA–– 16 50
16xSTM1 13 to 20

ISA – ETHERNET ACCESS CARDS

3AL 80404 AA––
ETHERNET ACCESS ETH–ATX 6 51
(474.156.039 B) 2 to 9,
GIGABIT ETHERNET 3AL 80411 AB–– 13 to 20
GETH–AG 8 52
ACCESS/2

ISA – PR ACCESS CARDS

ISA–PR 16XETH 10/100 3AL 89678 AA––
16FEA–PR 6
ACCESS ––.––.–– 1 to 9, 53
1AA 00014 0004 (9007) A4 – ALICE 04.10

ISA–PR 2XGBE 1000 3AL 89679 AA–– 13 to 21
2 GBA–PR 6 54
ACCESS PLUG–IN ––.––.––

ED 03

3AL 91669 AA AA 94 / 706

706


CONTROL AND GENERAL INTERFACE

CONTROL AND GENERAL
CONGI 3AL78830AD–– 2 10, 12 55,
INTERFACE

SERVICE

3AL78817AA––
SERVICES I/F SERVICE 1 11 56
(411.100.704R)

BOOSTER AND PREAMPLIFIER

OMSN BOOSTER +10dBm 3AL 78962 AA––
BST10
FC/PC (411.100.902 G)

OMSN BOOSTER +10dBm 3AL 78962 BA––
BST10
SC/PC (411.101.245 H)

OMSN BOOSTER +15dBm 3AL 78962 AC––
BST15
FC/PC (411.100.904 A) 2 to 8
OMSN BOOSTER +15dBm 3AL 78962 BC–– 13 to 19
BST15
SC/PC (411.101.247 B)
8 57
OMSN BOOSTER +17dBm 3AL 78962 AD––
BST17
FC/PC (411.100.905 B)

OMSN BOOSTER +17dBm 3AL 78962 BD––
BST17
SC/PC (411.101.248 L)

PREAMPLIFIER 2.5 GB/S 3AL 78963 AD––
PR16
SC/PC CH34 (411. 102.557 T) 2 to 8
PREAMPLIFIER 2.5 GB/S 3AL 78963 AC–– 13 to 19
PR16
FC/PC CH34 (411.102.558 C)

(Table continues)
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 95 / 706

706


CWDM CONNECTION MODULES

3AL 81344 AA––
COADM 1 CH (1470) COADM1
(411.102.513P)

3AL 81344 AB––
(411.102.542 U)

3AL 81344 AC––
(411.102.543 V)

3AL 81344 AD––
(411.102.544 W)

3AL 81344 AE––
(411.102.545 X)

3AL 81344 AF––
(411.102.546 Y) 1 to 8
8
3AL 81344 AG–– 13 to 20
COADM 1 CH (1590) COADM1 57
(411.102.547 Z)

3AL 81344 AH––
(411.102.548 A)

3AL 81346 AA––
COADM 2 CH (1470–1490) COADM2
(411.102.541 R)

3AL 81346 AB––
(411.102.539 Z)

3AL 81346 AC––
(411.102.540 E)

3AL 81346 AD––
(411.102.541 T)

3AL 81348 AA–– 1 to 8
MUX – DEMUX 8 CH. COMDX8 8
(411.102.517 K) 13 to 20
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 96 / 706

706


STM–1 MODULES

3AL78815AA––
S–1.1 OPT. INTERF. FC/PC IS–1.1
(474.166.420 C)

3AL 78815 AB––
S–1.1 OPT. INTERF. SC/PC IS–1.1
(474.166.424 U)

3AL78838AA––
L–1.1 OPT. INTERF. FC/PC IL–1.1
(474.156.326 F)

3AL 78838 AB––
L–1.1 OPT. INTERF. SC/PC IL–1.1
(474.156.352 R)

3AL78839AA–– 58,59
L–1.2 OPT. INTERF. FC/PC IL–1.2
(474.156.327 G)

3AL 78839 AB––
L–1.2 OPT. INTERF. SC/PC IL–1.2
(474.156.353 J)
3AL 91790 AA–– 64 ––
S–1.1 OPT. INTERF. LC IS–1.1
––––––––
3AL 91791 AA––
L–1.1 OPT. INTERF. LC IL–1.1
––––––––
3AL 91792 AA––
L–1.2 OPT. INTERF. LC IL–1.2
––––––––
3AL78840AA––
L–1.2 JE OPT. INTERF. FC/PC IL–1.2
(474.156.328 R)
58,59,60
58 59 60
3AL 78840 AB––
L–1.2 JE OPT. INTERF. SC/PC IL–1.2
(474.156.354 K)

140/155 ELECTRICAL 3AL37558AB––
ICMI 61
INTERFACE (474.156.346 K)

STM–1 MULTIMODE OPT 3AL 80741 AA––
MM1 58
SC/PC (474.166.035 Z)
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 97 / 706

706


STM–4 MODULES

S–4.1 OPTICAL INTERF. 3AL 79340 AA––
FC/PC 474.156.372 M
S–4.1 OPTICAL INTERF. 3AL 79451 AA––
IS–4.1
SC/PC 474.156.384 A
3AL 91793 AA––
S–4.1 OPTICAL INTERF. LC
––––––––
L–4.1 OPTICAL INTERF. 3AL 79452 AA––
FC/PC 474.156.385 B
L–4.1 OPTICAL INTERF. 3AL 79452 AB––
IL–4.1 8 –– 62
SC/PC 474.156.386 C
3AL 91794 AA––
L–4.1 OPTICAL INTERF. LC
––––––––
L–4.2 OPTICAL INTERF. 3AL 79453 AA––
FC/PC 474.156.387 D
L–4.2 OPTICAL INTERF. 3AL 79453 AB––
IL–4.2
SC/PC 474.156.388 N
3AL 71975 AA––
L–4.2 OPTICAL INTERF. LC
––––––––
4xANY MODULES

4 X ANY HS PLUG–IN 1310 3AL 81616 AA–– Refer to
OH–I 12 63
(OH–I) (474.156.178 K) Figure 56.

4 X ANY LS PLUG–IN 1310 3AL 81617 AA–– Refer to
OL–IN 24 64
(OL–I) (474.156.179 L) Figure 56.

3AL81613 AA–– Refer to
4 X ANY HS PLUG–IN 850 OH–MM 12 63
(474.156.175 G) Figure 56.

3AL81615 AA–– Refer to
4 X ANY LS PLUG–IN 850 OL–MM 24 64
(474.156.177 A) Figure 56.
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 98 / 706

706


ETHERNET “SFP” OPTICAL MODULES

OPTO TRX 1.25GBE SFP
1AB 18728 0001 ––
1000B–LX

OPTO TRX 1.25GBE SFP
1AB 18728 0002 ––
1000B–SX
65
1000B 64
OPTO TRX 1.25GBE SFP 66
1AB 18728 0028 ––
1000B–ZX

OPTO TRX SFP 1.25GBE SX
1AB 187280033 ––
DDM

STM–1 “SFP” OPTICAL MODULES

S S–1.1
OPTO TRX SFP S–1.1 or 1AB 194670001 256 ––
100B

OPTO TRX SFP L–1.1 65
SL–1.1 1AB 194670002 256 ––
PLUGIN

OPTO TRX SFP L–1.2
SL–1.2 1AB 194670003 256 ––
–40 +85 C LC

STM4 “SFP” OPTICAL MODULES

TRX SFP S–4.1 SS–4.1 1AB 196360001 32 ––

TRX SFP L–4.1
SL–4.1 1AB 196360003 32 ––
–40 +85 C LC 65

TRX SFP L–4.2
SL–4.2 1AB 196360002 32 ––
–40 +85 C LC

STM–16 “SFP” OPTICAL MODULES (Black and White)

OPTO TRX SFP S–16.1 SS–161 1AB 19637 0001

OPTO TRX SFP L–16.1 SL–161 1AB 19637 0004 16 –– 65

OPTO TRX SFP L–16.2 SL–162 1AB 19637 0003
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 99 / 706

706


CWDM “SFP” OPTICAL MODULES (Colored)

CWDM 1470 NM
SS–162C 1AB 19634 0001
PIN PLUGIN

CWDM 1490 NM
SS–162C 1AB 19634 0002
PIN PLUGIN

CWDM 1510 NM
SS–162C 1AB 19634 0003
PIN PLUGIN

CWDM 1530 NM
SS–162C 1AB 19634 0004
PIN PLUGIN
16 –– 65
CWDM 1550 NM
SS–162C 1AB 19634 0005
PIN PLUGIN

CWDM 1570 NM
SS–162C 1AB 19634 0006
PIN PLUGIN

CWDM 1590 NM
SS–162C 1AB 19634 0007
PIN PLUGIN

CWDM 1610 NM
SS–162C 1AB19634 0008
PIN PLUGIN

CWDM 1470 NM
SL–162C 1AB19635 0001
APD PLUGIN

CWDM 1490 NM
SL–162C 1AB19635 0002
APD PLUGIN

CWDM 1510 NM
SL–162C 1AB19635 0003
APD PLUGIN

CWDM 1530 NM
SL–162C 1AB19635 0004
APD PLUGIN
16 –– 65
CWDM 1550 NM
SL–162C 1AB19635 0005
APD PLUGIN

CWDM 1570 NM
SL–162C 1AB19635 0006
APD PLUGIN

CWDM 1590 NM
SL–162C 1AB19635 0007
APD PLUGIN

CWDM 1610 NM
SL–162C 1AB19635 0008
APD PLUGIN
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 100 / 706

706


CONTROLLER

3AL78836AB––
EQUICO E PQ2/EQC 1 22 67
(411.102.506 Z)

MATRIX

3AL81072 AA––
MATRIX ENHANCED MATRIXE 2 23,40 68
(411.102.032 Q)

FLASH CARD

FLASH CARD 256 MB 1AB 17634 0002
MEM–DEV 1 –– 69
–20/85° C ––––
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 101 / 706

706

Table 16. Accessories list


EQUIPMENT ACCESSORIES
3AN49397AA–– 70
DUMMY PLATE W20 –– 32 ––
(299.701.587 J)
3AN49399AA–– 71
(299.701.590 Z)
3AN49400AA–– 72
(299.701.591 N)

1AF00398AA––
TELEPHONE HANDSET –– 1 –– 73
(013.200.016A)
3AL91653AA––
INST. KIT X 1660SM R5 –– 1 –– 74
––.––.––
3CA 08540 AA––
19” / 21” ADAPTER KIT –– 1 –– 75
(299.701.597 L)
CAPS ESD COMMON PART 3AL 79266 AA––
–– 1 ––
OMSN (299.701.877 U)
3AL 79267 AA––
CAPS ESD 1.0/2.3 OMSN –– 38 –– 76
(299.701.878 D)
3AL 79268 AA––
CAPS ESD SUB/D OMSN –– 6 ––
(299.701.879 E)
40A 72V CIRCUIT 1AB16271 0015
–– 2 –– 77
BREAKER
40A CIRCUIT 1AB02438 0031
–– 2 –– 78
BREAKER S9 RACK
1AB 162710003
4A 72Vdc CIRCUIT BREAKER –– 2 –– 79
(001.791.353 R)
CASE EMC 1.0/2.3 FOR 3AL 80915 AA––
–– 64 –– 80
CABLE 3.6 mm (298.701.209 N)
120 OHM KIT FOR CABLE 3AN 50125 AA––
–– 2 –– 81
SUPPORT (299.701.063 X)
1AB 07984 0025
SM JUMPER FC/PC 1,35 MT ––
16 –– 82
1AB 08001 0065
SM JUMPER SC/PC 1,35 MT ––

JUMPER SM MU/SPC FC/ 1AB 217410045
SPC (1,35 m) ––
1 83
JUMPER SM MU/SPC SC/ 1AB 217420046
SPC (1,35 m) ––
KIT T_BUS UPGRADE FOR 3AL 81202 AA
–– 1 –– 84
1AA 00014 0004 (9007) A4 – ALICE 04.10

ISA APPLICATION (299.701.228 H)

KIT–CABLING ETHERNET –– 3AL 81639 AA–– 1 –– 85

ED 03

3AL 91669 AA AA 102 / 706

706


KIT SM/MM 50 um 3AL 81465 AA––

–– 64 –– 86
PATCH CORD (299.701.237 S)

KIT SM/MM 62.5 um 3AL 81466 AA––
–– 64 –– 86
PATCH CORD (299.701.2378B)
120 OHM NEW 3AL80834 AA––
–– 54 –– 87
CONNECTOR KIT (299.701.066 S)
1.0/2.3 COAXIAL 1AB061220003
–– 764 –– 88
CONNECTOR (3mm) (040.144.001N)
MALE CONNECTOR 1.0/2.3 1AB 00972 0049
–– 128 –– 89
(3.6 mm)
1.0/2.3 MALE COAXIAL 1AB158340001
–– 8 –– 90
CONNECTOR BALUN (040.144.010J)

CONNECTORS RJ45 M8
–– 1AB 07461 0019 300 –– 91
WIRES ITC CAT.6

SPARE PARTS

3AL 79088 AC––
TERMINATION BUS/2 TBUS 1 –
(487.166.408 B)

3AL 79497 AA––
EXTRACTORS KIT –– 1 ––
(299.701.341 A)

SFP MODULE PLUG–IN
–– 3AL 81728 AA–– 1 –– 92
TOOL

SOFTWARE 93

(End of table)
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 103 / 706

706

2.2.2 Fans Subrack 19” part list

Refer to Figure 33. on page 84.

Table 17. Fans Subrack 19” part list


MECHANICAL STRUCTURE

3AL79773AA––
FANS SHELF 19” SRFAN 1 – 94
(593.153.008 A)

ACCESSORIES

FAN UNIT FOR FAN SHELF 3AL 79772 AA––
FAN 4 0,1,2,3
19” (411.101.423 L)

METALLIC FAN GRID –– 3AL 81812 AA–– 2 4.5

DUST FILTER FOR FAN 3AL 80371 AA–– 95
–– 2 4,5
SHELF 19” (299.908.007 Y)
(End of table)
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 104 / 706

706

2.2.3 Explanatory notes

Table 18. Explanatory notes

Note Explanation

The subrack must be install in the Rack together with the FANS SHELF 19” and the relevant
1
fans units.
2 It is the main shelf of the equipment, also with the back panel
3 The subrack also hosts two fans units in the lower two slots of the mechanical structure.
4 Filters used as alternative in the 1660SM SUBRACK AND FAN.
5 Mandatory unit. Used to provide voltage logical reference to all Control and Auxiliary bus.
6 Extractors used to remove the SFP module.
To be used for “STM 64 PORT L– 64.2 B FC” extended application to cover span with
7 attenuation range (S–R) up to 28 dB, see para. 5.8.2 on page 641. Must be provided also
relevant jumpers.
8 As Low Speed ports are intended the 2 Mbit/s speed ports
To be used with the LS access cards. Three access cards are needed to fully connect the port’s
9
channel. The P63E1, P63E1N–M4 spare port must be inserted in slot 32.
The board supports the NT functionality, performance monitoring, Retiminig and Frame Slip
10
functionalities.
11 As High Speed PDH ports are intended the 34 Mbit/s and the 45 Mbit/s ports
The same board can be used as 3x34 Mbit/s or 3x45Mbit/s but its corresponding access cards
12
are separated (i.e A3E3 for 3x34 Mbit/s and A3T3 for 3x45 Mbit/s)
13 As High Speed SDH ports are intended STM–1, STM–4, STM–16, STM–64 ports
14 The port needs an access card with 4 STM–1 electrical interfaces
15 Each port of this board can be configured as 140 Mbit/s or STM–1.
The port needs four (electrical or optical) modules to reach the maximum capability of four
channels. Two modules have to be inserted on the card front panel and two on the correspond-
16 ing access card 2 x STM–1 front panel (A2S1). Notice that different kind of access module (elec-
trical and optical, also of different characteristic and connectors) can be inserted in the port card
or in the access card
The unit has 4 cavity on the front panel that can be equipped with up to 4 STM4 SFP modules
or up to 4 STM1 SFP modules. The unit can be used in conjuction with the relevant access card
17 in order to provide up to 12 STM1 optical ports (A12OS1E) or up to 16 STM1 electrical ports
(A16ES1E). Refer to Figure 80. on page 169 for relationship between SFP modules and rele-
vant Housing board.
The unit is two slot wide and it can house up to 4 optical modules (OH–I, OL–IN, OH–MM, OL–
18
MM). For details about the max. board capabilty refer to paragraph 3.10 on page 293.
19 The ports does not need access card
20 Ports supplied with different connectors types
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 105 / 706

706

Note Explanation
Note: this board does not support Low Order traffic termination
The board is used in conjunction with ISA–PR board.

21 Two modules have to be inserted on the card front panel.

Notice that different kind of STM–4 modules (also of different characteristic and connectors)
can be inserted in the port card .
22 STM–16 port is two slot wide
23 Ports to be used with the Booster
The board is used to interconnect distances less than approximately 2Km (intra–office applica-
24
tion)
The unit is one slot wide and must be equipped with SFP optical module. Refer to Figure 80.
25
on page 169 for relationship between SFP modules and relevant Housing board.
26 Port used as input for the WDM equipment (blue band)
27 Port used as input for the WDM equipment (red band)
28 The unit is two slot wide.
29 The board has #11 RJ45 interfaces
The board can be equipped with up to four 1.25 Gbit/s Modules. Refer to Figure 80. on page
30
169 for relationship between SFP modules and relevant Housing board.
The unit provides a STM–1 interface on the front coverplate.
It manages up to 16 ports configurable as: SDH VC–4, SDH VC–3, SDH VC–12, PDH 34M,
31 PDH 2M.
The max throughput towards backpanel is 622 Mbit/s.
The unit supports the PNNI.
PDH 34M, PDH 2M.
32
The unit supports the IMA.
PDH 34M, PDH 2M.
33
The unit supports the IMA.
The board is two slot wide
It manages up to 16+16 ports configurable as: SDH VC–4, SDH VC4–C, SDH VC–3, SDH
34 VC–12, PDH 45M, PDH 34M, PDH 2M.
The max throughput towards backpanel is 1.2 Gbit/s.
The unit supports the PNNI.
With a max. data throughput of 1Gb/s, it allows the transportation of MPLS packets over SDH,
35 their routing, and the traffic congestion management. It hosts, further, 4x 10/100BaseT
interfaces carring MPLS over ethernet.
With a max. data throughput of 1.6 Gb/s, it allows the transportation of MPLS packets over
SDH, their routing, and the traffic congestion management.
36
Refer to Figure 80. on page 169 for relationship between SFP modules and relevant Housing
1AA 00014 0004 (9007) A4 – ALICE 04.10

board.

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Note Explanation
The board is two slot wide
With a max. data throughput of 6.5 Gb/s data throughput, it allows the transportation of ethernet

packets over SDH, their routing, and the traffic congestion management.

37 It hosts four STM4 optical modules interfacing physical line (Refer to Figure 80. on page 169
for relationship between SFP modules and relevant Housing board).
Two access cards max are used for each PR board. Mixed access cards configuration are al-
lowed.
The unit must be equipped with SFP optical module (Refer to Figure 80. on page 169 for rela-
38
tionship between SFP modules and relevant Housing board).
The unit can be equipped with one 1.25 Gbit/s Modules (Refer to Figure 80. on page 169 for
39 relationship between SFP modules and relevant Housing board).
This module is not operative in current release.
The board must be equipped with SFP optical module “colored” (1470 – 1610 nm) or “Black and
White”. The max. number of SFP module per board is equal to four.
40
board.
Protected LS access card . Allow the bidirectional connection of up to twenty–one 2 Mbit/s
41
channels. To be used in EPS protected configurations.
42 Compliant with ITU K20 norms
HS access card dedicated to the 3x34 port. Allows the bidirectional connection of up to three
43
34 Mbit/s channels.
HS access card dedicated to the 3x45 port. Allows the bidirectional connection of up to three
44
45 Mbit/s channels.
HS access card to be used for the 4 x STM–1 electrical port. Allows the bidirectional connection
45
of up to 4 channels
To be used in an EPS protection scheme as access card for the HS electrical spare port
46
(3x34 Mbit/s, 3x45 Mbit/s and 4x155 Mbit/s)
To be used in an EPS protection scheme as access card for the HS electrical spare port
47
16x 155 Mbit/s
48 The access card needs up to 2 optical or electrical modules to be inserted inside
The unit can be equipped with up to 12 SFP STM1 optical modules S–1.1.
49 Refer to Figure 80. on page 169 for relationship between SFP modules and relevant Housing
board.
50 To be used in conjuction with P16S1–4E.
51 The board has #14 RJ45 interfaces.
The board can be used in conjunction with the ETH–MB.
If used in conjunction with ETH–MB the access card provides up to two Gigabit Ethernet Inter-
face; in this configuration only the two upper interfaces present on the access card can be used
52 for Gbit Ethernet application. For details on slot position refer to Table 28. on page 119.

The access card can be equipped with SFP Optical module. Refer to Figure 80. on page 169
for relationship between SFP modules and relevant Housing board.
1AA 00014 0004 (9007) A4 – ALICE 04.10

The board has 16 RJ45 interfaces at 10/100 Mbit/s.
53
It is used in conjunction with the ISA–PR Card for data access.

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Note Explanation
The board has 2 plug–in interfaces at 1 Gbit/s (Refer to Figure 80. on page 169 for relationship
54 between SFP modules and relevant Housing board)

It is used in conjunction with the ISA–PR Card for data access.

A max of two Control and General interfaces can be used.
It delivers two voltage levels to all the cards.
55 It provides external connectors for housekeepings, remote alarms, rack lamps, Q interface, LAN
interface.
If two CONGI cards are inserted, they provide different interfaces.
56 Provides the connectors for the auxiliary , EOW channels and the synchronization interfaces.
57 The board is two slot wide
Up to 2 of these modules are inserted on the following cards : P4E4N, P4S1N and A2S1 to real-
ize optical connections for a maximum of 2 STM–1 channels.
58 Only one of these modules can be inserted in the ATM matrix 4X4.
With the MM1 module must be ordered also the specific patch cord in order to reach the multi-
mode charachteistics (50um patch cord or 62 um patch cord).
59 Optical modules supplied with different connectors.
60 Optical modules to be used with the Booster
Up to 2 of these modules are inserted on the following cards : P4E4N, P4S1N and A2S1 to real-
61 ize electrical connections for a maximum of 2 STM–1 or 140 Mbit/s channels .
Only one of these modules can be inserted in the ATM matrix 4X4.
Up of 2 of these modules are inserted on the P4S4N card to realize optical connections for a
62 maximum of 2 STM–4 channels (one for module).Optical modules supplied with different con-
nectors.
63 Used for: Fiber Channel, FICON, Gigabit Ethernet
64 Used for: Fast Ethernet, FDDI, ESCON, Digital Video.
65
board.
Due to access limitation only two of this modules can be equipped when GETH–AG is used in
66
conjunction with ETH–MB.
67 Equipment Controller card provides the F interface for the Craft Terminal connection
Two MATRIX cards can be used in a 1+1 protected EPS configuration. The card performs con-
68
nection and cross–connection functionalities and moreover synchronization functionalities.
69 It contains the equipment data base . To be used for running “SDH” and “ATM” software
It is essential to insert the relevant dummy plates on the spaces left by the port or access mod-
70
ules units not supplied in order to obtain the EMI/EMC performances.
71 Dummy plate for unequipped SERVICES I/F unit
72 Dummy plate for unequipped MATRIX unit
73 Optional telephone handset associated to the SERVICES I/F card.
74 It is necessary when Optinex rack is employed
1AA 00014 0004 (9007) A4 – ALICE 04.10

75 Mechanical adaptor utilized to insert the subrack in “21” rack.

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Note Explanation
Protection cups to be used to respect the ESD precaution. At the end of the installation phase
76
all the connectors not used for cabling must be covered with the relevant “protection caps”

77 To be used with CONGI 3AL78830AD––.
78 To be used with S9 Rack.
79 To be used in Optinex rack (TRU) to power the Fan Shelf
80 To be used for EMC performance. One for each 140/155 ELECTRICAL INTERFACE (ICMI)
81 To be installed when 120 Ohm connector are used for 2Mbit/s signals.
Must be provided with optical boosters in order to perform connection with STM–4 or STM–16
82
ports.
Must be provided between “Optical Compensation Device” and “STM 64 PORT L– 64.2B
83
FC” card.
84 Upgrade for ATM functionality.
Cable duct to be used during the installation phase. It allows the electrical cables separation
85
from the optical cables.
86 Must be used in conjunction with “STM–1 MULTIMODE OPT SC/PC” Optical Module
87 Every kit contains #1 connectors for 7x2 Mbit/s interface 120 Ohm
88 To be used for the 2 Mbit/s connections and for the synchronism on SERVICES I/F card.
89 To be used for the 34/45 Mbit/s and STM–1 electrical connections
90 To be used only with SERVICES I/F port card. It allows the 75/120 Ohm conversion.
91 To be used with the relevant cable in the installation phase for ethernet port connection
92 To be used to remove the fiber cable from port connector
93 Details concerning the software P/N are given in the Operator’s Handbook.
The subrack (with relevant fans units and filter) must be install in the Rack together with the
94
1660SM SUBRACK “SR60M”
95 Filters used as alternative in the Fans shelf 19”

(End of table)
1AA 00014 0004 (9007) A4 – ALICE 04.10

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2.3 Relationship between Port Card and Access Card

Table 19. Relationship between P63E1, P63E1N–M4 (63 X 2 Mbit/s unit) port card and A21E1 access
card

Port Card acronym Port Card Slot Access Card acronym Access Card Slot

A21E1 1 (CH. 1–21)

24 A21E1 2 (CH. 22–42)

A21E1 3 (CH. 43–63)

A21E1 4 (CH. 1–21)

27 A21E1 5 (CH. 22–42)

A21E1 6 (CH. 43–63)

A21E1 7 (CH. 1–21)

30 A21E1 8 (CH. 22–42)

A21E1 9 (CH. 43–63)

P63E1, P63E1N–M4 32 (spare) –––––– ––––––

A21E1 13 (CH. 1–21)

33 A21E1 14 (CH. 22–42)

A21E1 15 (CH. 43–63)

A21E1 16 (CH. 1–21)

36 A21E1 17 (CH. 22–42)

A21E1 18 (CH. 43–63)

A21E1 19 (CH. 1–21)

39 A21E1 20 (CH. 22–42)

A21E1 21 (CH. 43–63)
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Table 20. Relationship between P3E3T3 (3X34/45 Mbit/s Switchable unit) port card and A3E3 access
card (3X34 Mbit/s)


P3E3T3 24 A3E3 2 (CH. 1–3)

P3E3T3 25 A3E3 3 (CH. 1–3)

P3E3T3 26 A3E3 4 (CH. 1–3)

P3E3T3 27 A3E3 5 (CH. 1–3)

P3E3T3 28 A3E3 6 (CH. 1–3)

P3E3T3 29 A3E3 7 (CH. 1–3)

P3E3T3 30 A3E3 8 (CH. 1–3)

P3E3T3 31 A3E3 9 (CH. 1–3)

P3E3T3 32 A3E3 13 (CH. 1–3)

P3E3T3 33 A3E3 14 (CH. 1–3)

P3E3T3 34 A3E3 15 (CH. 1–3)

P3E3T3 35 A3E3 16 (CH. 1–3)

P3E3T3 36 A3E3 17 (CH. 1–3)

P3E3T3 37 A3E3 18 (CH. 1–3)

P3E3T3 38 A3E3 19 (CH. 1–3)

P3E3T3 39 A3E3 20 (CH. 1–3)

One or more 1+N (N ≤15) EPS revertive protection scheme can be created (for more detail see point [3]
of para. 3.13.1 on page 322).
In case of EPS configuration the following configuration rules must be respected:

– Insert the protecting port card in a slot at the most left of of the protected port cards group.

– Insert the special protection access card (HPROT) associated to the protecting port card
following the rule reported in Table 20. on page 111 ( for example if the “protecting port card” has
been inserted in slot 24, the ” protection access card HPROT” must be inserted in slot 2).

The max. number of EPS groups is 8 i.e. 8 cards each protected 1+1 revertive. For each group a HPROT
access card is required therefore the max number of HPROT access cards is 8.
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Table 21. Relationship between P3E3T3 (3X34/45 Mbit/s Switchable unit) port card and A3T3 access
card (3X45 Mbit/s)


P3E3T3 24 A3T3 2 (CH. 1–3)

P3E3T3 25 A3T3 3 (CH. 1–3)

P3E3T3 26 A3T3 4 (CH. 1–3)

P3E3T3 27 A3T3 5 (CH. 1–3)

P3E3T3 28 A3T3 6 (CH. 1–3)

P3E3T3 29 A3T3 7 (CH. 1–3)

P3E3T3 30 A3T3 8 (CH. 1–3)

P3E3T3 31 A3T3 9 (CH. 1–3)

P3E3T3 32 A3T3 13 (CH. 1–3)

P3E3T3 33 A3T3 14 (CH. 1–3)

P3E3T3 34 A3T3 15 (CH. 1–3)

P3E3T3 35 A3T3 16 (CH. 1–3)

P3E3T3 36 A3T3 17 (CH. 1–3)

P3E3T3 37 A3T3 18 (CH. 1–3)

P3E3T3 38 A3T3 19 (CH. 1–3)

P3E3T3 39 A3T3 20 (CH. 1–3)




1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 22. Relationship between P4S1N, P4E4N, P4OC3 port card and A2S1 access card


P4E4N, P4S1N, P4OC3 24 A2S1 2 (CH. 3–4)

(CH. 1–2)

P4E4N, P4S1N, P4OC3 25 A2S1 3 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 26 A2S1 4 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 27 A2S1 5 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 28 A2S1 6 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 29 A2S1 7 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 30 A2S1 8 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 31 A2S1 9 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 32 A2S1 13 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 33 A2S1 14 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 34 A2S1 15 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 35 A2S1 16 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 36 A2S1 17 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 37 A2S1 18 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 38 A2S1 19 (CH. 3–4)
(CH. 1–2)

P4E4N, P4S1N, P4OC3 39 A2S1 20 (CH. 3–4)
(CH. 1–2)
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Table 23. Relationship between P16S1–4E port card and A12OS1E access card


P16S1–4E 24 A12OS1E 2+3

(CH. 1–4) (CH. 5 –16)

P16S1–4E 25 A12OS1E 3+4
(CH. 1–4) (CH. 5 –16)

P16S1–4E 26 A12OS1E 4+5
(CH. 1–4) (CH. 5 –16)

P16S1–4E 27 A12OS1E 5+6
(CH. 1–4) (CH. 5 –16)

P16S1–4E 28 A12OS1E 6+7
(CH. 1–4) (CH. 5 –16)

P16S1–4E 29 A12OS1E 7+8
(CH. 1–4) (CH. 5 –16)

P16S1–4E 30 A12OS1E 8+9
(CH. 1–4) (CH. 5 –16)

P16S1–4E 31 A12OS1E –––––––––
(CH. 1–4)

P16S1–4E 32 A12OS1E 13+14
(CH. 1–4) (CH. 5 –16)

P16S1–4E 33 A12OS1E 14+15
(CH. 1–4) (CH. 5 –16)

P16S1–4E 34 A12OS1E 15+16
(CH. 1–4) (CH. 5 –16)

P16S1–4E 35 A12OS1E 16+17
(CH. 1–4) (CH. 5 –16)

P16S1–4E 36 A12OS1E 17+18
(CH. 1–4) (CH. 5 –16)

P16S1–4E 37 A12OS1E 18 +19
(CH. 1–4) (CH. 5 –16)

P16S1–4E 38 A12OS1E 19 +20
(CH. 1–4) (CH. 5 –16)

P16S1–4E 39 A12OS1E –––––––––
(CH. 1–4)
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 24. Relationship between P16S1–4E port card and A12OS1SE access card


P16S1–4E 24 A12OS1SE 2

(CH. 1–4) (CH. 5 –16)

P16S1–4E 25 A12OS1SE 3
(CH. 1–4) (CH. 5 –16)

P16S1–4E 26 A12OS1SE 4
(CH. 1–4) (CH. 5 –16)

P16S1–4E 27 A12OS1SE 5
(CH. 1–4) (CH. 5 –16)

P16S1–4E 28 A12OS1SE 6
(CH. 1–4) (CH. 5 –16)

P16S1–4E 29 A12OS1SE 7
(CH. 1–4) (CH. 5 –16)

P16S1–4E 30 A12OS1SE 8
(CH. 1–4) (CH. 5 –16)

P16S1–4E 31 A12OS1SE 9
(CH. 1–4) (CH. 5 –16)

P16S1–4E 32 A12OS1SE 13
(CH. 1–4) (CH. 5 –16)

P16S1–4E 33 A12OS1SE 14
(CH. 1–4) (CH. 5 –16)

P16S1–4E 34 A12OS1SE 15
(CH. 1–4) (CH. 5 –16)

P16S1–4E 35 A12OS1SE 16
(CH. 1–4) (CH. 5 –16)

P16S1–4E 36 A12OS1SE 17
(CH. 1–4) (CH. 5 –16)

P16S1–4E 37 A12OS1SE 18
(CH. 1–4) (CH. 5 –16)

P16S1–4E 38 A12OS1SE 19
(CH. 1–4) (CH. 5 –16)

P16S1–4E 39 A12OS1SE 20
(CH. 1–4) (CH. 5 –16)
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 25. Relationship between P16S1–4E port card and A16ES1E access card


P16S1–4E 24 A16ES1E 2 (CH. 1 – 16)

P16S1–4E 25 A16ES1E 3 (CH. 1 – 16)

P16S1–4E 26 A16ES1E 4 (CH. 1 – 16)

P16S1–4E 27 A16ES1E 5 (CH. 1 – 16)

P16S1–4E 28 A16ES1E 6 (CH. 1 – 16)

P16S1–4E 29 A16ES1E 7 (CH. 1 – 16)

P16S1–4E 30 A16ES1E 8 (CH. 1 – 16)

P16S1–4E 31 A16ES1E 9 (CH. 1 – 16)

P16S1–4E 32 A16ES1E 13 (CH. 1 – 16)

P16S1–4E 33 A16ES1E 14 (CH. 1 – 16)

P16S1–4E 34 A16ES1E 15 (CH. 1 – 16)

P16S1–4E 35 A16ES1E 16 (CH. 1 – 16)

P16S1–4E 36 A16ES1E 17 (CH. 1 – 16)

P16S1–4E 37 A16ES1E 18 (CH. 1 – 16)

P16S1–4E 38 A16ES1E 19 (CH. 1 – 16)

P16S1–4E 39 A16ES1E 20 (CH. 1 – 16)




1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 26. Relationship between P4ES1N (4xSTM–1 Electrical) port card and A4ES1 access card.


P4ES1N 24 A4ES1 2 (CH. 1 to 4)

P4ES1N 25 A4ES1 3 (CH. 1 to 4)

P4ES1N 26 A4ES1 4 (CH. 1 to 4)

P4ES1N 27 A4ES1 5 (CH. 1 to 4)

P4ES1N 28 A4ES1 6 (CH. 1 to 4)

P4ES1N 29 A4ES1 7 (CH. 1 to 4)

P4ES1N 30 A4ES1 8 (CH. 1 to 4)

P4ES1N 31 A4ES1 9 (CH. 1 to 4)

P4ES1N 32 A4ES1 13 (CH. 1 to 4)

P4ES1N 33 A4ES1 14 (CH. 1 to 4)

P4ES1N 34 A4ES1 15 (CH. 1 to 4)

P4ES1N 35 A4ES1 16 (CH. 1 to 4)

P4ES1N 36 A4ES1 17 (CH. 1 to 4)

P4ES1N 37 A4ES1 18 (CH. 1 to 4)

P4ES1N 38 A4ES1 19 (CH. 1 to 4)

P4ES1N 39 A4ES1 20 (CH. 1 to 4)





The STM–4 and STM–16 high speed port card does not need Access Card because the physical
termination of the channel is on the port itself.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 27. Relationship between ETH–MB (11x10/100 Mb/s Ethernet) port card and ETH–ATX access
card.


ETH–MB (CH. 1 to 11) 24 ETH–ATX 2 (CH. 12 to 25)















1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 28. Relationship between ETH–MB (10/100Mb) port card and GETH–AG (1.25 Gb/s) access
card.

Port Card acronym Port Card Slot Access Card acronym Access Card Slot (N.B.)

ETH–MB 24 GETH–AG 2
(10/100 Mb CH.1 to 11) (Gigabit CH. 1 and 2)

N.B. The following channels are made available (max quantity) when GETH–AG is used in
conjunction with ETH–MB:

– up to two Gigabit Ethernet interface on the access card GETH–AG;in this configuration
only the two upper interfaces present on the access card can be used for Gbit Ethernet
application.
– up to eleven 10/100 Mbit Ethernet interfaces on the ETH–MB.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 29. Relationship between ISA ES–16 port card and and ETH–ATX access card.


ISA ES–16 24 ETH–ATX 2















1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 30. Relationship between ISA ES–16 port card and and GETH–AG access card.


ISA ES–16 24 GETH–AG 2















1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 31. Relationship between ISA–PR port card and 16FEA–PR or 2GBA–PR access cards.

Port Card acro- Port Card Slot Access Card Access Card Slot
nym acronym

ISA–PR 25–26 16FEA–PR or 2 –3 left
2GBA–PR 3–4 middle
4–5 right
ISA–PR 26–27 16FEA–PR or 3–4 left
5–6 right
6–7 right
7–8 right
8–9 right
9 – 10 right
2GBA–PR 9 – 10 middle
13 –14 right
ISA–PR 32–33 16FEA–PR or 12 – 13 left
14 – 15 right
15 – 16 right
16 – 17 right
17 – 18 right
18 –19 right
19 – 20 right
1AA 00014 0004 (9007) A4 – ALICE 04.10

20 – 21 right

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2.4 Units front view

The following paragraph show the access points (LEDs, switches etc.) present on each unit together with
legenda and meaning.

More in detail:

Paragraph 2.4.1 on page 124 shows the Port cards front view

Paragraph 2.4.2 on page 150 shows the Access cards front view

Paragraph 2.4.3 on page 173 shows the Fans subrack cover front view
1AA 00014 0004 (9007) A4 – ALICE 04.10

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2.4.1 Port cards front view

ACRONYM SLOTS

P63E1 24,27,30,32,33,36,39

P63E1N–M4 24,27,30,32,33,36,39

P3E3T3 24 to 39

P4ES1N 24 to 39

LEGENDA
3AL XXXXX AA

(1) Multicolor LED: (1)
xxxxxx

Red led – local unit alarm
Green led – in service unit
Orange led –unit in Stand–by (EPS schema)
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 35. PDH, SDH electrical ports front view

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ACRONYM SLOTS

P4S1N 24 to 39

P4E4N 24 to 39

P4OC3 24 to 39
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ (1)

ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ (2)
ÑÑÑ
ÑÑÑ
ÑÑÑ
ÑÑÑ
LEGENDA ÑÑÑ
ÑÑÑ
(1) Channel # 1 (N.B.)
(2) Channel # 2 (N.B.)
(3) Bicolor LED:
3AL XXXXX AA

Red led – local unit alarm (3)
xxxxxx


N.B.– The unit can be equipped with electrical or optical modules (see Figure 78. and Figure 79. )
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 36. 4 x STM–1, 4 x OC3 port : front view

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ACRONYM SLOTS

P16S1–4E 24 to 39

(1)

OUTPUT (2)

(3)
INPUT

(4)

(5)

LEGENDA

(1 to 4): are cavity for STM–1 / STM–4 SFP optical modules
(Refer to Figure 80. on page 169)
(6)
(5): Laser restart key

(6) Bicolor LED:
Red led – Local unit alarm
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 37. 16xSTM–1 – 4xSTM–4 port front view

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FC/PC SC/PC
ACRONYM SLOTS

S–4.1N 24 to 39

L–4.1N 24 to 39

L–4.2N 24 to 39

(2) (2)

INPUT
INPUT
OUTPUT
OUTPUT

LEGENDA

(1) Laser restart Key (1) (1)
(2) Channel #1
(3) Bicolor LED:
3AL XXXXX AA

3AL XXXXX AA

Green led – in service unit (3) (3)
xxxxxx

xxxxxx
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 38. STM–4 optical port front view

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ACRONYM SLOTS

P4S4N 25–26
28–29
34–35
37–38

(1)

(2)

LEGENDA:

(1) Channel # 1 (see NOTE)
(2) Channel # 2 (see NOTE)
(3) Bicolor LED:
3AL XXXXX AA

Green led – in service unit (3)

NOTE: the unit can be equipped with optical modules (see Figure 78. on page 167).
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 39. 4 x STM–4 port card – front view

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706

FC/PC SC/PC

ACRONYM SLOTS

25+26
S–16.1ND 28+29
34+35
37+38
(1) (1)
25+26
28+29
L–16.1ND 34+35
37+38

25+26 INPUT
28+29 OUTPUT
L–16.2ND 34+35
37+38

INPUT

OUTPUT

(2) (2)

LEGENDA

(1) Laser restart Key
(2) Channel #1
3AL XXXXX AA

3AL XXXXX AA

(3) (3)
xxxxxx

xxxxxx

(3) Bicolor LED:
xxxx

xxxx

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 40. STM–16 optical front view

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706

ACRONYM SLOTS

25+26
I –16.1ND 28+29
34+35
37+38 (1)

OUTPUT
INPUT

(2)

LEGENDA

(2) Channel #1
(3) Bicolor LED:
3AL XXXXX AA
xxxxxx

xxxx

(3)
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 41. I–16 PORT SFF (intra–office)

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ACRONYM SLOTS

O–16ES 24 to 39

(2)
OUTPUT

INPUT

Note: the cavities must be equipped with
SFP modules (refer to Figure 80. on page 169)

(1)

LEGENDA
(3)
(2) Optical Channel
(3) Bicolor LED:
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 42. STM–16 SFP SLIM port optical front view

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706

ATM4X4V2
ATM4X4 ATM4X4D3

ACRONYM SLOTS

ATM4X4
(1)
ATM4X4V2 24–39

ATM4X4D3

(2)

LEGENDA (3)
(4)
(1) Reset command Key (5)
(2) Channel #1 (N.B.) (6)
(3) Red LED – Urgent Alarm (Critical or Major) (7)
(4) (8) (1)
Red LED – Not Urgent alarm (Minor)
(5) Yellow LED – Alarm storing (Attended)
(6) Yellow LED – Abnormal condition (9)
(7) Yellow LED – Indicative Alarm (Warning)
(8) Lamp test push–button
(9) Factory use only
3AL XXXXX AA

3AL XXXXX AA

(10) Multicolor LED:
xxxxxx

xxxxxx

Red led – local unit alarm (INT) (10)

N.B.– The ATM4X4 unit can be equipped with electrical or optical STM–1 modules (see
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 78. and Figure 79. )

Figure 43. ATM 4X4 and ATM 4X4V2 card – front view

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706

ACRONYM SLOTS

ATM8x8 24 – 38
(1)

LEGENDA

(4)
(3) Red LED – Not Urgent alarm (Minor) (5)
(4) (6)
Yellow LED – Alarm storing (Attended) (7)
(5) Yellow LED – Abnormal condition
(8)
(8) Factory use only (9)
(9) Multicolor LED:
Red led – local unit alarm (INT)

Figure 44. ATM 8X8 card – front view
1AA 00014 0004 (9007) A4 – ALICE 04.10

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706

ACRONYM SLOTS

S–642E
I–641E 24 to 39

L–642E
(1)

(2)

INPUT

OUTPUT

LEGENDA

(2) Channel #1
(3) Bicolor LED: (3)
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 45. STM–64 optical port front view

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706

ACRONYM SLOTS

ETH–MB 24 to 39

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

Not used (12)

LEGENDA

(1) to (11) Ethernet Channels
(13)
(13) Bicolor LED
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 46. ISA – Ethernet port front view

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ACRONYM SLOTS

GETH–MB 24 to 39

OUTPUT
(1)

INPUT (2)

(3)

(4)

(6)

LEGENDA

(1) to (4) are Gigabit Ethernet channels
Ethernet Optical Modules (refer toFigure 80. on page 169)
(5)
(6): Factory use only

(5) Bicolor LED:
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 47. ISA– Gigabit ETHERNET board

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706

ACRONYM SLOTS

ES4–8FE 24 to 39

(11)

OUTPUT
(10)

INPUT (9)

(1)
Note: the cavities must be equipped with (2)
SFP modules (refer toFigure 80. on page 169)
(3)

(4)

(5)

(6)

LEGENDA
(7)

(1) to (8) 10/100 Ethernet channels (8)
(9) Gigabit Ethernet channel SFP

(10) Factory use only (12)

(11) Microprocessor restart Key

(12) Bicolor LED:

Figure 48. ISA – ES4–8FE port front view
1AA 00014 0004 (9007) A4 – ALICE 04.10

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706

ACRONYM SLOTS

ES1–8FE 24 to 39

(1) 1

(2)
2

(3)
3

(4)
4
RJ45 connectors
(5)
5

(6)
6

(7) 7

(8)
8

12
(9) 34
56
78

LEGENDA

(1) to (8) Ethernet channels
(10)
(9) Channel status indicators:
DBG
yellow : active channel
yellow blinking: channel with traffic (11)

(10) Not used
(12)
(12) Bicolor LED:
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 49. ISA – ES1–8FE port front view

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706

ACRONYM SLOTS

ES1–8FX 24 to 39

(1)

(2)

OUTPUT (3)

(4)
INPUT

(5)

(6)

(7)

(8)

LEGENDA (9)
(1): Reset button
(2 to 9): are cavity for Fast Ethernet optical SFP modules
(10)
(10) Bicolor LED:
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 50. ISA ES1–8FX front view

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706

ACRONYM SLOTS

ISA–ES16 24 to 39

(1)

MAJ (2)
MIN (3)
uP
(4)

(5)
ETH

(6)

LEGENDA

(7)
(1) Microprocessor reset key
(2) Red LED – Urgent Alarm (Major) RS232
(3) Yellow LED – Not Urgent alarm (Minor) not used in current release
(4) Microprocessor bicolor LED
(5) LED indicating the Ethernet port status (factory use only)
(6) Ethernet debugger port (factory use only)
(7) RS232 port (factory use only)

(8) Bicolor LED:
Red led – Local unit alarm (8)
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 51. ISA ES–16 front view

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706


ACRONYM SLOTS

PREA4ETH 24 to 39

(1)

(2)

(3)

(4) EthPort63

(5) EthPort62
RJ45 connectors
(6) EthPort61
LEGENDA
(1) Factory use only (7) EthPort60
(3) Not used
(4) to (7) Ethernet cahnnels (8)
(8) Bicolor LED
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 52. ISA– PRE_EA Matrix 4x Ethernet

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ACRONYM SLOTS

PREA1GBE 24 to 39

(1)

(2)

(3)

(4)
LEGENDA

(1) Factoy use only
(3) Not used
(4) The slot can be equipped with SFP Gigabit Ethernet optical (5)
module, see Figure 80. on page 169

(5) Bicolor LED
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 53. ISA– PRE_EA Matrix 1 x GB–ETH

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ACRONYM SLOTS

OUTPUT

ISA–PR 25 to 38

INPUT

LEGENDA (1)

(1) to (4) SFP optical connections for STM4 SDH ring interface.
From top to bottom W1, W2 for West ring interface, (2)
E1, E2 for East ring interface.
STM4 optical modules (refer to Figure 80. on page 169)
In the figure the four modules are included (3)

(5) OK led
Red led – Major / critical alarm (Major alarm on ISA–PR (4)
or slot alarms in access card or Major transmis–
sion alarms on access card. Access card slot
alarms stand for: Card Mismatch, Card unassigned,
Card Failure on POST _ Power On Self Test)
Red led blinking 50/50 – during POST failure (Power On Self Test)
Red led blinking 20/80 – Card Mismatch
Yellow led – Minor alarm (5)
Yellow led blinking 50/50 – Maintenance in progress (loopbacks..)
Green led – OK status (no alarms)
Green led blinking 50/50 – ISA–PR is in initialization process (6)
(following power–on or reset)
Led OFF – card not powered
(7)
(6) ETH– Ethernet management interface RJ45 connector
For local Craft Terminal or Network Management System connections
(7) RS 232 – RJ45 connector For internal factory use (8)
(8) Microprocessor restart key
(9)
(9) Active led
Green led – card is powered
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 54. ISA– PR Matrix 4x4STM4 PLUG–IN

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ACRONYM SLOTS

COWLA2 24 to 39

(1)

1st Channel

(2)

(3)

2nd Channel

(4)
LEGENDA

(1) Slot for ”Black White or ”Colored” SFP module

(2) Slot for ”Black White” or ”Colored” SFP module


Note: the cavities must be equipped with (5)
SFP modules (refer toFigure 80. on page 169)

(5) Active led
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 55. COWLA2 front view

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ACRONYM SLOTS

25+26
28+29
4XANYC 34+35
37+38
32+33

(3)

(1)

LEGENDA:

(1) Channel #1
(Low speed 4XANY acronym modules: OL–IN, OL–MM) (4)
(2) Channel #2
(Low speed 4XANY acronym modules: OL–IN, OL–MM)
(3) Channel #3
(Low speed 4XANY acronym modules: OL–IN, OL–MM
OR (2)
High speed 4XANY acronym modules: OH–I, OH–MM)

(4) Channel #4
(Low speed 4XANY acronym modules: OL–IN, OL–MM
OR
High speed 4XANY acronym modules: OH–I, OH–MM)


Note: The allowed mixed configuration are reported on
paragraph 3.10 on page 293
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 56. 4xANY Host C

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706

ACRONYM SLOTS

MATRIXE 23,40

(2)

LEGENDA
(1) Reset command key (1)
(2) RJ45 for factory use only
(3)
(3) Multicolor LED:
Orange led – unit in Stand–by (EPS schema)
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 57. MATRIXE card

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706

ACRONYM SLOTS

PQ2/EQC 22

(1)

(2a)

(2)

LEGENDA

(1) Reset command key
(3)
(2) Personal Computer Connector (F interface RS–232)
(2a) Personal Computer Connector (USB interface)
(not operative in current release)
(4)
(3) RJ45 for factory use only
(5)
(5) Red LED – Not Urgent ( Minor) (7)
(6) Yellow LED – Alarm storing (Attended) (8)
(7) Yellow LED – Abnormal condition
(9)
(10) Alarm storing push–botton (Attended)
(11) Green LED – When on it means active unit (10)
(11)
(12) Bicolor LED:
3AL XXXXX AA

(12)
xxxxxx

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 58. EQUICO (PQ2/EQC)

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ACRONYM SLOTS

CONGI 10, 12

(1)

(2)

(3)

(4)

LEGENDA

(1) Power
(2) Housekeeping and remote alarm
(3) Rack lamps (not used on CONGI in slot 12) (5)
(4) QMD (Q2) (not used on CONGI in slot 12)
(5) I/O BNC for Q3 10 base 2 (not used on CONGI in slot 12)
(6) RJ45 for Q3 10 base T (not used on CONGI in slot 12) (6)
(7) Bicolor LED:
3AL XXXXX AA

Green led – in service unit (7)
xxxxxx
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 59. Control and General interface

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ACRONYM SLOTS

SERVICE 11

J1 J5
J2 J6
(1)
J3 J7

J4 J8
LEGENDA

(1) I/O auxiliary 2 Mbit/s Channels G.703

J1 – 2 Mbit/s Channel Output 1
J2 – 2 Mbit/s Channel Input 1
J5 – 2Mbit/s Channel Output 2 (2)
J6 – 2Mbit/s Channel Input 2
I/O 2 MHz Synchronous interfaces
J3 – 2 MHz Output 1 (T4A) or 2 Mbit/s Output (T5A)
J4 – 2 MHz Input 1 (T3A) or 2 Mbit/s Input (T6A)
J7 – 2 MHz Output 2 (T4B) or 2 Mbit/s Output (T5B)
J8 – 2 MHz Input 2 (T3B) or 2 Mbit/s Input (T6B)
(2) Auxiliary channels: (3)
4 channel RS–232
4 channel V.11 64 Kbit/s
4 channel G.703 64 Kbit/s (4)

(3) Four wire telephone extension point
(RJ45)
(4) Four wire telephone extension point (5)
(RJ11)
(5) Z1–Z8 EOW zone selection LEDs (N.B.1) (6) L1 L2

(6) L1–L2 LEDS status for selective call (N.B.2) (7)
(8)
(7) Telephone jack
(9)
(8) Line seizure Key
(10)
(9) EOW zone selection (N.B.1)
3AL XXXXX AA

xxxxxx

(11) Bicolor LED:

N.B.1 Only one Zone is operative.
1AA 00014 0004 (9007) A4 – ALICE 04.10

N.B.2 For details see Table 59. on page 578 and Table 60. on page 578

Figure 60. SERVICE interface

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706

2.4.2 Access cards front view

ACRONYM SLOTS

A21E1 1 to 9,13 to21

(1)
(2)
(3)
(4)
(5)

(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)

LEGENDA (19)
(20)

(1) – (21) 2 Mbit/s data signals (21)

(22) Bicolor LED:
3AL XXXXX AA

Red led – local unit alarm (INT) INPUT OUTPUT
xxxxxx

(22)
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 61. 21 x 2 Mbit/s 75 ohm access card 1.0/2.3 connectors

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ACRONYM SLOTS

A21E1 1 to 9,13 to21

(1)

(2)

LEGENDA (3)

(1) Channels # 1 to 7 connector
(2) Channels # 8 to 14 connector
(3) Channels #15 to 21 connector
(4) Bicolor LED:
3AL XXXXX AA

(4)
xxxxxx

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 62. 21 X 2 Mbit/s 120 Ohm access card

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706

ACRONYM SLOTS

A3E3 2 to 9, 13 to 20

INPUT (1)
OUTPUT

INPUT (2)
OUTPUT

INPUT
(3)
OUTPUT

LEGENDA

(1) Channel #1
(2) Channel #2
(3) Channel #3

(4) Bicolor LED:
3AL XXXXX AA

xxxxxx

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 63. 3 X 34 Mbit/s 75 ohm access card

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706

ACRONYM SLOTS

A3T3 2 to 9, 13 to 20

INPUT (1)
OUTPUT

INPUT (2)
OUTPUT

INPUT (3)
OUTPUT

LEGENDA

(1) Channel #1
(2) Channel #2
(3) Channel #3

(4) Bicolor LED:
3AL XXXXX AA

xxxxxx

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 64. 3 X 45 Mbit/s 75 ohm access card

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ACRONYM SLOTS

A4ES1 2 to 9, 13 to20

INPUT
(1)
OUTPUT

INPUT
(2)
OUTPUT

INPUT
(3)
OUTPUT

LEGENDA
INPUT
(4)
(1) Channel #1 OUTPUT
(2) Channel #2
(3) Channel #3
(4) Channel #4
3AL XXXXX AA

(5)
xxxxxx

(5) Bicolor LED:
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 65. 4 X STM–1 access card

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
(1)

03
HPROT

LEGENDA
ACRONYM

Bicolor LED:
SLOTS

2 to 9, 13 to20

Figure 66. High Speed protection – front view

706
xxxxxx

3AL 91669 AA AA
3AL XXXXX AA

(1)

155 / 706

ACRONYM SLOTS

A2S1 2 to 9, 13 to20

(1)

(2)

LEGENDA

(1) Channel #3 (N.B.)
(2) Channel #4 (N.B.)
3AL XXXXX AA

xxxxxx


N.B.– The unit can be equipped with electrical or optical modules (see Figure 78. and Figure 79. )
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 67. 2 x 140/STM–1 O/E adapter (access card)– front view

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ACRONYM SLOTS

A12OS1E 2 to 8, 13 to 20

OUTPUT

INPUT

(1)

LEGENDA

(1): are cavity for STM–1 SFP optical modules;
12 channels can be managed

(2): Bicolor LED:
3AL XXXXX AA

xxxxxx

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 68. Optical access 12xSTM1 unit front view

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ACRONYM SLOTS

A12OS1SE 2 to 9, 13 to20

OUTPUT

INPUT

(1)

LEGENDA

(1): are cavity for STM–1 SFP optical modules;
12 channels can be managed

(2): Bicolor LED:
3AL XXXXX AA

xxxxxx

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 69. Optical access 12xSTM1 SLIM unit front view

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706

ACRONYM SLOTS

A16ES1E 2 to 9, 13 to20

(1)
(2)
(3)
(4)
(5)

(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)

INPUT OUTPUT
LEGENDA

(1) to (16): STM–1 input output electrical channels
3AL XXXXX AA

(2): Bicolor LED: (2)
xxxxxx

1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 70. Electrical access 16xSTM1 unit front view

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706

ACRONYM SLOTS

ETH–ATX 2 to 9, 13 to20

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)
LEGENDA

(15)
(1) to (14) Ethernet channels

(15) Bicolor LED
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 71. ISA – Ethernet access front view

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ACRONYM SLOTS

GETH–AG 2 to 9, 13 to20

OUTPUT

INPUT

(1)

(2)

(3)

(4)

LEGENDA

(1) to (4) are Gigabit Ethernet channels
Ethernet Optical Modules (refer to Figure 80. on page 169) (5)
Only the two upper cavities can be equipped when
the GHETH–AG is used in cojunction with ETH–MB

(5) Bicolor LED
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 72. ISA – Gigabit Ethernet access card front view

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706

ACRONYM SLOTS

2GBA–PR 2 to 8

13 to 20

OUTPUT

INPUT

LEGENDA

(1) and (2) are Gigabit ethernet channels
Ethernet Optical Modules (refer toFigure 80. on page 169)
In the figure the two modules are included

(3) and (4) Link led, one for each ethernet channel
Red led – any port related alarm
Green led – link up
(1)

(5) OK led
Red led – Major / critical alarm
Red led blinking 50/50 – during POST (Power On Self Test) failure (2)

Yellow led – Minor alarm
Yellow led blinking 50/50 – maintenance
Green led – OK status (no alarms) (3)
Green led blinking 50/50 – during init
(4)
Green led blinking 20/80 – Card is Unassigned (i.e.not yet
approved by NMS) (5)
(6)
(6) Active led
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 73. ISA PR 2XGBE 1000 access card front view

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(2)

ACRONYM SLOTS

2 to 8 (3)
16FEA–PR
13 to 20

LEGENDA

(1) 16 x 10/100 fast ethernet channels
(2) Link led, one for each channel
Green led – link up
Led off – link down
(3) Activity led, one for each ethernet channel
Yellow led – Rx/Tx in progress (1)
Led off – link silent

(4) OK led
Red led – Major / critical alarm
Red led blinking 50/50 – during POST (Power On Self Test) failure

Yellow led – Minor alarm
Yellow led blinking 50/50 – maintenance
Green led – OK status (no alarms)
Green led blinking 50/50 – during init
Green led blinking 20/80 – Card is Unassigned (i.e.not yet
approved by NMS)

(5) Active led
(4)
(5)
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 74. ISA PR16XETH 10/100 access card front view

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706

ACRONYM SLOTS

COADM1 1 to 8
13 to 20

(1)

(2)

LEGENDA
(3)

(1) Line Side Fiber Connectors

(2) Add/Drop Channel Fiber Connectors
(4)
(3) Pass–through Fiber Connectors

(4) Bicolor LED
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 75. COADM1 front view

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706

ACRONYM SLOTS

COADM2 1 to 8
13 to 20

(1)

(3)
(2)

LEGENDA (4)


(2) Add/Drop Channel #1 Fiber Connectors

(3) Add/Drop Channel #2 Fiber Connectors

(4) Pass–through Fiber Connectors (5)

(5) Bicolor LED
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 76. COADM2 front view

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706

ACRONYM SLOTS

COMDX8 1 to 8
13 to 20

(1)

(2) (3)

(4) (5)

LEGENDA (6) (7)

(2) Channel 1470 nm Fiber Connectors
(8) (9)
(8) Channel 1590 nm Fiber Connectors (10)

(10) Bicolor LED
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 77. COMDX8 front view

ED 03

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706

STM–1 module EQUIPPED
acronym on CARDS

IS–1.1 SC/PC

P4S1N
IL–1.1 P4E4N
ATM4X4
IL–1.2 A2S1 INPUT
P4OC3 OUTPUT
MM1
(SC/PC only)

STM–4 module EQUIPPED
acronym on CARDS
Laser restart key
IS–4.1
P4S4N
IL–4.1

IL–4.2

FC/PC
LC

INPUT
Laser restart key
OUTPUT

INPUT

OUTPUT
Laser restart key
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 78. STM–1/STM–4 optical module front view

ED 03

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03
ICMI
ACRONYM

A2S1
P4E4N
P4S1N
P4OC3

ATM4X4
EQUIPPED
ON PORTS

INPUT

OUTPUT

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Figure 79. STM–1 or 140 Mbit/s electrical module front view

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SFP MODULE EQUIPPED ON
ACRONYM PORT/ACCESS
GETH–MB

GETH–AG
1000B ES4–8FE
2GBA–PR
PREA1GBE

100B ES1–8FX

SS–161

SL–161
O–16ES
SL–162
COWLA2
SS–162C

SL–162C

SS–41
ISA–PR
SL–4.1 P16S1–4E SFP Module

SL–4.2

SS–11
P16S1–4E OUTPUT
SL–11 A12OS1E
A12OS1SE
SL–12

INPUT

Optical cables
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Figure 80. Relationship between SFP modules and housing boards

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03
OH–I
acronym

OL–IN

OL–MM
OH–MM

INPUT
OUTPUT
4XANYC
4XANY modules EQUIPPED
on CARDS

Figure 81. 4XANY plug–in module

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ACRONYM SLOTS
SC/PC FC/PC

2 to 8 INPUT

BST10

13 to 19
OUTPUT
2 to 8
BST15 13 to 19

2 to 8
BST17
13 to 19

(2) (2)

INPUT
OUTPUT

(1) (1)

LEGENDA:
(1) Cover remove
(2) IN / OUT Main Signal
(3) Yellow LED: active Shut Down
(4) Bicolor LED: (3) (3)
Red led – Local unit alarm (4) (4)

Figure 82. Optical Booster card front view
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ACRONYM SLOTS
SC/PC FC/PC

2 to 8

PR16

13 to 19

INPUT

OUTPUT

INPUT
OUTPUT

(1) (1)

(2)

LEGENDA: (2)

(1) Cover remove
(2) IN / OUT Main Signal Not used Not used
(3) Yellow LED: active Shut Down
(4) Bicolor LED: (3) (3)
Red led – Local unit alarm (4) (4)

Figure 83. PREAMPLIFIER 2.5 GB/S front view
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2.4.3 FAN subrack cover front view

(1)

(2) (4) (5) (6) (3)

LEGENDA

(1) MULTICOLOR LED:
Orange led – temperature major than 55 C

(2) Battery A connector
(3) Battery B connector
(4) Not used

(5) Alarms connector for 1660SM

(6) Not used
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Figure 84. 19” Fans subrack cover front view

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2.4.4 Assembled Fans unit

(1)

(2)

(1) MULTICOLOR LED:
Orange led – temperature major than 55 C

(2) Not used

Figure 85. Assembled Fans unit front view
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3 FUNCTIONAL DESCRIPTION

3.1 General description

From Figure 89. on page 187 to Figure 96. on page 194 illustrates, in block diagram form, the units
employed in the 1660SM and the general operating functions:

• EQUICOE unit (also called PQ2/EQC)

The unit provides the following functionality:

– Equipment Controller (EC) function

– F interface for Local Craft Terminal

– USB interface for Local Craft Terminal (not operative in current release)

– Communication with the Operation System (O.S) through different interface (DCC, QB3
etc.)

• MATRIXE unit


– Matrix that performs HPC, LPC and protection functions

– Synchronization functions

– Shelf Controller (SC) function

• 2 or 34/45 Mbit/s PDH Electrical unit

Different PDH Electrical unit are available:

– ”2 Mbit/s PDH Electrical unit” provides the interface for the asynchronous mapping G.703
2 Mbit/s signals into SDH VC12s. Each unit supports 63 interface.
The unit is the same for 75 Ω and 120 Ω. applications; impedance match is performed at
the “access card” level.

– ”34 Mbit/s / 45 Mbit/s unit” provides the interface for the asynchronous mapping of G.703
34 Mbit/s or 45 Mbit/s signals into SDH VC–3s. Each unit supports 3 interface .
The selection of the working mode (3 x 34 Mb/s or 3 x 45 Mb/s) is controlled via software.
Two different access module are used for the 34 Mb/s and 45 Mb/s applications.

For both units the Lower Order Interface (LOI) block includes PPI (physically on the Access
Card), LPA, LPT functionality (see Figure 86. on page 175 and Figure 89. on page 187)

LOI

PPI LPA LPT
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Figure 86. LOI block diagram

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• 4 x 140 Electrical or 155 Mbit/s E/O unit

The unit provide four 140 PDH electrical or 155 Mbit/s STM–1 Electrical/Optical interfaces.
The selection of the working mode (per port) is controlled via software:

– When the 140 Mbit/s mode is selected, the port provides an interface for the asynchronous

mapping of G.703 140 Mbit/s signals into SDH VC–4. The functions performed in the High
Order Interface (HOI) block are: PPI (Physically on the Access Card), LPA, HPT(see
Figure 87. on page 176 and Figure 89. on page 187. Two of the four PPI blocks are
present on the board, the other two are on the Access Card.
HOI

PPI LPA HPT

Figure 87. HOI block diagram

– When the 155 Mbit/s STM–1 mode is selected, the VC–4 can either be unstructured or
structured into lower order VCs. The functions performed are TTF and HOA (see
Figure 88. on page 176). Two of the four SPI blocks are present on the board, the other
two are on the Access Card.
TTF

SPI RST MST MSP MSA

HOA

HPT HPA

Figure 88. TTF and HOA block diagram

• 4 x155 Mbit/s Electrical/Optical unit

The unit provides four bidirectional STM–1 electrical or optical interfaces. For each STM–1, the
VC–4 can either be unstructured or structured into lower order VCs. The function performed are
TTF and HOA ( see Figure 88. on page 176 and Figure 89. on page 187.).
Two of the four SPI blocks are present on the board, the other two are on the Access Card.
Any combination of electrical or optical (short or long haul) is possible on the same unit.

• 4 x155 Mbit/s Electrical unit

The unit provides four bidirectional STM–1 electrical interfaces. The four SPI blocks are
available on Access Card. For each STM–1, the VC–4 can either be unstructured or structured
into lower order VCs. The function performed are TTF and HOA ( see Figure 88. on page 176
and Figure 89. on page 187.).
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• 16 x155 Mbit/s Electrical/Optical – 4xSTM–4 unit

The board P16S1–4E provides either 4 STM–4 optical interfaces or 16 STM–1
Optical/Electrical interfaces (along with the Optical/Electrical Access Board) (refer to

Figure 91. on page 189).

The P16S1–4E board along with A12OS1E or A12OS1SE Optical Access board allows the
transport of 16 optical STM1 streams by means of 16 SFP optical transceivers.
On the P16S1–4E there are four of 16 SFP transceivers, while in the A12OS1E card there are
the other 12 transceivers.
On the P16S1–4E board the SFP transceivers can work at both the bit rate of 155 and 622 Mb/s
for both Short Haul and Long Haul applications.

The P16S1–4E board along with the A16ES1E Electrical Access card allows the transport of
16 electrical STM–1 streams. All the 16 electrical line interface devices are present in the
A16ES1E board.

• 1 X STM–4 Optical unit

The 1 x STM–4 optical unit provide one STM–4 optical interface; the function performed are TTF
and HOA. Several short and long haul types are available.

• 1 X STM–16 optical unit

The 1 x STM–16 optical unit provide one STM–16 optical interface (on front panel); the function
performed are TTF and HOA. Several short and long haul types are available.

“Colored” versions are available for direct interworking with WDM equipment without
intermediate wavelength adapters.

STM–16 SLIM short haul port are also available (one slot wide)

• 1 X STM–64 optical unit

The 1 x STM–64 optical unit provide one STM–64 optical interface (on front panel); the function
performed are TTF and HOA. Short haul and intra–office interface types are available.

• 4 X OC3 AU3/TU3 Conversion unit

This board can manage up to 4 x OC–3 (SONET) streams. The board hosts up to 2 interfaces
into the front panel.
The other two interfaces can be hosted in the Access area using the relevant access card that
must be equipped in the slot associated to the corresponding traffic unit slot (refer to Table 22.
on page 113).
Each combination of interfaces (electrical, S.1.1,L.1.1,..) can be equipped in the same board.
On OC–3 interface the Sonet mapping is mange so the RS and MS sections are terminated,
the 3 AU3 are processed to extract or insert the 3 VC3. This unit performs the AU3/TU3
conversion , which allows the transport in SDH network of Sonet VC3 traffic.
The conversion is performed on OC–3 interface: the 3 VC3 are extracted then re–mapped in
SDH VC4 container and this container is passed to the matrix where it is managed as a
structured VC4. The OH byte of RS and MS section are managed according SDH ITU standard.
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• ISA – ATM4X4, ATM4X4V2, ATM4X4D3

Three boards types are available:

– ATM4X4 with a max. number of 16 TPs configurable among SDH VC4, SDH VC3, SDH

VC12, PDH 2M and PDH 34M.

– ATM4X4V2 with a max number. of 252 TPs configurable among SDH VC4, SDH VC3,
SDH VC12, PDH 2M, PDH 34M and PDH 45M.

– ATM4X4D3 with a max number. of 16 TPs configurable among SDH VC4, SDH VC3, SDH
VC12, PDH 2M, PDH 34M and PDH 45M.

They are a one slot wide boards that integrate an ATM switch functionality.
Only the ATM4X4 BOARD also includes a STM–1 local access port on the front panel.
For both throughput capacity towards backpanel is 622 Mbit/s.
ATM traffic control functions, such as “Shaping” and “Policing” (which are needed to avoid
network congestion) are supported.

• ISA – ATM MATRIX 8X8

It is a two slot wide board that integrate an ATM switch functionality.
16+16 TPs are configurable among SDH VC4,SDH VC4–C, SDH VC3, SDH VC12, PDH 2M
and PDH 34M.
The throughput capacity is 1.2 Gbit/s.
ATM traffic control functions, such as “Shaping” and “Policing” (which are needed to avoid
network congestion) are supported.

• ISA – PR_EA MATRIX

1660SM can host two types of PR_EA matrix (generically ISA PR_EA board):
– in the first version, it hosts a 4 x 10/100 BaseT Fast Ethernet module and the total traffic
throughput is 1 Gb/s, in which 622Mb/s are contributed by the SDH matrix, and 400 Mb/s
contributed by the 4 Fast Ethernet local ports.
– in the second version, it hosts a 1 x 1Gigabit Ethernet module and the total traffic
throughput is 1.8 Gb/s, in which 622Mb/s are contributed by the SDH matrix, and 1.25 Gb/s
contributed by the Gb Ethernet local port.

The following table summarizes the interfaces that can accede to the MPLS functions:

Table 32. Interfaces acceding to the MPLS functions

TYPE OF INTERFACE CONTAINER NOTES

SDH VC–12, VC–3, VC–4

PDH E1, E3, T3 not available in current rel.

Ethernet (E, FE, GE) MAC 802.3 also “802.1p/q Tagged”
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• ISA – PR MATRIX

1660SM can host PR matrix (generically ISA–PR board) and relevant access cards:

It provides a shared carrier–class Ethernet Packet Ring embedded, in a flexible manner over SDH

VCs (with VC–4–nv framing), either physically or logically into the SDH infrastructure.
The ISA–PR is a Layer 2 MPLS–based statistical packet switch with Ethernet and GBE interfaces
operating a Resilient Packet Ring transported over multiple STM–4 standard interfaces.

The ISA–PR port card is a RPR switch with four STM–4 interfaces providing 6.5 Gbps packet
throughput with a provisionable trunk capacity of 1.2 Gbps both in East and West directions.

On its front plate a RJ45 connector provides the connection toward the Local Craft Terminal
or the Operation System.

The following table summarizes the interfaces that can accede to the PR functions:


SDH VC–4


Two access card types are availale (also in mixed configuration):

– 16 FEA–PR – Fast ETHERNET access card

10/100 Ethernet Access card supporting sixteen (16) 10/100 Fast Ethernet interfaces.
Up to four 16FEA–PR access cards can be equipped.

– 2 GBA–PR – GigaBit Ethernet access card

GigaBit Ethernet Access card supporting two (2) GigaBit Ethernet interfaces.

• ISA – Fast ETHERNET unit

The unit is able to provide 25 x 10/100 Mb/s Ethernet interfaces to allow LAN–to–LAN
connections.
In the main port are provided 11 connectors on the front panel of the unit. The main port can
be used in conjunction with the relevant access module (ETH–ATX) which is able to provide 14
additional 10/100 Mb/s Ethernet interfaces.

Ethernet frames are mapped over an SDH VC (VC–12, VC–3, VC–4) with a max. throughput
of 622 Mbt/s toward the backplane.

Each physical interface can independently be mapped into the relevant VC according to the
required bit rate.

N.B. The Fast Ethernet unit 10/100 Mb/s can be also used in conjunction with the Gigabit
Ethernet Access card (GETH–AG); in this configuration the Fast Ethernet unit can
handle the following interfaces:

– two Gbit Ethernet interfaces (on the access card GETH–AG); Ethernet frames
are mapped over a single SDH VC–4.
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– 11 Interfaces 10/100 Mb/s Ethernet interfaces (on the Main board)

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• ISA – Gigabit ETHERNET unit

The unit is able to manage 4 Gigabit Ethernet interfaces on the main board.

• ISA ES1–8FE, ISA ES1–8FX and ISA ES4–8FE

The boards mainly work as a LAN switching, and in particular they provide the service of
connecting two LANs as point to point connection between two routers or switches through a
SDH network.

ISA ES1–8FE and ISA ES4–8FE units have eight 10/100 Mbit/s Ethernet interfaces on the front
panel; the Ethernet traffic, opportunely mapped in the SDH transport structures, is then sent
toward the SDH matrix via the back plane with a STM–1 equivalent throughput .

ES1–8FX board has eight Small Form factor Pluggeable module supporting optical Fast
Ethernet Interfaces on the front panel.

ES4–8FE board has also one Small Form factor Pluggeable module supporting a Gigabit
Ethernet Interface on the front panel.

ISA–ES1 and ISA ES4 series module can classify ETH traffic according to a wide set of standard
specified criteria in order to provide a feature reach set of capability. Each classified traffic is
referred as a classified flow.
Classification criteria are the following:

– Port (Physical ETH or ETH over SDH)
– IEEE 802.1Q (VLAN tagging)
– IEEE 802.1p (ETH frame priority)
– IEEE 802.3 Source/Destination MAC address (also according to IEEE 802.1ad)

Hereafter are reported the available trunking capacity:

– ISA–ES1 has 1 VC–4 of bandwidth available

• ISA ES16

As for ISA ES1 and ISA ES4 the boards ISA ES16 mainly work as a LAN switching, and in
particular they provide the service of connecting two LANs as point to point connection between
two routers or switches through a SDH network.

ISA–ES16 is a port less card that can use specific access modules:

– 14 x FE access module: 14 x Fast Ethernet ports (10/100 Base T)

– 4 x GE access module: 4 x GB Ethernet ports with SFP plugs

ISA ES16 Classification criteria are the following:

– Port (Physical ETH or ETH over SDH)
– IEEE 802.1p (ETH frame priority)
– IEEE 802.3 Source/Destination MAC address (also according to IEEE 802.1ad)
– MPLS label (according to IETF Martini draft ETH over MPLS)
– IP–TOS/DSCP fields
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Hereafter are reported the available trunking capacity:

– ISA–ES16 has up to 16 VC–4 of bandwidth available

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• Double channel multirate transponder (COWLA2) unit

This unit realizes both the ’wavelength assignment’ and the ’wavelength regeneration’ on the
2 separate channels supported, according to the type of optical interface (’colored’ CWDM or

BW) equipped.

Pluggable CoarseWDM/BW SFP optical modules are equipped in order to allow maximum
flexibility in channel configuration.
8 possible Coarse WDM modules with SFP transceiver are available with a throughput up to
2.5Gb/s. CWDM transceiver are ITU–T grid compliant (1470–1490–1510–
1530–1550–1570–1590–1610 nm).
The configuration of COWLA2 requires the operator to specify for each module the transported
client signal and if the module is colored or BW.
The transponder unit supports the ’3R’ functionality for the following signal types:

– FDDI (125 Mb/s); not operative in current release

– Fast Ethernet (125 Mb/s); not operative in current release

– STM1/OC3; not operative in current release

– Escon (200 Mb/s); not operative in current release

– Digital Video (270 Mb/s); not operative in current release


– Fiber Channel (1.0625 Gb/s); not operative in current release

– FICON (1.0625 Gb/s); not operative in current release

– Gb Ethernet (1.25 Gb/s); not operative in current release

– 2 Fiber Channel (2.125 Gb/s); not operative in current release

– STM16/OC48;

– 2 Gb Ethernet (2.5 Gb/s); not operative in current release

– STM16 w/ FEC (2.667 Gb/s) not operative in current release

• OADM1 (COADM1) unit

COADM1 unit realizes wavelengths multi–demultiplexing allowing to add/drop 1 channel out of
the 8 supported according to CWDM grid and the pass–through of remaining WDM channels
not terminated.
One specific item per ITU–T channel is foreseen: 1470 – 1490 – 1510 – 1530 – 1550 – 1570
– 1590 – 1610 nm.
The functionality of the board has to be considered for ring application, and performing ’one
side’ channel termination: thus, two separate boards are required at a node of the ring in order
to achieve the complete OADM functionality.
’Loss of Signal’ detection on CWDM optical signal received is not managed.
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• OADM2 (COADM2) unit

COADM2 board realizes wavelengths multi–demultiplexing allowing to add/drop 2 channels out
of the 8 supported according to CWDM grid and the pass–through of remaining WDM channels

not terminated.

Four specific items are foreseen, considering to support the termination of two adjacent
wavelengths per item:

– 1470 – 1490 nm;

– 1510 – 1530 nm;

– 1550 – 1570 nm;

– 1590 – 1610 nm.

The functionality of the board has to be considered for ring application, and performing ’one
side’ channel termination: thus, two separate boards are required at a node of the ring in order
to achieve the complete OADM functionality.

• Mux/Demux 8 ch (COMDX8) unit

MUX/DEMUX board realizes wavelengths multi–demultiplexing on the whole group of 8
CWDM channels supported.
8 CWDM ITU–T grid compliant filters are equipped on the MUX/DEMUX module: 1470, 1490,
1510, 1530, 1550, 1570, 1590, 1610 nm.

The functionality of the board can be considered both for linear and ring application; contrary
to COADMn boards, no ’pass–through’ link is provided, then pass–through of wavelengths not
terminated must be realized on each single wavelength.
In ’ring’ application, the board performs ’one side’ channels termination: thus, two separate
boards are required at a node of the ring in order to achieve the complete functionality.

• 4 x ANY HOST C unit

The 4xANY board is a Time Division Multiplexer concentrator that performs a bidirectional
interface between up to 4 clients data and the MATRIX board (via backpanel) through up to 16
VC–4.

A mixing of SDH and Data Services is possible. Multiplexing scheme delivers a fully compliant
SDH frame.

The board is two slot wide and can be plugged in the enhanced slot( 2526, 2829, 3435,
3738) and not enhanced slot (3031, 3233).
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Up to 4 client signals can be independently handled among the following types (for details and
restriction refer to paragraph 3.10 on page 293) :

• Fast Ethernet

• FDDI (125Mbps)

• ESCON (200Mbps)

• Digital Video (270Mbps)

• Fiber Channel (1.0625Gbps)

• FICON (1.0625Gbps)

• Gigabit Ethernet (1.25Gbps)

• SERVICE unit


– Auxiliary channels

– Engineering Order Wire (EOW)

– 2 MHz Input/Output

• CONGI unit


– Power Supply

– QB3 Interface

– Housekeeping and remote alarm

– Q2/RQ2 interface

• Access Cards

They provides the physical interface for the different types of signals

• Protection Card

The unit allows the EPS protection for 34/45Mbit/s and 155 Mbit/s electrical unit.

• BOOSTER

To improve the span length of STM–N interfaces for single channel application, the Optical
booster unit can be used. This unit can be plug–in in the access area. Three integrated boosters
are available, according to the relevant gain values: 10dbm, 15dBm and 17dBm.

• OPTICAL PREAMPLIFIER

This unit can be plug–in in the access area. It is used in conjunction with the optical booster to
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The functions carried out by the unit can be splitted into the following sub–systems:

[1] Connections sub–system (see paragraph 3.2 on page 198)

[2] Signal management sub–system (see paragraph 3.3 on page 200)

[3] ISA (Integrated Service Adapter) sub–system ( refer to paragraph 3.4 on page 223)

[4] 4xANY HOST C subs–system (see paragraph 3.10 on page 293)

[5] Coarse WDM sub–system (refer to paragraph 3.11 on page 300)

[6] Controller sub–system (see paragraph 3.12 on page 315)

[7] Protection sub–system (see paragraph 3.13 on page 321)

[8] Synchronization sub–system (see paragraph 3.14 on page 363)

[9] Auxiliary sub–system (see paragraph 3.15 on page 365)

[10] Power supply sub–system (see paragraph 3.16 on page 367)

[11] Remote inventory sub–system (see paragraph 3.17 on page 370)

On the following paragraphs a detailed description of each sub–system is given.

Each logical function does not correspond necessarily to a physical card but can be distributed over more
than one card. On the other side, one card can house more than one function.

For each sub–system the list of the involved cards and a brief abstract of the function detailed on the
following paragraphs is reported in Table 33. on page 185.

Notice that the On Board Power Supply (DC/DC converter in Figure 89. on page 187) is present on each
card and that the Controller function is centralized ( EC and SC).
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Table 33. Sub–systems involved cards
Sub–system Card involved Short description
Connections MATRIXE and ports On the para. is explained how the signal is

managed between the port and the MATRIXE

Signal management all the ports (LS and HS) On the para. it is explained how the PDH, SDH
Access Modules and SONET signals are elaborated on the
ports.
The description in compliancy with the G.783
ITU–T Rec.

On the paragraph are explained the ATM,
ISA boards, relevant access
ISA boards manage- Ethernet/Fast Ethernet/Gigabit Ethernet, MPLS,
modules and
ment PR, connections types supported by the
SDH MATRIX
system.

4xANY HOST C and On the paragraph are explained the 4xANY
4xANY management SDH MATRIX HOST C connections types supported by the
system.

COADM1, COADM2, On the paragraph is explained the integration of
Coarse WDM COMDX8, COWLA2 WDM tecnology inside the 1660SM in order to
and SFP modules enhance the network capacity.
Controller EQUICOE and MATRIXE The control system is centralized. The
EQUICOE performs the Equipment Controller
(EC) function and the MATRIXE perform the
Shelf Controller (SC) function.
all the ports (LS and HS) The following network protection are explained:

– linear MSP
Network- – MS SPRING
protections – SNCP/I and SNCP/N (among VC–4 only)
– Drop Continue + insertion SNCP
– Collapsed single–node ring interconnection
– Collapsed dual–node ring interconnection

The MATRIXE card manages all the protections.
63x2 Mbit/s port (N+1) The SC on the MATRIXE card controls the EPS
protections.
Protection 3x34/45 Mbit/s port (N+1)
4xSTM–1 electrical port (N+1)
16xSTM–1 electrical port (N+1)

Equipment ISA–ATM MATRIX (1+1)
protections PR_EA MATRIX (1+1)

ISA–ES 16 (1+1)
CONGI (power supply only)
MATRIXE
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HPROT

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Sub–system Card involved Short description
Synchronization MATRIXE The MATRIXE performs the synchronization
function therefore distributing the clock and

synchronisms to all the equipment cards.

Auxiliary HS ports, SERVICE, On the para. is explained how the OH bytes
EQUICOE (DCC, EOW and AUX channels) are managed.

Power supply all the cards, CONGI The powering is distributed over the all equip-
ment cards. The CONGI cards provides the 48
V and the service 3.3 V to power each card.

Remote Inventory all the cards, access card and On the para. is explained the Remote Inventory
modules architecture
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SPARE
Prot.
Link
63 x 2 Mbit/s PDH Electrical unit
MAIN Access cards
T2 line clock
T∅ LOI G.703 Electrical
Sw
Data Interfaces
–Batt/Gnd DC/DC
Control Converter Vcc W

Prot. Vcc W Control

3 x 34/45 Mbit/s PDH Electrical unit PROT. Access cards
CARD
TO/FROM MATRIX

Prot. Prot.
See Figure 95.

Link Link
OH

Electrical
T∅ LOI G.703
Data Interfaces

–Batt/Gnd DC/DC
Control Converter Vcc X

Vcc X Control

4 x 155 Mbit/s electrical unit PROT. Access cards
CARD
Control

HOA TTF SPI
Data

T∅ Prot. Prot.
Link Link Electrical
T1 Interfaces
DCC
OH DC/DC HOA TTF SPI
Converter
–Batt/Gnd Vcc Y

Vcc Y Control
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Figure 89. 1660SM Block diagram – ( SDH and PDH boards)

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4 x 140 Mb/s el.–155 E/O Mbit/s unit

–Batt/Gnd

DC/DC
Control Converter 140 Mbit/s
HOI PPI
T∅ Vcc Z STM–1
T1 HOA TTF SPI
DCC STM–1 Optical/
OH HOA TTF SPI
Electrical
Interfaces
Data TTF SPI STM–1
HOA
Access card Booster
TO/FROM MATRIX See Figure 95.

Vcc Z Control

4 x 155 E/O Mbit/s unit
–Batt/Gnd
DC/DC
TTF Booster
Control Converter SPI STM–1
HOA
T∅ Vcc Z STM–1
T1 HOA TTF SPI
DCC STM–1
SPI Optical/
OH HOA TTF
STM–1 Electrical
Data HOA TTF SPI Interfaces

Access card

Vcc Z Control

1 x STM–4 SDH unit
–Batt/Gnd 1 x STM–16 SDH unit
DC/DC
Control Converter (*)
T∅
T1 Preamplifier
DCC TTF SPI Optical
STM–4/STM–16 Interfaces
Data
HOA
OH
Booster

–Batt/Gnd
DC/DC 1 x STM–64 SDH unit
Control Converter
T∅
T1 Optical
DCC TTF SPI Interfaces
STM–64
Data
HOA
OH Booster

(*) – Only for STM–16
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 90. 1660SM Block diagram – (SDH and PDH boards)

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16 x 155 E/O – 4xSTM–4 Optical
Mbit/s unit
–Batt/Gnd #1 STM–1
DC/DC TTF
Converter SPI

HOA

Vcc Z
Optical
Control STM–1 Interfaces
#4
T∅ HOA TTF SPI
T1
DCC Access card
OH
STM–1
HOA TTF #5 SPI
Optical
STM–1 Interfaces
#16 SPI
HOA TTF
Data

OR

Vcc Z Control
Mbit/s unit
–Batt/Gnd DC/DC
Access card STM–1
Converter
HOA TTF #1 SPI
Vcc Z
Control STM–1
T∅ HOA TTF #4 SPI
T1
Electrical
DCC
OH
STM–1 Interfaces
HOA TTF #10 SPI

STM–1
HOA TTF #16 SPI
Data

OR

Vcc Z Control
Mbit/s unit
–Batt/Gnd
DC/DC #1
Converter #1 STM–4
TTF
SPI
Vcc Z HOA
Optical

Control STM–4 #4 Interfaces
#4
T∅ HOA TTF SPI
T1
DCC
OH #5
HOA TTF
not used

Data HOA TTF #16
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 91. 1660SM Block diagram – (SDH boards)

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4 x OC3 AU3/TU3 CONV. unit
–Batt/Gnd

DC/DC

Control Converter OC3
AU3/TU3 conv. SPI
T∅ Vcc Z OC3
AU3/TU3 conv. SPI
DCC OC3
OH AU3/TU3 conversion SPI Optical/
Electrical
Interfaces
Data AU3/TU3 conversion SPI OC3

Access card

Vcc Z Control

4 x ANY HOST C unit
–Batt/Gnd DC/DC
Converter
Control
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
CDR
T∅ RX
ÏÏÏÏÏÏÏ Low speed signals:
TX
ÏÏÏÏÏÏÏ Fast Ethernet
Opt. module #1 FDDI
2xAny ÏÏÏÏÏÏÏ ESCON
ÏÏÏÏÏÏÏ
CDR
ÏÏÏÏÏÏÏ RX
Digital Video
FDDI
TX

Data STM–16
ÏÏÏÏÏÏÏ
Opt. module #2
ÏÏÏÏÏÏÏ
Mapper ÏÏÏÏÏÏÏ Low speed signals:
ÏÏÏÏÏÏÏ
CDR

ÏÏÏÏÏÏÏ RX
TX
Fast Ethernet
FDDI
ÏÏÏÏÏÏÏ
Opt. module #3 ESCON
2xAny ÏÏÏÏÏÏÏ Digital Video
FDDI
ÏÏÏÏÏÏÏ
CDR
RX High speed signals:
ÏÏÏÏÏÏÏ TX
Fiber Channel
ÏÏÏÏÏÏÏ
Opt. module #4
ÏÏÏÏÏÏÏ FICON
Gigabit Ethernet
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 92. 1660SM Block diagram – (SONET and 4xANY HOSTC boards)

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DOUBLE MULTIRATE TRANSPONDER unit
CK

Multirate Rx1 Mx SFP module
SFP module Data

CDR Data Rx1
Data Rx3 Recovery
BW CWDM
Data Rx2 TVC
TVC Data Data Rx4
Recovery CK Multirate
CK Rx 1:4 Data Rx 1:4 Rx3 CDR BW or CWDM
BW or CWDM
SFP module Data SFP module
Multirate CK Recovery
CDR Rx2
CWDM CWDM
TVC TVC
Data CK Multirate
RS RS Rx4 CDR
Recovery
monitor monitor
#1 #2

Alarm/Control
Interface
Remote Inventory

EEPROM RIBUS

SPI bus ISPB bus

λ1 1470 output signal

λ2 1490 CWDM
1510
λ3
OUTPUT CHANNELS 1530
(from colored port or λ4 MUX
Transponder interface) 1550
λ5
1570
λ6 1610
λ7 1590
λ8

λ1 1470
λ2 1490
LOS HANDLING
INPUT CHANNELS
λ3 1510 CWDM
input signal
(to colored port or λ4 1530
Transponder interface) DEMUX
λ5 1550

λ6 1570

λ7 1610
1590
λ8 LOS
DETECTION

MUX/DEMUX8 unit Remote Inventory

EEPROM RIBUS

SPI bus
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 93. 1660SM Block diagram – (CWDM boards)

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To/From
colored port
or
transponder CWDM
λx 1xx0

output signal

CWDM

λgrid – λx

OADM
λx 1xx0 CWDM
input signal
CWDM
λgrid – λx

LOS
DETECTION
LOS HANDLING
To/From
OADM
opposite
side

Remote Inventory

EEPROM RIBUS
COADM1 unit

SPI bus

To/From
colored port
or
transponder CWDM
λx 1xx0
output signal
CWDM λy 1xx0

λgrid – λx–λy

OADM
λx 1xx0 CWDM
input signal
CWDM λy 1xx0


LOS
DETECTION
LOS HANDLING
To/From
OADM
opposite
side

Remote Inventory

EEPROM RIBUS
COADM2 unit

SPI bus
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 94. 1660SM Block diagram – (CWDM boards)

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ISA boards

See from Figure 96. on page 194 to Figure 98. on page 196

Data
2
1

Data Data
See Figure 89. and Figure 90.

TO/FROM
SDH matrix PORT
(HPC–LPC) See Figure 89. and Figure 90.

T∅ SERVICE unit
–Batt/Gnd DC/DC
T1
Converter
MATRIXE RS232 Aux RS232
T2
TO/FROM PORT

Synchronization
T3/T6 a OH OH G.703 Aux 2Mbit/s
ports add/drop
T3/T6 b G.703 Aux 64kbit/s
T4/T5 a Control V.11 Aux 64kbit/s
T4/T5 b Control Voice ext.
Digital
Control DCC Party Local phone
EQUICOE
add/drop Line Aux ext.

T3/T6 a T3a/T6a_ext.
T3/T6 b T3b/T6b_ext.
Shelf
T4/T5 a G.703
–Batt/Gnd DC/DC Controller T4a/T5a_ext.
Converter T4/T5 b
T4b/T5b_ext.

SC/EC Control Control b
CONGI unit
EQUICOE
Remote alarms
Housekeeping
–Batt/Gnd DC/DC
Converter
USB –Batt/Gnd Filter
Interface Power B
Vcc DC/DC
Equipment
F Controller a
Control CONGI unit
Interface QB3
Remote alarms
leds Housekeeping
Rack lamps
ports
DCC Q2
add/drop –Batt/Gnd Filter
SERVICE Vcc DC/DC Power A
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 95. 1660SM Block diagram – ( Common units and ISA boards)

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ISA – ATM MATRIX
–Batt/Gnd
DC/DC
Converter
Control

Traffic Policing CELL
and SWITCHING
Shapimg
T∅
ATM ENGINE

Data

Optical/Electrical
SDH TERMINATION

Interface
STM–1 E/O STM–1
LOCAL PORT MODULE
(*)

ISA – PR_EA MATRIX 1GBPS 1 X GB ETHERNET

Gigabit Ethernet Optical Interfaces
–Batt/Gnd
DC/DC
Control Converter

1000 BASE–SX / LX /ZX
T∅

OPTICAL MODULE #1
Data MPLS ENGINE
1000 BASE–SX/LX/ZX

ISA – PR_EA MATRIX 4X ETHERNET
–Batt/Gnd
DC/DC
10/100 Mbit/s Base T

Control Converter ETHERNET #1
Ethernet Interface

1
T∅ ETHERNET #2

ETHERNET #3
Data MPLS ENGINE ETHERNET #4 4

NOTE: (*) – Available only on ATM MATRIX 4X4
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 96. 1660SM Block diagram – (ISA boards)

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1000 BASE–SX / LX /ZX
Physical
See Figure 95. Interface
ISA – ES1

Control GBit ETH.
ISA – ES4
T∅
(*)

Physical
TO/FROM MATRIX

Interface
1

ETH. 1

Ethernet Interfaces

100 Mbit/s Base FX
Data SDH Ethernet frame
Ethernet
mapping into switcher
framer

or
SDH VC

8
ETH. 8

–Batt/Gnd DC/DC
Converter

(*) GIGABIT ETHERNET interface is available only on ES4–8FE board; it is not supported in
current release

Ethernet Interfaces
ETHERNET #1 1
See Figure 95.

ISA – ES16
Control

T∅ ETHERNET #14 14
10/100 ETH
Access card
TO/FROM MATRIX

Data SDH Ethernet frame
Ethernet
mapping into switcher
framer

SDH VC
Gigabit Ethernet
1000 BASE–SX / LX / ZX

Access card
OPTICAL MODULE #1
1
–Batt/Gnd DC/DC
Converter
OPTICAL MODULE #2 4
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 97. 1660SM Block diagram – (ISA – ES boards)

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Ethernet Interfaces
ISA – ETHERNET

ETHERNET #1 1
Control

PORT (10/100 Mb/s)

T∅
11
ETHERNET #11
Ethernet frame
Data mapping into

Ethernet Interfaces
SDH VC ETHERNET #1 1

See Figure 95.

ETHERNET #14 14
–Batt/Gnd DC/DC
Converter
Access card

Ethernet Interfaces
ISA – ETHERNET PORT 1
Control ETHERNET #1
(10/100 Mb/s)
TO/FROM MATRIX

T∅
11
ETHERNET #11
Ethernet frame
mapping into
Data SDH VC

OPTICAL MODULE #1
1

1000 BASE–SX /LX/ZX

OPTICAL MODULE #2 2
–Batt/Gnd DC/DC
Converter Gigabit Ethernet
Access card

ISA – GBIT
Control
ETHERNET PORT

T∅

OPTICAL MODULE #1
1
Ethernet frame 1000 BASE–SX /LX/ZX
Data mapping into
SDH VCxc
OPTICAL MODULE #4 4

DC/DC
Converter
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 98. 1660SM Block diagram – (ISA – ETHERNET boards)

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Ethernet Interfaces 10/100 Mbit/s Base T
16FEA–PR
ISA – PR MATRIX Access card
TO/FROM STM4 LINE OR PORT CARD

1
ETHERNET #1

NETWORK
PROCESSOR

16
STM4 1 ETHERNET #16
STM4 2 MPLS ENGINE
STM4 FRAME
INTERFACE
STM4 3 TRAFFIC

STM4 4 MANAGEMENT OPTICAL MODULE #1 1

NETWORK
PROCESSOR

–Batt/Gnd OPTICAL MODULE #2
DC/DC 2
from Congi Converter

2 GBA–PR
Control
PR
Access card
from/to Matrix
Controller
Craft
Terminal RJ45
or NMS
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 99. 1660SM Block diagram – (ISA–PR board)

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3.2 Connections sub–system

This sub–system allows connections between any SDH, SONET, PDH or ISA (Integrated Service Adapter)
ports

The connections can be realized at VC–12, VC–3, and VC–4 level using a not blocking matrix present
on the MATRIXE unit.
Several types of connections may be established, such as:
• Unidirectional Point to Point
• Unidirectional Point to Multipoint
• Bidirectional Point to Point

Cross–connection function can be considered within two layers: HO Layer and LO layer. Refer to
Figure 100. on page 199.

The maximum matrix cross connection capability can be 256x256 STM–1 equivalent port at VC–12 /
VC–3 level + 384x384 equivalent port at VC–4 level.

The following table illustrates the connections for each unit:

Table 34. High Order/Low Order connections for 1660SM
STM–1, STM–4, STM–16, OC3 140 Mbit/s 34 Mbit/s 2 Mbit/s
STM–64 ports ports ports 45 Mbit/s ports
ports

PORTS Struc- AU–4 TU–3 TU–12 AU–3 VC–4 VC–3 VC–12
ture

STM–1, AU–4 Yes – – – Yes – –

STM–4, TU–3 – Yes – Yes – Yes –

STM–16 TU–12 – – Yes – – – Yes

OC3 AU–3 – Yes – Yes – – –

140 Mbit/s VC–4 Yes – – – Yes – –

34Mbit/s
45Mbit/s VC–3 – Yes – – – Yes –

2Mbit/s VC–12 – – Yes – – – Yes

The above connections allows the 1660SM to realize Multi Line Terminal configuration, Add/Drop
configuration and Mini Cross–Connect configurations in linear links, rings, and mashed network as
describe in Chapter 1 on page 63.
AU4–4C and AU4–16C concatenated signals can also be cross connected between any STM–4 and
STM–16 ports.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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(equivalent STM–1 streams)

128 256 4x STM–64 Tx

8x STM–16 Tx

port port

128 256
8x STM–16 Rx 4x STM–64 Rx
port port

MATRIXE

MSP MSP
128x 256x
128 256

384 384

HPC
640x
640

256 256

LPC
256 256x 256
HOA sk HOA sk
LVC 256 LVC

LOI so LOI so

port port
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 100. MATRIXE– Cross connection management

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3.3 SIGNAL MANAGEMENT SUB–SYSTEM

3.3.1 Signal management referred to ”G.783 1994”

In the next paragraphs will be explained the SDH and PDH port signal management. The functional blocks
in this description are similar to that utilized in the Craft Terminal application.
For each port the description is subdivided in two part:
– Signal management from Side B (high bit rate signal) to Side A (low bit rate signal).
– Signal management from Side A (low bit rate signal) to Side B (high bit rate signal).

Anyway a signal may not transit through all the functional blocks (e.g. from side A to side B) but it comes
back to the source side by means of the matrix (LPC, HPC) thus realizing a cross connection.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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3.3.2 SDH port signal management
(For STM –N see Figure 101. on page 203)

Side B to Side A description:

•

SPI (Synchronous Physical Interface)

It interface the physical transmission medium, regenerates and decodes line signal and
detect the LOF alarm.
• RST (Regenerator Section Termination)
It manages the section overhead bytes for the Regeneration Section; it performed frame
alignment detection, regenerator section trace recovery and mismatch detection, B1
BIP–8 errored block count.
• MST (Multiplex Section Termination)
It manages the section overhead bytes for the Multiplexing section; performs BIP–24
errored block count, MS–REI recovery, MS–RDI and MS–AIS detection.
• MSP (Multiplex Section Protection) and MSPC (Multiplex Section Protection Connection)
It provides protection for the STM–N signal against failures within a multiplex section, by
using a bit oriented protocol for the MSP bytes K1,K2 and P, B1.
• MSA (Multiplex Section Adaptation)
It performs AU4 pointer interpretation, LOP and AIS detection, pointer justification.
• HPOM (High Order Path Overhead Monitoring)
It monitors the higher order VC–n for errors, and recover the trail termination status. it
extract the payload independent overhead bytes J1, G1, B3.
• HPC (High Order Path connection)
This function assign higher order VCs of level n at its input port to higher order VCs of level
n at its output port.
• HSUT (Higher Order Supervisory Unequipped Termination)
It performs the termination of an unequipped path recovering path trace information, REI
and detecting HP–RDI (Path status monitoring),VC4 BIP–8 Errored Block count.
• HPT (High Order Path Termination)
This function recover the trail termination status. It extract the payload independent
overhead bytes/bits (J1, G1, B3) from the VCn layer ;
• HPA (High Order Path Adaptation)
This functions provide VC–4 disassembly TU pointer interpretation, LOP and TU–AIS
detection;
• LPOM (Lower Order Path Monitor)

• LPC (Low Order Path Connection)
It assigns lower order VCs of level m at its input ports to lower order VCs of level m at
its output ports. The process does not affect the nature of the characteristic information
of the signal.
• LSUT (Lower Order Supervisory Unequipped Termination)
It is used to monitor unequipped path trace, recovering VC–m unequipped signal label,
BIP–2 recovery.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Side A to Side B description:

• LSUT (Lower Order Supervisory Unequipped Termination)
It is used to monitor unequipped path trails; it inserts VC–m unequipped signal label, path

trace, BIP–2, REI and RDI.

• LPC (Low Order Path Connection)
It assigns lower order VCs of level m at its input ports to lower order VCs of level m at
its output ports. The process does not affect the nature of the characteristic information
of the signal.
• LPOM (Lower Order Path Monitor)
It is used for performance monitoring purpose and for lower order SNCP/n.
• HPA (High Order Path Adaptation)
This function provides VC–4 assembly, TU pointer generator, TU–AIS.
• HPT (High Order Path Termination)
It performs path trace identification insertion, RDI and REI insertion VC–4 BIP–8
calculation and insertion, signal label insertion.
• HPOM (High Order Path Overhead Monitoring)
It monitors the higher order VC–4 for errors, and recover the trail termination status. it
extract the payload independent overhead bytes J1, G1, B3.
• HPC (High Order Path connection)
This function assign higher order VCs of level n at its input port to higher order VCs of level
n at its output port.
• HSUT (Higher Order Supervisory Unequipped Termination)
It generates and inserts an unequipped container, trail trace identifier, RDI and REI, VC–4
BIP–8.
• MSA (Multiplex Section Adaptation)
It performs AUG assembly, AU–4 pointer generation, AU–AIS generation
• MSP (Multiplex Section Protection) and MSPC (Multiplex Section Protection Connection)
It provides protection for the STM–N signal against failures within a multiplex section, by
using a bit oriented protocol for the MSP bytes K1,K2 and P, B1.
• MST (Multiplex Section Termination)
It performs BIP–24 calculation and insertion, MS–REI, MS–RDI and MS–AIS insertion.
• RST (Regenerator Section Termination)
It performs frame alignment insertion , regenerator section path trace insertion BIP–8 (B1)
calculation and insertion.

• SPI (Synchronous Physical Interface)
Signal conditioning for transmission medium
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Side A

To point Y1 From point Y2

Figure 102. Figure 102.
X1 X2
Low
Order
LSUT LSUT Path
Layer
LPC

LPOM LPOM

HPA HPA

HPT HPT
High
To point W1 From point W2 Order
Figure 103. Figure 103. Path
HSUT Layer
HSUT Z1 Z2

HPC

HPOM HPOM

MSA MSA

Multiplex
MSP MSPC MSP Section
Layer

MST MST

Regenerator
RST RST Section
Layer

SPI SPI SDH
Physical
Layer

Side B
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 101. SDH signal management block diagram

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3.3.3 PDH port signal management

Ports managed are: 2Mbit/s (mapped into VC–12), 34Mbit/s (VC–3), 45Mbit/s (VC–3) and 140Mbit/s
(VC–4). The following functions are associated with each PDH port.

2Mbit/s, 34 Mbit/s and 45 Mbit/s port management
( See Figure 102. on page 204 )


• PPI This block provides the interface between the physical transmission medium and the
internal unit format. The received line signal is HDB3 coded. A decoder on the physical interface
decodes the signal to NRZ (no return–to–zero) format.
• LPA This block adapts user data for transport in the synchronous domain. For asynchronous
user data, lower order path adaptation involves bit justification. The 2.048 Mbit/s is inserted into
a VC–12, which is synchronized (stuffing) with the correspondent TU–12. The 34 Mbit/s or 45
Mbit/s is inserted into a VC–3, which is synchronized with the correspondent TU–3.
• LPT For the 2.048 Mbit/s the LPT function creates a VC–12 by generating and adding POH
to a C–12. The POH formats are defined in Recommendations G.708 and G.709. For the 34
Mbit/s and 45 Mbit/s the LPT functions creates a VC–3 by generating and adding POH to a C–3.


• LPT The LPT function terminates and processes the POH to determine the status of the defined
path attributes.
• LPA It extracts the POH from the VC–12 (2 Mbit/s) or VC–3 (34 Mbit/s and 45 Mbit/s) .
• PPI This block provides the interface between the internal unit format and the physical
transmission medium. It encodes HDB3 the signal to be sent on line.

Side B

PPI PPI

LPA LPA

LPT LPT

Y1 Y2

From point X1 To point X2

Side A
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 102. 2Mbit/s, 34 Mbit/s, 45 Mbit/s signal management block diagram

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140 Mbit/s port management
( See Figure 103. on page 205 )


• PPI This block provides the interface between the physical transmission medium and the
internal unit format. The received line signal is CMI coded. A decoder on the physical interface
decodes the signal to NRZ (no return–to–zero) format.

• LPA The 140 Mbit/s plesiochronous stream is inserted in a C4 container to be adapted so as
to be transported into the synchronous network.

• HPT The Virtual Container (VC–4) is formatted. The VC–4 is structured so that its octets are
distributed within a 125 µs. interval and consist of the C4 container and POH.


• HPT The HPT extract and processes the POH to determine the status of the defined path
attributes.

• LPA It extracts the 140 Mbit/s signal from the container C4 .

• PPI This block provides the interface between the internal unit format and the physical
transmission medium. It encodes CMI the signal to be sent on line.

Side B

PPI PPI

LPA LPA

HPT HPT

w1 w2
From point Z1 To point Z2

Side A

Figure 103. 140Mbit/s signal management block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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3.3.4 SIGNAL MANAGEMENT referred to ”G. 783”

The ITU–T G.783 Recommendation describe the SDH characteristic in terms of atomic functions.
This paragraph has been introduced as an aid to the understanding of the terms used for the Termination

Point (T.P.). These TPs can be accessed and managed by the operator for performance monitoring

purpose .
In the following will be explained the atomic functions naming conventions and the signal processing in
the SDH and PDH port .

3.3.5 ATOMIC FUNCTION NAMING CONVENTIONS

Each characteristic layer of the SDH network is splitted into different atomic functions :

– trail termination function :

• Source (So): additional information is added to the characteristic information to allow trail
monitoring.
• Sink (Sk): the information related to the trail monitoring is extracted

If a signal fail condition of the associated data signal is detected, a TSF signal is generated to
inform the next downstream function. TSF is use in the HPOM (Snm) function to drive the
SNCP/MSP protection.

– adaptation function :

• Source (So):the characteristic information is adapted from the client to the server layer
• Sink (Sk): the characteristic information is adapted from the server to the client layer

The processes present in an adaptation function can be : encoding, rate changing, alignment,
justification, multiplexing.
If a signal fail condition of the associated data signal is detected, a SSF signal is generated to
inform the next downstream function.

– connection function : it represents the connection functions inside the network ( link
connection, sub–network network connection) and it is performed by the matrix functional block

Each atomic function is represented by a different symbol and named as follow:

– trail termination TT : triangle
Sink Source

naming rules: layer_TT[ _direction] example: OSn_TT[ _Sk]

– adaptation A : trapezium
Sink Source

naming rules: layer/client layer_A[direction] example: OSn/RSn_A[Sk]
1AA 00014 0004 (9007) A4 – ALICE 04.10

– connection C: circle or ellipse

naming rules: layer_C example: Sm_C

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3.3.6 SDH PORT FUNCTIONAL BLOCKS

(For STM–N port refer to Figure 104. on page 216)

The received signal is either electrical STM–1 CMI coded (ITU–T G.703 Rec.) or optical STM–N (ITU–T

G.957 Rec.). The SDH frame format is compliant with ITU_T G.707 Rec.

In this paragraph will be explained the SDH and PDH port signal management referred to atomic function.
For each port the description is subdivided in two part:

– Signal management from Side B (high bit rate signal) to Side A (low bit rate signal).

– Signal management from Side A (low bit rate signal) to Side B (high bit rate signal).


a) SDH Physical layer (SPI)

It is the interface between the physical transmission medium and the Regeneration Section. The function
performed are describe below:

• Optical or Electrical Section layer Trail Termination: OSn_TT_Sk or ESn_TT_Sk

• input LOS detection.

• Optical or Electrical Section layer Adaptation to Regenerator Section layer: OSn/RSn_A_Sk
and ESn/Rsn_A_Sk

• descrambler.

• A1, A2: frame alignment detection.
• OOF count and LOF detection.
• AIS or SSF insertion if LOF is detected

b) Regenerator Section layer (RST)

• Regenerator Section layer Trail Termination: RSn_TT_Sk
• J0: regenerator section trace recovery and mismatch detection (TIM) (not
managed in this release)
• B1: BIP–8 Errored Block count: even bit parity is computed and compared with
B1 recovered from the current frame.
• AIS insertion if TIM is detected

• Regenerator Section layer to Multiplex Section layer Adaptation: RSn/MSn_A_Sk
• AIS insertion on AIS detection
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c) Multiplex Section layer :

• Multiplex Section layer Trail Termination (MST): MSn_TT_Sk

•

B2: BIP–24N Errored Block count ––Ex–BER, Signal Degrade alarm

• M1: MS–REI recovery.
• K2[6–8]: MS–RDI detection.
• K2[6–8]: MS–AIS detection.

• Multiplex Section Sub–layer Protection function (MSP):

– Multiplex Section layer to the Multiplex Section Protection Sub–layer Adaptation:
MSn/MSnP_A_Sk

• the K1–K2 information (APS protocol) is recovered .
• AIS or SSF insertion

– Multiplex Section Protection Sub–layer Trail Termination: MSnP_TT_Sk

• AIS or SSF detection
• TSF insertion (on SSF detection)

• Multiplex Section layer Adaptation to the High Order Path layer (MSA): MSn/Sn_A_Sk

• AU–4 Pointer interpreter.
• LOP detection
• AU–AIS detection
• AIS or SSF insertion (on LOP and AU–AIS detection)
• PJE (Pointer Justification Event) count.

d) High Order Path layer:

• High Order Path Overhead Monitoring Function (HPOM)

– High Order Path Overhead Trail Termination: Snm_TT_Sk

• J1: Path Trace information is recovered.
• G1[1–4]: The REI information is recovered.
• G1[5]: Path Status monitoring –– HP–RDI detection.
• C2: Signal Label Monitoring –– UNEQ and VC–AIS detection.
• B3: VC–4 BIP–8 Errored Block Count –– Ex–BER and Signal Degrade alarm
• TSF insertion
• TSD insertion
TSF and TSD are used for SNCP switch

• High Order Supervisory Unequipped Termination

– High Order Supervisory Unequipped Trail Termination (HSUT): Sns_TT_Sk

• G1[5]: Path Status monitoring ––HP–RDI detection.
• B3: VC–4 BIP–8 Errored Block Count.
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• High Order Path Tandem Connection Trail Termination (according to Option 2 TC described in
Recc. ITU–T G.707)

– High Order Path Tandem Connection Termination (HTCT): SnD_TT_Sk

• N1[1–4]: VC–4 BIP–8 extraction and EDC calculation.
• N1[8][73]: RDI extraction.
• N1[5]: REI extraction.
• N1[7][74]: ODI extraction (Outgoing Defect Indication).
• N1[6]: OEI extraction (Outgoing Error Indication)
• N1[7–8]: extraction from the multiframed channel N1[7–8] of:
FAS (Frame Alignment Signal) in frames 1 to 8.
trace identifier in frames 9 to 72.
TC RDI and ODI in frames 73 to 76.
• B3: BIP–8 compensation.

• High Order Path Tandem Connection Adaptation (according to Option 2 TC described in Recc.
ITU–T G.707)

– High Order Path Tandem Connection Adaptation (HTCA): SnD/Sn_A_Sk

this function will restore the invalid Frame Start condition if that existed at the iput of the
tandem connection.
AIS insertion.

• High Order Path Tandem Connection Monitoring (according to Option 2 TC described in Recc.
ITU–T G.707)

– High Order Path Tandem Connection Monitoring (HTCM): SnDm_TT_Sk

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• High Order Path layer Trail Termination Function (HPT): Sn_TT_Sk

• J1: Path Trace information is recovered –– TIM detection.


• C2: UNEQ detection.
• B3: VC–4 BIP–8 Errored Block Count –– Ex–BER, Signal Degrade alarm

• High Order Path layer Adaptation to Low Order Path layer (HPA): Sn/Sm_A_Sk

• VC–4 disassembly.
• TU pointer interpretation.
• LOP detection.
• TU–AIS detection.
• C2: HP–SLM (signal label mismatch) detection.
• H4: LOM (Loss of Multiframe) detection.

e) Low Order Path layer:

• Low Order Path Overhead Monitoring Function (LPOM)

– Low Order Path Overhead Trail Termination: Smm_TT_Sk

• J2: Trace Identifier Monitoring.
• V5[8]: RDI information is recovered and reported.
• V5[3]: REI bit is recovered and the derived performance primitives are reported.
• V5[5–7]: Signal Label Monitoring –– VC–AIS detection.
• V5[1,2]: VC–m BIP–2 Errored Block Count ––Ex–BER, Signal Degrade alarm
• AIS or SSF detection––SSF alarm
• TSF insertion (used for SNCP switch)

• Low Order Supervisory Unequipped Termination (LSUT)

– Low Order Supervisory Unequipped Trail Termination: Sms_TT_Sk

• V5[5–7]: signal label is recovered from the VC–m. 000 (unequipped) is expected.
• J2: trail trace identifier is recovered.
• V5[1,2]: BIP–2 is recovered.
• V5[3]: REI bit is recovered and the derived performance primitives is reported.
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• Low Order Path Tandem Connection Trail Termination (according to Option 2 TC described in

– Low Order Path Tandem Connection Termination (LTCT): SmD_TT_Sk

• N2[4]: AIS detection
• V5[1–2]: BIP–2 compensation.

• Low Order Path Tandem Connection Adaptation (according to Option 2 TC described in Recc.
ITU–T G.707)

– Low Order Path Tandem Connection Adaptation (LTCA): SmD/Sm_A_Sk

tandem connection.
AIS insertion.

• Low Order Path Tandem Connection Monitoring (according to Option 2 TC described in Recc.
ITU–T G.707)

– Low Order Path Tandem Connection Monitoring (LTCM): SnDm_TT_Sk

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a) Low Order Path layer:

•

Low Order Supervisory Unequipped Termination (LSUT)

– Low Order Supervisory Unequipped Trail Termination: Sms_TT_So

• V5[5–7]: signal label 000 (unequipped) is inserted in the VC–m.
• J2: trail trace identifier is generated.
• V5[1,2]: BIP–2 is calculated and transmitted.
• V5[3]: the number of errors is encoded in REI.
• V5[8]: RDI indication is inserted.

• Low Order Path Overhead Monitoring Function (LPOM)

– Low Order Path Overhead Trail Termination: Smm_TT_Sk

• J2: Trace Identifier Monitoring.
• V5[3]: REI bit is recovered and the derived performance primitives are reported.
• V5[5–7]: Signal Label Monitoring –– VC–AIS detection.
• V5[1,2]: VC–m BIP–2 Errored Block Count –– Ex–BER, Signal Degrade alarm

• Low Order Path Tandem Connection Adaptation (according to Option 2 TC described in Recc.
ITU–T G.707)

– Low Order Path Tandem Connection Adaptation (LTCA): SmD/Sm_A_Sk

tandem connection.
AIS insertion.

• Low Order Path Tandem Connection Trail Termination (according to Option 2 TC described in

– Low Order Path Tandem Connection Termination (LTCT): SmD_TT_So

• N2[8][73]: RDI insertion
• N2[5]: REI insertion
• N2[7][74]: ODI insertion (Outgoing Defect Indication)
• N2[6]: OEI insertion (Outgoing Error Indication)
• N2[7–8]: insertion in the multiframed channel N1[7 –8] of:
FAS (Frame Alignment Signal) in frames 1 to 8
trace identifier in frames 9 to 72
TC RDI and ODI in frames 73 to 76
• N2[1–2]: BIP–2 calculation and insertion
• V5[1–2]: BIP–2 compensation
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• Low Order Path Tandem Connection Monitoring (according to Option 2 TC described in Recc.
ITU–T G.707)

– Low Order Path Tandem Connection Monitoring (LTCM): SnDm_TT_Sk


b) High Order Path layer:

• Low Order Path layer to High Order Path layer Adaptation (HPA): Sn/Sm_A_So

• VC–4 assembly.
• TU pointer generator.
• TU–AIS generator.
• C2: Signal label insertion.
• H4: Multiframe indicator

• High Order Path layer Trail Termination Function (HPT): Sn_TT_So

• J1: path trace identifier is inserted.
• G1: insertion of RDI[5] and/or REI[1–4] information.
• B3: VC–4 Bip–8 calculation and insertion.

• High Order Path Overhead Monitoring Function

– High Order Path Overhead Trail Termination (HPOM): Snm_TT_Sk

• G1[5]: Path Status monitoring –– HP–RDI detection.
• B3: VC–4 BIP–8 Errored Block Count.
• AIS or SSF detection –– SSF alarm
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– High Order Supervisory Unequipped Trail Termination (HSUT): Sns_TT_So

• Generation of an unequipped container and frame offset.
• C2: “unequipped” insertion.


• G1: insertion of RDI and/or REI information.

• High Order Path Tandem Connection Adaptation (according to Option 2 TC described in Recc.
ITU–T G.707)

– High Order Path Tandem Connection Adaptation (HTCA): SnD_A_So

this function will replace the incoming Frame Start signal by a local generated one if
all–ONEs VC is received.

• High Order Path Tandem Connection Trail Termination (according to Option 2 TC described in

– High Order Path Tandem Connection Termination (HTCT): SnD_TT_So

• N1[8][73]: RDI insertion
• N1[5]: REI insertion
• N1[7][74]: ODI insertion (Outgoing Defect Indication)
• N1[6]: OEI insertion (Outgoing Error Indication)
• N1[7–8]: insertion in the multiframed channel N1[7 –8] of:
FAS (Frame Alignment Signal) in frames 1 to 8
trace identifier in frames 9 to 72
TC RDI and ODI in frames 73 to 76
• N1[1–4]: BIP–8 calculation and insertion
• B3: BIP–8 compensation

• High Order Path Tandem Connection Monitoring (according to Option 2 TC described in Recc.
ITU–T G.707)

– High Order Path Tandem Connection Monitoring (HTCM): SnDm_TT_Sk

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c) Multiplex Section layer:

• Multiplex Section layer Adaptation to the High Order Path layer (MSA): MSn/Sn_A_So

•

AUG assembly and byte interleaving.

• AU–4 Pointer generator.
• AU–AIS generator.

• Multiplex Section Sub–layer Protection function (MSP)

– Multiplex Section Protection Sub–layer Termination: MSnP_TT_So

• no information is inserted.

– Multiplex Section layer Adaptation to the Multiplex Section Protection Sub–layer:
MSn/MSnP_A_So

• generation of K1–K2 information (APS protocol).

• Multiplex Section layer Trail Termination: MSn_TT_So

• B2: BIP–24N calculation and insertion.
• M1: MS–REI insertion.
• K2[6–8]: MS–RDI insertion.
• K2[6–8]: MS–AIS insertion.

d) Regenerator Section layer (RST)

• Multiplex Section layer to Regenerator Section layer Adaptation : RSn/MSn_A_So

• RS–AIS insertion.
• Regenerator Section layer Trail Termination: RSn_TT_So
• A1, A2: frame alignment insertion.
• J0: regenerator section trace insertion (not managed in this release)
• B1: BIP–8 calculation and insertion.

e) SDH Physical layer (SPI)
It is the interface between Regeneration Section and the physical transmission medium. The function
performed are describe below:

• Optical or Electrical Section layer Adaptation to Regenerator Section layer: OSn/RSn_A_So
and ESn/Rsn_A_So:
• scrambler.
• AIS generator (on LOS or LOF).
• Optical or Electrical Section layer Trail Termination: OSn_TT _So or ESn_TT _So
• signal conditioning for transmission medium (e.g. electrical/optical conversion etc.)
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Side A
Low
LTCA To point Y1 From point Y2 LTCA Order
SmD/Sm Figure 105. Figure 105. SmD/Sm Path
Figure 106. Figure 106. Layer

X2

X1

LPOM LTCM LTCT LSUT LSUT LTCT LTCM LPOM
Smm SmDm SmD Sms SmD SmDm Smm
Sms

Sm
LPC

HPA HPA High
Order
HTCA Sn/Sm Sn/Sm Path
SnD/Sn Layer HTCA
HPT HPT SnD/Sn
Sn Sn

HTCT HPOM To point W1 From point W2 HPOM
HSUT Figure 107. Figure 107. HSUT HTCT
Snd Snm Sns Z1 Z2 Sns Snm Snd

Sn
HPC
HTCM
SnDm HTCM
SnDm

MSA MSA
(*) MSn/Sn MSn/Sn (*)

MSnP MSnP
Multiplex
MSP MSP Section
MSnPC Layer

MSn/MSnP MSn/MSnP

MSn MSn
MST MST

RSn/MSn RSn/MSn Regeneration
Section
RST RST Layer
RSn RSn

OSn/RSn or ESn/RSn OSn/RSn or ESn/RSn SDH
Physical
Layer
SPI OSn or ESn OSn or ESn SPI

Side B

(*) – 1,4,16,64 MSn/Sn are multiplied in STM–n
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Figure 104. 1660SM Block Diagram: signal management (SDH port)

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3.3.7 PDH PORT FUNCTIONAL BLOCKS
In LC–NG PDH Low Order ports managed are 2Mbit/s (mapped into VC–12), 34Mbit/s (VC–3), 45Mbit/s
(VC–3) and 140Mbit/s (VC–4). The following functions are associated with each PDH port.

2 MBIT/S PORT MANAGEMENT

(See Figure 105. on page 218 )


• Low Order Path layer Trail Termination Function (LPT): S12_TT_Sk
• J2: trail trace identifier is recovered –– TIM detection.
• V5[1,2]: BIP–2 is recovered –– Ex–BER, Signal Degrade alarm
• Low Order Path layer Adaptation to PDH Section layer (LPA): S12/P12x_A_Sk or
S12/P12s_A_Sk
• V5[5–7]: Signal label detection in the byte V5[5–7] –– Signal label Mismatch
detection
• AIS or SSF is applied if Signal label Mismatch is detected

b) Electrical PDH Physical Section layer (PPI)
• Adaptation to PDH section layer: E12/P12x_A_So or E12/P12s_A_So
• It convert the internal signal code to the line code.
• Trail Termination: E12_TT_So
• signal conditioning for transmission medium ( e.g. electrical level, etc.)


a) Electrical PDH Physical Section layer (PPI)
• Trail Termination: E12_TT_Sk
• input LOS detection.
• AIS insertion if LOS is detected

• PDH physical adaptation layer: E12/P12x_A_Sk or E12/P12s_A_Sk
• timing is extracted.
• data are decoded.
• AIS insertion if LOF or AIS is detected.

b) Low Order Path layer:
• PDH Section layer to Low Order Path layer Adaptation (LPA): S12/P12x_A_So or
S12/P12s_A_So
• V5[5–7]: Signal label insertion in the byte V5[5–7].

• Low Order Path layer Trail Termination function (LPT): S12_TT_So
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Side A

PPI PPI

E12 E12

E12/P12 E12/P12

LPA LPA
S12/P12 S12/P12 Low Order Path
Layer

LPT LPT
S12 S12

Y1 Y2


Side B
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 105. 1660SM Block Diagram: signal management ( 2Mbit/s PDH ports)

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34 MBIT/S AND 45 MBIT/S PORT MANAGEMENT

(See Figure 106. on page220 )



• Low Order Path layer Trail Termination Function (LPT): S3_TT_Sk

• B3: VC–3 BIP–8 Errored Block Count –– Ex–BER, Signal Degrade
• SSF detection –– SSF alarm

• Low Order Path layer Adaptation to PDH Section layer (LPA): S3/P3x_A_Sk or S3/P3s_A_Sk

• C2: Signal label detection in the byte C2 – Signal label Mismatch detection.
• AIS or SSF is applied if TSF or Signal label Mismatch is detected


• Adaptation to PDH section layer: E3/P3x_A_So or E3/P3s_A_So

• It convert the internal signal code to the line code (HDB3)


• signal conditioning for transmission medium ( e.g. electrical level, etc.).




• Input LOS detection.

• PDH physical Adaptation layer: E3/P3x_A_Sk or E3/P3s_A_Sk

• AIS detection and insertion.
• LOF detection (only in case of E3/P3x_A_Sk)


• PDH Section layer to Low Order Path layer Adaptation (LPA): S3/P3x_A_So or S3/P3s_A_So

• The signal label is inserted in C2

• Low Order Path layer Trail Termination Function (LPT): S3_TT_So
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Side A

PPI PPI

E3 E3

E3/P3 E3/P3

LPA LPA

S3/P3 Low Order Path
S3/P3
Layer

LPT LPT
S3 S3

Y1 Y2
Side B
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 106. 1660SM Block Diagram: signal management ( 34 Mbit/s and 45 Mbit/s PDH ports)

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140 MBIT/S PORT MANAGEMENT

(See Figure 107. on page 222)


a) High Order Path layer:

• High Order Path layer Trail Termination Function (HPT): S4_TT_Sk

• B3: VC–4 BIP–8 Errored Block Count–– Ex–BER, Signal Degrade alarm
• SSF detection –– SSF alarm

• Low Order Path layer Adaptation to PDH Section layer (LPA): S4/P4x_A_Sk or S4/P4s_A_Sk

• C2: Signal label detection in the byte C2 – Signal label Mismatch detection.
• AIS or SSF is applied if TSF or Signal label Mismatch is detected


• Adaptation to PDH section layer:E4/P4x_A_So or E4/P4s_A_So

• It convert the internal signal code to the line code (CMI)


• signal conditioning for transmission medium ( e.g. electrical level, etc.).




• Input LOS detection.

• PDH physical Adaptation layer: E4/P4x_A_Sk or E4/P4s_A_Sk

• AIS detection and insertion.
• LOF detection (only in case of E4/P4x_A_Sk)


• PDH Section layer to Low Order Path layer Adaptation (LPA): S4/P4x_A_So or S4/P4s_A_So

• The signal label is inserted in C2

• High Order Path layer Trail Termination Function (HPT): S4_TT_So
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Side A

PPI PPI

E4 E4

E4/P4 E4/P4

LPA LPA

S4/P4 S4/P4

High Order Path
Layer

HPT HPT
S4 S4

W1 W2
From point Z1 To point Z2


Side B

Figure 107. 1660SM Block Diagram: signal management ( 140 Mbit/s PDH ports)
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3.4 ISA (Integrated Service Adapter) introduction

Today’s metropolitan and regional optical transmission networks need the flexibility to support new and
existing services.

As new data services overcome traditional voice services in terms of global traffic volume,

telecommunication operators face a host of challenges.
These include finding the optimal solution with the bandwidth to handle increasing data traffic, keeping
infrastructure updating investments to a minimum and protecting their high revenues on traditional voice
services.
Whereas core networks have to provide traffic with huge bandwidth capacity, metro and regional networks
need to focus on better aggregating traffic with refined dimensioning and improved network resource
allocation.
Integrated ”data–aware” features distributed along the optical transmission nodes of today’s metro
networks enable multi–service and multi–technology transmission of data services.
They optimize the network infrastructure and bandwidth allocation, giving carriers the twofold benefit of
reducing the need for extra investments in dedicated data equipment and safeguarding their high
revenues on traditional voice services.

Alcatel’s Integrated Service Adapter (ISA) series of plug–in cards are specially designed for the Optical
Multi–Service Nodes (OMSN) family (1660SM is part of this family) .
They enhance the optical transport network by adding data–aware features that are easy to introduce,
allowing carriers to efficiently and cost–effectively aggregate, switch and transport the expanding amount
of data services in their metropolitan network.
1660SM equipped with ISA plug–in cards give telecom operators a new generation modular platform for
multi–service SDH transport and further strengthen Alcatel’s leading position in the supply of optical
multi–technology transmission networks.

Whenever and wherever it is needed in the metro network, OMSNs extend their multi–service functionality
by integrating ISA plug–in ATM switching and Ethernet/Gigabit Ethernet rate–adaptive transport
capabilities into a single optical network element efficiently and cost–effectively. The ISA plug–ins bring
metro networks the switching intelligence needed to aggregate and groom mixes of different
packet–based data protocols and traditional TDM services (refer to Figure 108. on page 224).

ATM and Ethernet ISA cards are able to provide services such as ATM Virtual Private Networks,
Broadband Virtual Leased Lines and TLS.

The OMSN product family allows operators of SDH transport networks to introduce a wide variety of data
managed services including top–level differentiated QoS capabilities, variable service rates and traffic
congestion management.

Different types of ISA cards can be easily and quickly plugged into 1660SM. The system is modular and
the plug–ins can be chosen according to the specific application the optical multi–service equipment
needs to manage.

In the following will be explained the different ISA boards type and their application in the network:

– ISA – ATM (Asynchronous Transfer Mode) refer to paragraph 3.5 on page 225.

– ISA – PR_EA (Packet Ring Edge Aggregator) refer to paragraph 3.6 on page 234

– ISA – PR (Packet Ring) refer to paragraph 3.7 on page 245

– ISA – ETHERNET/FAST ETHERNET/GIGABIT ETHERNET refer to paragraph 3.8 on page 263
1AA 00014 0004 (9007) A4 – ALICE 04.10

– ISA – ES (Ethernet Switch) refer to paragraph 3.9 on page 281

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SAN

ISP1 UMTS
ISP2
RNC DWDM ATM
POS

Radio ATM LMDS

Optical Ring
Eth
DWDM/ MSN
O OMSN
Enterprise
DWDM ATM
DSL

CORE GbE
DSL

EDGE Residential

ACCESS Enterprise
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 108. Example of technology convergency with ISA boards in OMSN

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3.5 ISA – ATM management sub–system

3.5.1 ATM ( Asynchronous Transfer Mode) basic

Asynchronous Transfer Mode (ATM) is an International Telecommunication Union Telecommunication
Standardization Sector (ITU–T) standard for cell relay wherein information for multiple service types, such
as voice, video, or data, is conveyed in small, fixed–size cells. ATM networks are connection oriented. This
chapter provides summaries of ATM protocols, services, and operation.

According to ITU–T Recommendation I.311, an ATM transport network has two layers: the ATM layer and
the physical layer as shown in Table 35. .

Table 35. ATM transport network layered model

Higher layer

ATM layer VC (Virtual Channel) level

VP (Virtual Path) level
ATM Transport network
Physical Layer Transmission Path Level

Transmission Media Level

The ATM layer is subdivided into two levels: the VP level and the VC level.

The relations between the Virtual Channel, the Virtual Path and the Transmission Path are shown in
Figure 109. on page 225.

ÔÔÔÔÔÔÔÔÔÔÔÔÔÔ
VC VP VP VC
VC VP VP VC
Transmission Path

VC VP
ÔÔÔÔÔÔÔÔÔÔÔÔÔÔ VP VC

Figure 109. Relationship between the VC, the VP and the TP
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ATM transfers information in fixed –size unit called cells ; each cell consist of 53 octets, or bytes.
The first 5 bytes contain cell–header information and the remaining 48 contain the “payload” (user
information). Figure 110. on page 226 illustrates the basic format of an ATM cell.

8 Bits

HEADER (5 bytes)

53 Bytes
PAYLOAD (48 bytes)

Figure 110. Basic format of an ATM cell

An ATM network is made up of an ATM switch and ATM endpoints. An ATM switch is responsible for cell
transit through an ATM network. An ATM switch accepts the incoming cell from an ATM endpoint or
another ATM switch. It then reads and updates the cell–header information and quickly switches the cell
to an output interface toward its destination. An ATM endpoint (or end system) contains an ATM network
interface adapter. Examples of ATM endpoints are workstations, routers etc.

An ATM network consists of a set of ATM switches interconnected by point–to–point ATM links or
interfaces. ATM switches support two primary types of interfaces: UNI and NNI. The UNI connects ATM
end systems (such as hosts and routers) to an ATM switch. The NNI connects two ATM switches.
Depending on whether the switch is owned and located at the customers premises or publicly owned and
operated by the telephone company, UNI and NNI can be further subdivided into public and private UNIs
and NNIs. A private UNI connects an ATM endpoint and a private ATM switch. Its public counterpart
connects an ATM endpoint or private switch to a public switch. A private NNI connects two ATM switches
within the same private organization. A public one connects two ATM switches within the same public
organization (see Figure 111. on page 227).
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03
ATM
Switch

Private UNI
ATM
Switch

UNI
Private ATM Network

Pivate NNI
Public UNI

UNI

Figure 111. ATM network interface

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ATM

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Switch

Public NNI

UNI
ATM
Switch
Public ATM Network

227 / 706

An ATM cell header can be one of two formats: UNI or the NNI. The UNI header is used for communication
between ATM endpoints and ATM switches in private ATM networks. The NNI header is used for
communication between ATM switches. Figure 112. on page 228 depicts the basic ATM cell format, the
ATM UNI cell–header format, and the ATM NNI cell–header format.

8 Bits 8 Bits
HEADER (5 Bytes)

GFC VPI VPI
VPI
VCI VCI
PT CLP PT CLP
HEC HEC

53 Bytes
PAYLOAD (48 Bytes)

ATM UNI cell ATM NNI cell

GFC (Generic Flow Control)
Generic Flow Control field permits multiplexing the transmission of several terminals on
the same user interface. It is used for the traffic from the users to the network
VPI/VCI (Virtual Path Identifier / Virtual Channel Identifier)
The VPI/VCI field contains 24 bits on the UNI interface and 28 bits on the NNI interface.
The VPI field is 8 to 12 Bits, allowing 256 to 4096 virtual paths. Each path can consist of
64.000 VCIs. VPI/VCI identifies the next destination of a cell as it passes through a series
of ATM switches on the way to its destination.
PT (Payload Type)
Payload Type field id used to indicate different types of payload for OAM. It also
indicates ”end of packet” wich is used with ATM Adaptation Layer 5
CLP (Cell Loss Priority)
Cell Loss Priority bit is used for buffer managementin conjunction with congestion control
If it is set to 1, then the cell within a buffer could be discarded.
When the CLP bit is set to 0, the cell could not be discarded
HEC (Header Error Control)
Header Error Control field allows to either correct single bit errors or detect multiple
bit errors. If multiple bit errors are detected the cell is dropped.
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 112. UNI and NNI ATM cell header and payload

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3.5.2 ATM in1660SM

Optinex 1660SM can integrate ATM switch functionality through dedicated plug–in board.

Three ATM switch boards are available:

– ATM MATRIX 4X4 that provide a 622 Mb/s throughput (4xSTM–1 equivalent capacity); this board
includes a local STM–1 access port on the front panel.
Up to 16 TPs can be configured among VC–4, VC–3, VC12, E3 and E1.

– ATM MATRIX 4X4V2 that provide a 622 Mb/s throughput (4xSTM–1 equivalent capacity);
Up to 252 TPs can be configured among VC–4, VC4–C, VC–3, VC12, E3 and E1.

– ATM MATRIX 8X8 that provide a 1.2 Gb/s throughput (8xSTM–1 equivalent capacity)
Up to 32 TPs can be configured among VC–4, VC4–C, VC–3, VC12, E3 and E1.

If more capacity is needed more than one ATM board in a single 1660SM can be used.

The overall ATM Switch functional model is compliant to ITU–T I.731, I.732, ETSI EN 300 417–1–1/2–1,
af–tm–0010.002.

The board provide ATM traffic control functions, such as shaping (Input and Output) and policing (UPC,
NPC) which are needed to avoid network congestion (SCD, EPD, TPD).

The standard PDH and SDH ports of 1660SM can be used to transport ATM traffic streams.

The ATM traffic can be mapped on the VC–12, VC–3, VC–4 and VC–4–4c SDH Virtual Containers and
on E1, E3 PDH signals, in accordance with relevant ITU–T recommendations (G.804 and G.832 for ATM
over PDH and G.707 for ATM over SDH).

The following ATM connection types are supported:

• Permanent Virtual Connections (PVCs): Virtual Path Connections (VPCs) and Virtual
Channel Connections (VCCs ) provisioned by the TMN.

• Switched Virtual Connections (SVCs): VPCs or VCCs set–up end–to–end in real–time by
signaling procedures. Virtual Channel Connections (VCC) can be transparently tunnelled via
a Hard or Soft VP tunnel. (Note: UNI signalling is not supported).

Two instances of Permanent Virtual Connections (PVCs) are defined on network level:

• Hard PVC: Virtual Path Connections (VPC) and Virtual Channel Connections (VCC); it is a PVC
established/released upon a request initiated by a management request procedure (all the
nodes involved by the connections need to be configured by the Network Management).

• Soft PVC: Virtual Path Connections (Soft–VPC) and Virtual Channel Connections (Soft–VCC).
The P–NNI signalling and routing is supported according to af–pnni–0055.000,
af–pnni–0066.000 and af–pnni–0081.000.
In the scope of Soft–PVC the two connecting points contiguous to the connection end–points
are defined as calling end–point and called end–point: the former is responsible to start the
signaling process in order to establish the Soft–PVC and to restore the connection in case of
failures.
It is provisioned by the ATM–OS only in the calling and called endpoints and setup by means
of a signaling protocol, e.g. the PNNI, in all the other intermediate connecting points as if it is
a SVC. The routing of the soft–PVC is done by the calling endpoint by means of the PNNI
Routing Algorithm presenting every ATM board together with some network topology
knowledge.
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3.5.2.1 ATM point to point and point to multipoint connections

Uni–directional and bi–directional point–to–point ATM connections (VPC and VCC) are supported.
Uni–directional (for broadcast or dropcontinue usages) point–to–multipoint ATM connections (VPC and

VCC) are also supported.

The uni–directional point–to–multipoint ATM connection is supported via the Spatial (cell copy to different
interfaces) and Logical (cell copy to different flows on the same interface) Multicast feature of the ATM
switch.

3.5.2.2 ATM traffic management

According to ITU–T I.358 terminology (ATM–Forum TM4.1) the following ATM Transfer Capabilities (ATC)
are supported on all connections (see Table 36. on page 230).

Table 36. ATM traffic contracts.

ATM ITU–T Traffic type QoS class
FORUM parameter parameter
CBR DBR class 1 PCR0+1, CDVTPCR CTD, CDV, CLR0+1
–– DBR class 2 PCR0+1, CDVTPCR CLR0+1
UBR DBR class U PCR0+1, CDVTPCR ––
rt–VBR.1 SBR.1 class 1 PCR0+1, CDVTPCR, CTD, CDV, CLR0+1
SCR0+1, CDVTSCR
nrt–VBR.1 SBR.1 class 2 PCR0+1, CDVTPCR, CLR0+1
SCR0+1, CDVTSCR
nrt–VBR.2 SBR.2 class 3 PCR0+1, CDVTPCR, CLR0
SCR0+1, CDVTSCR
nrt–VBR.3 SBR.3 class 3 PCR0+1, CDVTPCR, CLR0
SCR0+1, CDVTSCR
GFR.2 GFR.2 PCR0+1, CDVTPCR, minimum CLR/FLR for
MCR0, MBS, MFL high priority cells/frame
Notes:
PCR: Peak Cell Rate
CDVT: Cell Delay Variation Tolerance
SCR: Sustainable Bit Rate
MCR: Minimum Cell Rate
MBS: Maximum Burst Size
CLR: Cell Loss Ratio

ATC and example of applications

CBR (Constant Bit Rate) / DBR (Deterministic Bit Rate):
Static amount of bandwidth that has to be reserved. Used for real–time application very sensitive to cell
delay variation like circuit emulation, video and voice at constant rate.

VBR (Variable Bit Rate ) / SBR ( Statical Bit Rate):
– Real Time ( rt ): those listed above but at variable rate
– Non –real–time ( nrt ) with bursty traffic: Banking transactions, Frame Relay services

UBR (Unspecified Bit Rate):
Non real–time application, best effort: Banking transactions, World Wide Web (WWW) E–mail, LAN
interconnection
1AA 00014 0004 (9007) A4 – ALICE 04.10

GFR (Guaranteed Frame Rate) :
Non –real–time application with minimum throughput guarantee. Traffic sent beyond this rate ( extra traf-
fic) will receive fair share of resource.

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The traffic contract is used as input to the Connection Admission Control (CAC) or Global CAC (GCAC)
for Soft–PVC in order to accept/reject the ATM connection.

Usage Parameter Control (UPC) can be performed at User–Network Interface (UNI) while Network

Parameter Control (NPC) can be performed at Network–Network Interface (NNI) or Inter–Carrier Interface

(ICI); UPC/NPC can be performed at VP and VC level.

Input Shaping can be performed in order to guarantee that incoming traffic is coherent with the resource
allocation performed by the CAC.
Output Shaping can be performed in order to guarantee that outgoing VPC is coherent with the resource
allocation performed by the CAC when several VCC are multiplexed in the outgoing VPC.

Congestion control and queues management are performed and alarms are generated accordingly.

Traffic and Congestion management is according to ITU–T I.371, ATM Forum af–tm–0056.000.

3.5.2.3 ATM OAM F4 and F5 flows

The ATM Switch board support the following OAM functionality at F4 (VP level) and F5 (VC level):

• Fault Management functions supported for all the supported ATM connections are Alarm
Indication Signal / Remote Defect Indication (AIS/RDI), Continuity Check (CC) defects and
Loop–back. Defects and possible subsequent failures are detected and reported.

• Performance Management (PM) functions are Forward Monitoring and reporting. The
supported ATM cell transfer outcomes are successful cell transfer, tagged cell transfer, errored
cells, lost cells, mis–inserted cells and severely errored cell–block. The supported ATM
performance parameters are Cell Loss Ratio, Cell mis–insertion Rate, Severely Errored Cell
Block Ratio, Cell Transfer Delay, and Cell Delay Variation; moreover, the
availability/unavailability status and parameters and the Severely Errored Second are
determined.

• Activation and De–activation of Performance Management (PM) and Continuity Check (CC) are
supported.

• Cell Insertion, extraction, non–intrusive monitoring and loop–back functions and the related
processing can be performed at F4 and F5 levels depending on the setting of VPC/VCC
end–points and segment end–points before and after the ATM Switching Matrix.

• OAM is performed according to ITU–T I.610. Performance and Availability according to I.356
and I.357.

3.5.2.4 ATM Virtual Path Group Protection (VPG)

The ATM VPG Protection is supported (on Hard–PVC) in order to facilitate fast ATM layer protection
switching in cases where the under–laying SDH protection mechanism is not used.
The uni–directional and bi–directional 1+1 and 1:1 VPG protection schemes are supported to allow
high–priority traffic protection eventually dropping in 1:1 scheme the low–priority traffic. The Signal Fail
is used as a switching trigger mechanism. VPG Protection follows ITU–T I.630.

3.5.2.5 ATM switching modules architecture

The ATM switch is cascaded to the SDH matrix via back–panel connection (see Figure 113. on page 232)
1AA 00014 0004 (9007) A4 – ALICE 04.10

In a given node, SDH VCs or PDH flows carrying ATM cells that do not require switching in the ATM layer,
at virtual path (VP) / virtual channel (VC) can be cross–connected transparently by the SDH matrix directly,
without unnecessarily loading the ATM switch (pass through functionality).

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OMSN Port Pass–through OMSN Port
traffic
RX TX

STM–
STM–4 STM–
STM–4
TX RX

SDH
OMSN Port Xconnection OMSN Port

RX TX
STM–
STM–1 STM–
STM–1
TX RX
Traffic
consolidation
OMSN Port OMSN Port

RX TX
STM–
STM–1 SDH MATRIX STM–
STM–1
TX RX

OMSN Port

RX –Cell switching
STM–
STM–1
TX

SDH
termination Local Port (*)
ATM TX
STM–
STM– 1
Traffic
policing and ENGINE RX port
shaping
– ATM Matrix

NOTES:
(*) Available only on ATM MATRIX 4X4

Figure 113. 1660SM with ATM Matrix architecture
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3.5.2.6 ATM switching modules application

The main application of the ATM board is to consolidate ATM traffic collected from different sources onto
shared SDH VCs (virtual containers) in STM–n rings and to switch the ATM traffic, as needed at VP and

/or VC level, into the network.

Wasted bandwidth

SDH circuits

E3 E3

E3 E3

E3 SDH VC–4 [3 X VC–3] E3
ADM ADM

Free bandwidth
Data flows
Consolidation

E3 E3
E3

STM–1
E3 SDH VC–4 [3 X VC–3]
E1
1660SM 1660SM
ATM board

Figure 114. Leased line service versus Data transport service

Typical applications of the atm board concept are ADSL, UMTS and LMDS metropolitan networks.

In all those scenarios the Provider can take great advantage of the distributed switching functionality for
optimizing the transmission resources avoiding wasting capacity not effectively used by the paying traffic.

The switch can also be used in FTTB scenarios and as CPE where a mix of TDM and ATM services in the
1AA 00014 0004 (9007) A4 – ALICE 04.10

same box results in benefits for both the Provider and the Customers.

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3.6 ISA – PR_EA (MPLS) sub–system

3.6.1 PR_EA (MPLS) generalities

The MPLS (Multi Protocol Label Switching) technique is used in Alcatel transport systems in order to
distribute and route data packets originated by the network layer (level 3 of the protocol stack) and
encapsulated into the Ethernet 802.3 frame; it can be seen as a “server” layer for the Ethernet “client”
layer (called “MPLS over SDH”). The data may also be “MPLS–packed” at the network edge, and
transported over Ethernet; this transport modality is called “MPLS over Ethernet”.

MPLS operates at the level 2 of the protocol stack and uses the SDH as its physical layer to transport and
aggregate the various streams of data packets (MPLS over SDH); see Table 37. on page 234. The “MPLS
over Ethernet” layering is illustrated in Table 38. page 234.
The MPLS technique consists of binding one or more “Labels” to the packets, in this way permitting the
forwarding of a packet to the other nodes of the network without inspecting the level 3 header, only the
look up of the attached label(s) is needed.
The classification of the incoming packets are performed only once, at the edge of the MPLS network; the
inner MPLS routers have only to select the “next hop” to which forwarding the incoming packets, by looking
the top label.

PR_EA (Packet Ring Edge Aggregator) is an Alcatel mark indicating a system that is able to aggregate,
at the edge of the MPLS network (ring topology), many mpls packets communications.
It is a “path oriented” connectionless service; all the packets belonging to the same stream and assigned
to the same class of service are all treated the same way by a router.
In other words, when they enter the network, the packets are assigned to a “Forwarding Equivalence
Class” (FEC); the subsequent packets with the same destination and the same quality of service are
assigned to the same FEC; also other packets belonging to different streams can be assigned to the same
FEC, in this way aggregating various packets streams to a common path.
This common path is called LSP (Label Switched Path) and can be treated by the intermediate nodes as
a tunnel.
The intermediate inner nodes have in charge the only forwarding of the packets, and all the incoming
packets within the same LSP will be forwarded toward the same direction.

For more information about MPLS refer to RFC_3031, RFC_3032, RFC_3209, RFC_3270, ITU–T_
Y1311, etc.

3 NETWORK any network “packetized” data service

ETHERNET
2 DATA LINK
MPLS

1 PHYSICAL SDH

Table 37. MPLS layer stack over SDH

3 NETWORK any network “packetized” data service

2 DATA LINK MPLS

1 PHYSICAL ETHERNET
1AA 00014 0004 (9007) A4 – ALICE 04.10

Table 38. MPLS layer stack over ETHERNET

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The Alcatel MPLS system can manage packets data streams transported over “local” Ethernet FE or GE
(Fast Ethernet, Gigabit Ethernet) and “remotized” ethernet over GFP/SDH; the packets are identified and
classified with a first label (by inspecting the ethernet frame header), marked again by the label switching
router with a second label, and then sent into the MPLS network, aggregated and encapsulated into

PPP/HDLC/SDH frames.

If coming from the MPLS network, the packets can be terminated towards the ethernet ports or routed
towards other routers, if possible they are also aggregated into a common FEC; the routing operation is
performed by the swapping of the top label.

The protocol stacking is illustrated in the figure below (Figure 115. ).
The MPLS framing among the various protocols is illustrated in Figure 116.
A generic example of MPLS tunnelling is illustrated in Figure 123. page 239.
A generic scheme of MPLS classification and aggregation is illustrated in Figure 124. page 240.

The protocol stacking is illustrated in the figure below (Figure 115. ).
The MPLS framing among the various protocols is illustrated in Figure 116.
The label and frames formats are illustrated in Figure 117. , Figure 118. , Figure 119. , Figure 120. ; the
GFP frame is reported in the “Ethernet” description, para. 3.8.3.1, page 265.

3 any 3 any 3 any
2 Eth Eth Eth
2 3 any
1 FE or GE MPLS MPLS
Eth
local 2 MPLS
FE,GE 2 MPLS
Ethernet CI PPP
Proc. MPLS
HDLC
1 SDH
MPLS SDH/HDLC MPLS
3 any over
3 any ROUTING Proc. SDH
2 Eth
2 Eth
GFP
MPLS
1 SDH
remote SDH/GFP
CI
Ethernet Proc.
over SDH

CLASSIFICATION

IDENTIFICATION

Figure 115. MPLS subsystem, protocol stacking
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Ethernet PRE FS DA SA DFL Ethernet Payload FCS

DA SA DFL Ethernet Payload FCS

Ethernet Packet

GFP GFP Header Ethernet Packet

Ethernet Packet

Label Label Ethernet Packet
MPLS 1 2

Labelled Packet (MPLS)

PPP PPP Header MPLS packet PPP
PAD

HDLC Flag Addr Control PPP frame FCS

HDLC frame
SDH
VC4 or VC3 or VC12 frame

POH SDH payload

GFP frame
SDH
VC4 or VC3 or VC12 frame

POH SDH payload
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 116. Framing for MPLS

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A generic MPLS label is illustrated below (refer to RFC 3032):

0 1 2 3

0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Label Exp S TTL

Label: Label Value (20 bits)

Exp: Experimental (3 bits)

S: Bottom of Stack (1 bit)

TTL: Time To Live (8 bits)

Figure 117. MPLS label format

Protocol Information Padding
8/16 bits a* b*

a* + b* = 1500

Figure 118. PPP frame

Flag Address Control
01111110 11111111 00000011

PPP
FRAME

FCS Flag Inter–Frame–Fill
16/32 bits 011111110 or next Address
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 119. HDLC frame with PPP encapsulation

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Preamble FS Dest. Add. Source Addr. DFL
( 7 bytes) (1) (6) (6) (2)

Data + Pad FCS
(46 to 1500) (4)

FS=start of frame delimiter; DFL=length of data field; FCS= frame checksum

Figure 120. Ethernet MAC 802.3 frame format

PR FS DA SA 1Q TCI L/T
(7B) (1) (6) (6) (2) (2) (2)

Data + Pad FCS
(46 to1500) (4)

PR: preamble
FS: Frame Start
DA: Dastination Address
SA: Source Address
1Q: 802.1Q field (a constant fixed value)
TCI: Tag Control Information= (3bits:user priority 802.1p)+(1bit:CFI)+(12 bits: VLAN identifier 802.1q);
CFI : Canonical Field Identifier

L/T: MAC client Lenght/Type

Figure 121. Ethernet “Tagged” MAC 802.3 frame format

+–––––+––––+––––+––––+–––––+––––+–––––+
| PRE | FS | DA | SA | L/T |MPLS Label|
|(7B) |(1) | (6)| (6)| (2) | (4) |
+–––––+––––+––––+––––+–––––+––––+–––––+
+––––––––––––––––––––––––+–––––––––+–––––+
| Data + Pad | FCS |
| (46 to 1500) | (4) |
+––––––––––––––––––––––––+–––––––––+–––––+
1AA 00014 0004 (9007) A4 – ALICE 04.10

PRE: preamble; FS: Frame Start; DA: Destination Addr.; SA: Source Addr.
L/T: MAC client Length/Type;

Figure 122. Ethernet frame format for “MPLS over Ethernet”

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
Originating Transport Transit Transport Terminating
Point Network Point Network Point

03
SDH Network SDH Network

SDH XC SDH XC SDH XC SDH XC
ETH Port
Ethernet ETH Port PPP Port PPP Port PPP Port PPP Port (Rate) Ethernet
Data (Rate) (Rate) (Rate) (Rate) (Rate) Data

MPLS Port MPLS Port MPLS Port MPLS Port

HEAD TRANSIT TAIL
OuterTunnel OuterTunnel OuterTunnel
(Label + TD) (Label + TD) (Label + TD)

HEAD TAIL
InnerTunnel InnerTunnel
(Label + TD) (Label + TD)

InFlow OutFlow InFlow OutFlow

Figure 123. MPLS Tunnelling Example
(TD) (TD)
Classifier
(Priority)

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(VLAN) ETS XC
ETS XC

– MPLS TUNNELLING EXAMPLE –

239 / 706

Classifier

VLAN#1

C
.
.
. ETS Flow InnerTunnel
(label)
C

. .
VLAN#i
Local or
Remote
Ethernet ETH
.
. .
.
Port
OUTER
TUNNEL MPLS PPP MPLS

.
. C
VLAN#m
(label) Port Port
over
SDH
. .
.
. ETS Flow InnerTunnel

.
(label)
C
. .
.
Local or
Remote
Ethernet
VLAN#n
. .
ETH InnerTunnel
C ETS Flow
Port VLAN#1...n (label)

.
.
Local or
Remote
.
Ethernet VLAN#1...n
ETH InnerTunnel
C ETS Flow

. .
Port
.
(label)

. . .
OUTER
Local or
Remote
Ethernet
. . . TUNNEL
(label)
ETH VLAN#1...n InnerTunnel
C ETS Flow
Port (label)

– GENERIC CLASSIFICATION AND AGGREGATION SCHEME AT AN ORIGINATING EDGE NODE –

NOTE:
1) at the terminating edge node the scheme is specular
2) at the intermediate MPLS nodes, only the outer tunnel is processed
3) the VLAN links may be speciffied individually or by a range, and may be addressed to a single or more ETSFlows

Figure 124. Generic MPLS aggregation scheme
1AA 00014 0004 (9007) A4 – ALICE 04.10

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3.6.2 PR_EA (MPLS) service in 1660SM equipment

The PR_EA (MPLS) subsystem permits the circulation and relevant traffic management of the MPLS data
packets through the SDH network.

The system allows the management of packet data services over Ethernet and their transportation over

the SDH network. The packets may be originated by any “packetized” service operating at level 3 of the
protocol stack. The ethernet packets are labelled and then mapped onto SDH frames via PPP/HDLC
framing.
In substance it performs the MPLS functions: classification, routing, aggregation of data packets.
Locally, at the network edge, the packets are received and delivered over ethernet links or over “remotized”
ethernet ports via GFP/SDH encapsulation; the ethernet links can be type E, FE, GE (10Mb/s, 100Mb/s,
1Gb/s).
The ethernet frames can be either “standard” as in Figure 120. or “802.1 Tagged” as in Figure 121.
The packets streams aggregation permits the use of one single interface per site, into a VPN (Virtual
Private Network) context, when several remote sites of the same VPN are connected between them,
passing through the MPLS network.
The MPLS traffic can be routed over 63 logical ports.
The ethernet SLA (Service Level Agreement) is managed by means of three types of QoS (Quality of
Service): Best Effort bandwidth (BE–BW), or Min–BW with regulated bursts, or Guaranteed constant BW.
The classification is based on 802.1p/q fields (up to 4096 VLAN identifiers and up to 8 priority values) of
the “Tagged MAC frame”, if present, otherwise it is automatically defined by the system.
Furthermore it provides the traffic congestion control. This is based upon 256 queues per “logical” port,
scheduled by means of HOL (Head Of Line) or WC–WFQ or WNC–WFQ (Work Conservative or Work Non
Conservative – Weighed Fair Queuing) methods. The congestion avoidance is based upon the W–RED
(Weighed – Random Early Discarding) method. The police function is accomplished by a “Dual–Rate
Leaky–Bucket”, based on PIR (Peak Information Rate) and CIR (Committed Information Rate) values of
the traffic contract.
“Fixed Share” or “VariableProportional Share” options are possible for Best–Effort traffic deployed in ring
topology.

The MPLS functions are implemented on PR_EA units that can be inserted into the 1660SM.
There are two versions of PR_EA board:
– the first version, it hosts a 4 x 10/100 BaseT Fast Ethernet module and the total traffic throughput
is 1 Gb/s, in which 622Mb/s are contributed by the SDH matrix, and 400 Mb/s contributed by the 4
Fast Ethernet local ports.
– the second version, it hosts a 1 x 1Gigabit Ethernet module and the total traffic throughput is 1.8
Gb/s, in which 622Mb/s are contributed by the SDH matrix, and 1.25 Gb/s contributed by the
GbEthernet local port.

The following table summarizes the interfaces that can accede to the MPLS functions:


SDH VC–12, VC–3, VC–4

PDH E1, E3, T3 not available in current rel.


Table 39. Interfaces acceding to the MPLS functions
1AA 00014 0004 (9007) A4 – ALICE 04.10

This subsystem is illustrated in Figure 125. page 244.
The description of the MPLS unit functional blocks is hereinafter reported; for the description of the blocks
belonging to the other units refer to their dedicated paragraphs of this handbook.

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The following are the main functional blocks implemented in the PR_EA Unit:

• SDH–MAP
It provides to deassemble the SDH virtual containers (toward MPLS direction), removing the

SDH OverHead, and to assemble them toward SDH direction, thus “loading” and “unloading”

the packets to/from the SDH frames (refer to ITU–T rec. G.707); the packets are then switched
toward GFP or HDLC processing, according to the logical ports configurations.

• HDLC
It provides: to deassemble (toward MPLS direction) the HDLC frames (High–Level Data Link
Control), removing the HDLC header; and to assemble them toward SDH direction; to
scrambler/descrambler the data; byte stuffing/destuffing. The HDLC frame format is reported
in Figure 119. page 237 (refer to rec. RFC 1662 and RFC 2615).

• PPP
It provides to deassemble (toward MPLS direction) the PPP frames (Point–to–Point Protocol),
removing the PPP header, and to assemble them toward SDH direction; the PPP frame format
is reported in Figure 118. page 237 (refer to rec. RFC 1661).
The “Martini Encapsulation” can be configured for the MPLS packets (substitution of ethernet
“FCS” field with an error check value consistent with the entire labelled packet).

• GFP
It provides to deassemble (toward MPLS direction) the GFP frames (Generic Framing
Procedure), removing the GFP header, and to assemble them toward SDH direction; the GFP
frame format is reported in para. 3.8, page 263 (refer to rec. ITU–T G7041). It supports
un–concatenated ethernet frames over unstructured VC4 payloads.

• PUSH1
It provides to “push in” the first label to the ethernet packet, after having inspected the ethernet
header, identified the destination and the class of service. It classifies the packets by decoding
the 802.1p/q “User Priority” and “VLAN–Tag” fields. Depending on the type of decoded or
negotiated ethernet SLA (Service Level Agreement), the stream can be associated with one of
three types of QoS (Quality of Service): Best Effort bandwidth (BE–BW), or Min–BW with
regulated bursts, or Guaranted constant BW. The label format is reported in Figure 117. page
237 (refer to rec. RFC 3032).

• POP1
It provides to “pop out” the label from the ethernet packet.

• PREAMBLE
It provides to remove (toward MPLS direction) the “preamble” and “start–of–frame–delimiter”
fields from the ethernet MAC 802.3 header (Medium Access Control), and to re–insert them
toward ethernet direction. Moreover it decodes the “Tag” fields of the MAC client header: 802.1p
and 802.1q. The ethernet FCS value is calculated too. The MAC frame is illustrated in
Figure 120. page 238 and Figure 121. page 238 (refer also to rec. IEEE 802.3).

• LOCAL PORT
This block represents a module that is mounted on the board and, according to the the module,
it distinguishes the type of unit.
The three possible types of module are:
4xFE: it contains 4 Fast Ethernet transceiver interfaces type 10/100Base–T, each
interface allowing a local connection to a LAN at auto–negotiable rates 10 or 100 Mb/s.
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1xGbE: it contains 1 small–form Gigabit Ethernet optical transceiver, implementing the
optical/electric conversion and a full–duplex Gigabit Ethernet interface at 1.25 Gb/s, as
specified in IEEE–802.3.

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• QUEUING MANAGER
It provides to monitor the load of traffic in the local router, and to take measures for preventing
the congestions, supported by the intra–board MPLS microcontroller. The priority management
is based on the ethernet SLA (Service Level Agreement), three types of QoS (Quality of Service)

are available: Best Effort bandwidth (BE–BW), Min–BW with regulated bursts, Guaranted

constant BW. The traffic management is based upon 256 queues per “logical” port (63 available
logical ports); scheduled by means of HOL or WC–WFQ or WNC–WFQ methods; congestion
avoidance via W–RED method; police service by means of CIR and PIR parameters: a
“Dual–Rate Leaky–Bucket” police mechanism is used (it can be seen as two cascaded leaky
buckets, the first based on PIR value, the second on CIR). In case of congestion, only the low
priority traffic will be cut–off, while the high priority traffic maintains the guaranted BW.
The Best–Effort traffic deployed in ring topology can be associated to a “Fixed Share” of the total
available band, or to a “VariableProportional Share”. In case of congestion the BE excess
traffic will be cut–off via W–RED.
Packets shorter than the minimum ethernet frame are silently discarded. Packets longer than
the maximum frame are silently discarded. The discarded packets are counted by the PM
function.
Note: the priority and the BW parameters (classification) are marked on the first label, at the
“PUSH1” function of the ingress node.

• MPLS ROUTING
It performs, supported by the local microcontroller, the routing functions by looking the top
MPLS label; it can forward the packets streams to up to 63 SDH or ethernet ports.
In the MPLS network, it provides to inspect the top label of the MPLS packet in order to identify
the incoming FEC and LSP; if possible, it aggregates the packet to other packets streams on
a common path, then it selects the forwarding to a next hop by swapping the top label.
At the edge of the MPLS network (originating node), on receiving packets from the local or
remote ethernet interfaces, it provides to push the top label reporting information for the routing
procedure (LSP and FEC).
At the edge of the MPLS network (destination node), on receiving packets from the network,
it provides to pop out the top label and drops them to the destination end port.
At the beginning of a packets stream introduction, the microcontroller starts the RSVP–TE
signalling (Resource Reservation Protocol – Traffic Engineered Tunnel) in order to search and
establish a path with a certain band capacity and a given priority, between the destination and
the source node; this path can be treated as a tunnel and is called LSP (Label Switched Path);
once the LSP has been established, the RSVP signalling finishes and starts the Label
Distribution Protocol (LDP) signalling, that informs all the nodes of the network to maintain the
label bindings for the relevant established LSP. The RSVP and LDP signalling are in–band
communications between the local and remote microcontrollers.

• MPLS CONTROLLER
It is a local microcontroller managing and supporting the MPLS functionalities, such as:
The RSVP–TE and LDP communications between the destination and the origination nodes,
in order to establish the routing and the LSP tunnelling.
Management of communications with the network Operations System (OS), by means of
SNMP (Simple Network Management Protocol) messaging for MPLS network configuration.
Configuration of the MPLS functions implemented by the devices on the board, by means of
ICMP (Internet Control Message Protocol) messaging.
Collection of alarms and status of the MPLS functions.
Management of the Performance Monitoring (PM) function for MPLS.
Management of Multicast traffic.
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Management of OSPF (Open Shortest Path First) routing (not operative).
Furthermore it aids the congestion control function, supporting the “Queuing Manager”.

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MPLS Unit

MPLS
CONTROLLER QUEUING
MANAGER

MPLS
ROUTING

PUSH1 PPP POP1 PPP
POP1 PUSH1

LOCAL PORT GFP HDLC GFP HDLC
ETH PREAMBLE
local 4xFE
access or
1xGbE

SDH SDH–MAP

SDH unit MATRIX unit SDH unit

MPLS SDH MPLS
over SDH SDH over
SDH PORTS CONNECTION PORTS SDH

sc

PQ2/EQC unit

EC PDH SDH FE GbE
UNITS UNITS UNITS UNITS

MPLS over PDH over SDH over FE over GbE

NOTES:
1) FE = Fast Ethernet 10/100Mb/s; GbE = Gigabit Ethernet 1.25Gb/s
2) 4xFE or 1xGbE local ports are alternative and are mounted on three different boards
3) MPLS over PDH is not available in current release

Figure 125. MPLS subsystem
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3.7 ISA – PR Subsystem

3.7.1 PR Generalities

The role of the ISA–PR (Internetworking Services Architecture – Packet Ring) functionality inside 1660SM
is to provide a shared carrier–class Ethernet Packet Ring:

• embedded physically into the SDH infrastructure, in which case the embedded Packet Ring is
provided in a flexible manner over SDH Virtual Containers (VC–4–Xv)

or alternatively

• connected directly to independent fibers to create a Packet Ring over single or dual STM4.

ISA–PR Deployment Scenario is presented on next Figure 16.

ISA–PR aggregates and transports Metro Ethernet traffic within a metro access or metro core SDH access
ring/rings, all packet traffic is statistically multiplexed, with multiple Classes of Services and guaranteed
QoS support (according to the defined SLA).

The ISA–PR is effectively an Ethernet Add–Drop Multiplexer (ADM) sub–system, which operates as a
embedded Overlay ”Packet–Ring” transported over an 1660SM SDH ring at flexible rates.

The ISA–PR provides a number of primary functions including:

– Statistical sharing of ring bandwidth between Metro Ethernet ports/services (including spatial reuse)
to ensure maximum bandwidth efficiency

– Aggregates Ethernet traffic from multiple edge Ethernet ports (e.g. other ISA–Eth, ISA–PR_EA
cards) onto GbE uplinks at the central gateway node

– Traffic Management at the customer and flow level

• Three distinct classes of service to cater for different application requirements.

• Enforceable customer SLA’s (Service Level Agreement)

– Supports point–to–point, point–to–multipoint and multipoint connections, enabling the delivery of
basic and value–added Metro Ethernet services

– Provides multiple physical Ethernet access interfaces (10/100Mbps and GbE interfaces) to both
customer and core network devices
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3.7.2 PR in 1660SM

The ISA–PR is a self contained, independent sub–system operating in the OMSN 1660SM chassis, it is
not connected to the rest of the node from a system perspective except for the drawing of power from the

backplane; (i.e. in order to function it requires only the Congi card to be present in the chassis)

The ISA–PR Sub–System can operate in two embedded ring modes: ”Overlay” and ”Independent”.

• In Overlay mode ISA–PR sub–systems communicates via external cabling into the 1660 switch
matrix cards and shares fiber with other traffic (TDM, ATM). See Figure 126.
• In Independent mode the ISA–PR nodes connects directly to a dedicated fiber ring, thus
creating a standalone packet ring. See Figure 127.

Overlay mode is typically used to integrate into an existing SDH Ring or where additional fiber pairs are
not available, which requires the provision of STM4 cards to connect the ISA–PR subsystem into the
matrix.
Independent mode is useful when the availability of additional fiber pairs and/or the requirement for data
only transmission makes creating a standalone ring a viable option.

There are currently three card variants that make up the ISA–PR sub–system:

1) ISA–PR – Port card: four STM–4 interfaces are supported which connect either into the
1660SM Matrix via STM–4 port cards (overlay mode) or directly over dark fiber or DWDM layer
(independent mode).

2) 16FEA–PR – 10/100 Ethernet Access card –: sixteen (16) 10/100 FE (Fast Ethernet)
interfaces are supported.

3) 2GBA–PR – 2 Gigabit Ethernet Access card –: up to two (2) GbE (Gigabit Ethernet) interfaces
are supported

All optical interfaces are based on SFP optical transceiver modules.
A single Port card must be installed working in conjunction with one or two Access cards;
Possible access interface combinations are:

• 16 or 32 x 100BaseTX
• 16 x 100BaseT + 2 x GbE
• 2 or 4 GbE

An ISA–block diagram is also presented in Figure 99. on page 197
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Three 1.25 Gb/s Backplane
Bus Connections connect
Access cards to Port Card
(one bus for control signals)

Upto 2 Access Cards

Ethernet 10/100 per Port card Single or Dual STM 4 Output of
or 1000 Mb/s Ports ISA PR Port card is cable via
optic fibre to STM 4 tributary
card(s). MPLS Packet Ring
Framing format is VC–4–Xv

ISA – PR ISA – PR
ISA PR
Access Card Port Card
ISA – Access Cards:
PR Card or GbE
FE
Card
*16 x 10/100 Ethernet TX
* 2 x 1000 GbE SFP

To Ring
Dual SDH
SDH
Trib Card Port
STM–4 Matrix
Trib
Card

Figure 126. ISA–PR Sub–System Architecture (Overlay Mode)

Three 1.25 Gb/s Backplane
Bus Connections connect
Access cards to Port Card
(one bus for control signals)
Upto 2 Access Cards
per Port card
Ethernet 10/100
or 1000 Mb/s Ports

– ISA – PR
ISA PR ISA – PR
Access Card
Access Port Card
Port
VC –4–Xv
Card or GbE
FE
Card
Packet Ring
ISA PR Access Cards:
*16 x 10/100 Ethernet TX
* 2 x 1000 GbE SFP

–

Single (or Dual) STM 4 Output
of ISA PR Port card is directly
to fibre pair to create an data
Packet Ring. MPLS Packet
Ring Framing format is VC–4Xv
over STM4
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Figure 127. ISA–PR Sub–System Architecture (Independent Mode)

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1 ) ISA–PR Port card
The ISA–PR Port Card supports up to four STM–4 interfaces and it works in conjunction with one or
two Access cards plugged into the correspondent access slots, as depicted in next Figure 126. and
Figure 127. Each ISA–PR port card requires two chassis slots.

The ISA–PR may be plugged into any PORT slot in the 1660SM, apart from the slots dedicated to

Controller and Switch cards. Multiple ISA–PR sub–systems may be installed in a single 1660SM
system.
The STM–4 pluggable module, which can be plugged, independently into each port on the ISA–PR
PORT card and provides a range of options for the physical interfaces; they are named Small
Formfactor Pluggable (SFP) Transceivers and they can be considered as independent items
hardware, in fact they have an own Remote Inventory.
At the moment the type of Small Form–Factor Pluggable Transceivers provided is:

STM–4 Short Haul optical interface (approx 2kms) – SS–4.1

2 ) 16FEA–PR Access card: Sixteen (16) 10/100 Fast Ethernet interfaces are supported.
The 16FEA–PR board supports sixteen 10/100 TX (copper RJ45) Ethernet interfaces on this access
card which work in conjunction with the ISA–PR Port card plugged into the correspondent port slot,
by adding a second 16FEA–PR card up to thirty two 10/100 interfaces may be supported per ISA–PR
sub–system.

The 16FEA–PR may be plugged into any Access slot in the 1660SM, apart from slots dedicated to
common cards; e.g. Congi.

3 ) 2GBA–PR Access card: Two (2) GBE interfaces are supported (via SFP optical modules)
The 2GBA–PR board supports two 1000 SX/LX/ZX Ethernet interfaces on this access card which
work in conjunction with the ISA–PR Port card plugged into the correspondent port slot, by adding
a second 2GBA–PR card up to four GbE interfaces may be support per ISA–PR sub–system.
The 2GBA–PR may be plugged into any Access slot in the 1660SM, apart from slots dedicated to
common cards.

The GbE interfaces are Provided via a pluggable module, which can be plugged, independently into
each port on the 2GBA–PR access card and provides a range of options for the physical interface;,
in fact they have an own Remote Inventory.

At the moment three types of SFP Transceivers are provided:

GbE Long Haul optical interface 1000BASE–LX, extended 10km reach

GbE Short Haul optical interface 1000BASE–SX, 500m reach

1000BASE–ZX, 80 Km reach

ISA–PR supports up to 100 milliseconds of differential delay between Virtual Concatenation timeslots.

The ISA–PR port card and Access cards (2GBA–PR and 16FEA–PR) communicate over the 1660SM
backplane using three 1.25Gb/s communication channels. The ISA–PR port card connects the virtual
Packet Ring into the SDH physical ring using external optical cabling to one or more STM–4 interface
modules installed in the 1660SM system (Note: it is possible that these connections could be to another
16xx system).
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Main functional aspects of the ISA–PR:
1660SM when equipped with ISA–PR sub–system will allow point–to–point and multipoint–to–multipoint
Metro Ethernet connections between routers or switches through SDH, as depicted Figure 16.
The Packet Ring maps Ethernet over MPLS over POS and shares the bandwidth between hundreds of

Ethernet traffic flows according to the defined SLA.

The bandwidth in this Packet Ring may, and likely will, be oversubscribed; hence sophisticated traffic
management functions are provided to ensure the service SLAs are adhered to.

All the Ethernet access connectors are on the front panel of the 2GBA–PR and 16FEA–PR cards.
A full–blown configuration constitutes two or three cards.
An ISA–PR Port card and at least one of either an 2GBA–PR and/or 16FEA–PR Access card, which
provide various combinations of 10/100 and GbE interfaces.

ISA–PR ”Overlay” Packet Ring provides:

• Layer 1 – STM–4 (or dual STM–4)
• Layer ”1.5” – MPLS over PPP/HDLC Packet Ring multiplexed over VC–4–4v, VC–4–6v and
VC–4–8v
• Ring protection is executed at the overlay L1.5 level
• Ring operational modes: Uni–directional and [future] Bi–directional

The ISA–PR Ethernet Packet Ring bandwidth is constructed from a virtually concatenated SDH path in
the form VC–4–xv (where x=4, 6, 8). This Packet Ring provides sub–50ms protection by employing packet
wrapping to ensure restoration or traffic under ring or node failure conditions.

The ISA–PR board provides the operator with the flexibility to provision the mapping between the ISA–PR
port STM–4 interfaces and the SDH Ring; in this way the operator can choose the mapping which he thinks
more appropriate:

ISA–PR provides the following concatenation options over a single STM–4 interface:

• VC–4–4c over a single STM–4 interface
• VC–4–4v over a single STM–4 interface

ISA–PR provides the following concatenation options over dual STM–4 physical interfaces:
• VC–4–6v over two STM–4 interfaces
• VC–4–8v over two STM–4 interfaces

Ethernet frames arriving onto the ports of an 2GBA–PR and 16FEA–PR Access card are firstly classified
to determine priority and destination, placed in the appropriate priority queue and then mapped, according
to SLA rules, into the Packet Ring via the ISA–PR Port card – the mapping used is
Ethernet/MPLS/POS/SDH.

The output of the ISA–PR port card uses either two or four STM–4 optical outputs, which are connected
externally (via optical cable) into one or more 1660 SM STM–4 tributary cards toward the SDH matrix, then
through the back–Plane and finally out onto the physical SDH ring as an overlay embedded Packet Ring.
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ISA–PR Traffic Management

ISA–PR supports Ethernet traffic management, fully compliant with the MEF specifications. The basic
concepts for the ISA–PR traffic management at all tributary ports are described in the following and

depicted in Figure 128. and Figure 130.

Figure 128. provides a high level overview of the traffic flow and processing in the ISA–PR series
modules. The figure depicts the traffic flow from ingress node to egress node – left to right, and load
balancing control flow – right to left. The pipeline is composed of some main processing steps that are
described in the next.

INGRESS NODE EGRESS NODE

Load Balancing
Local feedback Network–wide feedback

Network Buffer Buffer Network
Policer Shaper ADM RING ADM
Processor Manager Manager Processor

Classifier – Limits in- Buffers Regu- Adds in- Extracts Switches Editor of
Determines gress BW and lates gress traf- “drop” traffic egress packet
EVC CoS. according switches traffic fic into the from the ring. traffic headers.
Editor of pack- to SLA ingress flow into ring Classifier – Layer 2
et headers. and BW traffic the ring Determines based func-
Layer 2 based availability EVC QoS tionality.
functionality.

Figure 128. Traffic flow and processing in 1660 SM
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3.7.2.1 Ingress processing

Classification

Every packet entering through a tributary port is classified to identify the EVC it belongs to, and its CoS.

Classification may occasionally result in a decision to discard the packet because it is not valid or does
not belong to any of the provisioned EVCs; i.e. a misrouted packet.

Validation

Incoming packets are validated according to:

– Correct Packet Format; Ethernet frame format as per IEEE 802.3 including
• 802.3
• 802.1Q
• Multiple stacked VLAN
• Ethernet frame encapsulating MPLS payload (e.g. According to the Martini draft)

– Packet Size
• Minimum – 64 Bytes
• Maximum – 1574 Bytes

– Valid CRC.

EVC

ISA–PR can be provisioned to use the following criteria to determine the EVC, used to forward the packet:
– Input access Port
– Destination MAC address
– MPLS pseudo–wire label (according to IETF Martini draft ETH over MPLS) with Tri–Color marking
(L–LSP mode)
– Combinations of the above; e.g. Port + MPLS + VLAN

Priority indications, discussed below, may not be used to determine the EVC. They are used to determine
the order in which packets are forwarded across the EVC.

COS

Packet classification by CoS is required to differentiate between customer applications. For example, a
videoconference over IP carried over the Ethernet network will require low delay through the network. At
the other extreme, applications such as web browsing, are fairly tolerant to delay. Such applications also
exibit uneven traffic distribution over time and are therefore more suitable for statistical multiplexing.

ISA–PR implements three CoS: High, Medium and Low.

Delay and Delay Variation, associated with each CoS, may be customized using 1354BM–PR NMS; e.g.
by setting a limit for total delay sensitive traffic.

1354BM–PR default parameters address typical use of these CoS:
• High – Delay sensitive applications; e.g. VoIP
• Medium – moderately Delay sensitive applications; e.g. interface Client – Server
• Low – Delay insensitive applications; e.g. e–mail.
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ISA–PR may be provisioned to use the following criteria to determine the CoS of the packet:

• 802.1p
– IP TOS/DiffServ

– MPLS Exp

– MPLS Tricolor scheme.
– Fixed CoS; i.e. independent of any indication within the packet.

The rationale for using the Fixed CoS criterion is mostly Customer Equipment inability to support any of
the other criteria.

Layer 2 Based Functionality

Layer 2 Based FunctionalityI herein refers to any decisions, based on MAC address. This includes:
• identifying the EVC, when provisioned to an E–LAN service
• selective processing of Layer 2 control protocols.
Both functions above are tightly related to MEF service standards.

When provisioned to an E–LAN service, ISA–PR learns the MAC address of the connected equipment and
forwards packets accordingly.
Layer 2 control protocols are identified using the standard MAC addresses. Selective processing allows
1354BM–PR to provision ISA–PR to either block; i.e. discard the control protocol packets or tunnel; i.e.
forward them. The most useful example is blocking the Spanning Tree at an interface to ISP.

Editing

Editing is not functionally associated with Classification. It is described here because ISA–PR implements
Editing by Network Processor, which also implements Classification. On Classification completion packet
may be optionally edited to modify its header/s.

Supported packet editing options are:
• append VLAN
• swap VLAN
• strip VLAN
• strip MPLS
The rationale for header editing is needed to mediate between different paradigms, usde by the connecting
networks; e.g.between MPLS and Q–in–Q paradigms; as well as potential tag uniqueness challenges,
when certain values are already in use and therefore require swap to another value.

Classifier is able to process any blend of ingress packet lenghts at wire–speed. Under no circumnstances
will it discard a packet due to inability to process it.

On classification completion Classifier forwards valid packets to the Policer, along with their EVC and CoS
identifiers and the MPLS label identifying the EVC across the ring.
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Policing

ISA–PR implements policing to enforce traffic parameters as contracted between the customer and the
provider. Policing supports all the three modules specified by MEF; i.e. policing per:

• UNI

• EVC
• EVC.CoS

The standard set of attributes for each of the model is above is
• CIR (committed information rate)
• CBS (committed burst size)
• EIR (excess information rate)
• EBS (excess burst size)

The outcome of policing is colour marking of the packet. The effect of this marking is as follows
• green packets are delivered unconditionally
• yellow packets are delivered only if the network has available resources
• red packets are discarded.
Figure 129. depicts the policing function.

– CIR = committer information rate Burst window size (bytes)
– CBS = burst window size at the CIR
– EIR = excess information rate PBS
– EBS = burst window size at the EIR
Yellow
EBS

CBS
EIR
Green
Rate (bps)

CIR PIR

Figure 129. ISA–PR Policing

This policing scheme decouples BW profile; i.e. CIR vs. EIR, from CoS. This allows to fix for every
application the mix of attributes it needs. Some examples:
• client/server applications – CIR 0, EIR = 0, CoS = Medium
• voice – CIR 0, EIR = 0, CoS = High
• broadcast TV – CIR 0, EIR = 0, CoS = Low
• residential internet access – CIR 0, EIR = 0, CoS = Low
• VPN for multiple applications – CIR 0, EIR = 0, CoS = High/Medium/Low (derived from priority
indication within the packet)
In addition to the standard settind ISA–PR implements a proprietary bunding feature. The use of bunding
is optional and does not contradict any of the MEF applications. It improves the performance of the per
EVC policing by protecting a higher CoS traffic from undesirable effects of bursts of lower CoS traffic. This
allows the customer to better utilise his bandwith by using a single service for all of his VPN applications.

Policing attributes the granularity
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• CIR, EIR – 100 Kbps
• CBS, EBS – 1 Kbyte
Policed packets are passed to the Buffer Manager which places them at appropriate queue/s.

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Buffer Management

Buffer Management maintains packet memory, structured into multiple queues each queue serving a
particular destination and CoS; i.e. three queues per destination.

It also maintains various queue fill level thresholds to maintain priorization between CoS, prevent any

queue from monopolizing the memory and provide triggers for load balancing.
Load balancing packets are issued after a fixed number of yellow bytes is delivered from a channel.
Upon reaching the first stress level, indicated by queue depth increasing beyond a threshold, buffer
management issues a stress signal to local policers that is increasing in queue depth.
Upon reaching a higher threshold it starts discarding the yellow packets.
Upon reaching a yet higher threshold, which indicates maximum queue occupancy, it discards all arriving
packets.

Shaping

Shaping controls the rate and the order at which packets are injected into the ring.
The total Bandwidth per destination may be determined to either wide NMS as fixed number or dynamically
changed by the load balancing mechanism.
Selection between the two modes is performed by NMS.
The bandwidth per destination is shared between the various queues in decreasing CoS order; i.e. High
packets are forwarded first, Medium next and Low last.

ADM

The ADM function maps packets into the synchronous SDH payload.
The applicable payloads are VC4–4v, VC4–5v, VC4–6v, VC4–7v, VC4–8v.
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Ingress summary

Figure 130. summarises ingress processing.

MEF policer
CIR EIR Discard
Packets output to ring:
Packets are output onto the ring
into the appropriate Virtual trunk (VT)
for the CoS Destination node/port
Packet analysis(B):
Policing: Packets are put into queues
MEF policing with CIR+ based on header priority and SDH
EIR SLS. Either per UNI destination port out
Per EVC Queues
Packet analysis(A): Per EVC.CoS Destination A
NN proprietary bundling
Classified by service
Based on header and High
port info
Medium

Packet Labeling Low
Martini Labels are
stripped, and internal
MPLS Labels are added Scheduler
Destination B
High
Medium

Low

Aggregate SDH
Stress Shapers in
Queue filling feedback
Similar to R.E.D

Access card Port card
NP Policer BM ADM

Figure 130. ISA–PR Traffic Management Overview

Every packet is assigned an identifier detailing customer, SLA and traffic flow. i.e. where is the packet to
be delivered, which priority is the packet given internally. These classified or tagged packets are then
managed at wire speed, creating a breakthrough in service agility.
Service providers can now market and deliver differentiated services – and importantly, more than one
data service per customer interface – to hundreds of customers over a single, shared fibre or wavelength
of capacity.
ISA–PR functions as a Layer 2 device, so the Ethernet connectivity it provides is transparent to the
customer. Therefore any L2 protocol used by the customer, such as spanning tree, can be delivered
unaffected, unless explicitly provisioned to filter them out.
Sophisticated traffic–engineering algorithms ensure that, on a per–flow, per–node and per–ring basis, all
SLAs configured on all network elements are met.
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3.7.2.2 Egress processing

Egress processing is much simpler than Ingress processing. It involves no extensive classification and no
policing.

ADM

The ADM function selectively drops packets into the node, based on their MPLS labels and identifiers their
EVC and CoS. Per packet decision by ADM may result in either:
– drop
– drop and forward
– forward
– discard.

Buffer Management

Buffer management maintains packet memory, structured into queues, each queue serving a 1Gbps
interface between Port and Access card and CoS; i.e. three queues per every one of the 4 interfaces. It
also maintains various queue fill level thresholds to maintain prioritisation between CoS, prevent any
queue from monopolizing the memory and provide triggers for load balancing.
Upon reaching the load balancing threshold buffer management issues a flow control packet.
Upon reaching a higher threshold it starts discarding the yellow packets.
Upon reaching a yet higher threshold, which indicates maximum queue occupancy it discards all arriving
packets.
Buffer Management forwards packets to the Access cards as long as the interface between the cards is
free to do so; i.e. without any shaping.

Editing

Egress Editing may be provisioned to append an MPLS header, if any of the Ethernet ports on that Access
card is configured as a Martini interface.
Editing is applied by the Network Processor.

L2 Switching

Egress L2 Switching comprises MAC based filtering and MAC learning.
L2 Switching is applied by the Network Processor.

Egress Buffering

Egress Buffer Management maintains packet memory, structured into queues, each queue serving an
Ethernet port and CoS; i.e. three queues per every one of the 16 Fast Ethernet in ISA–16FEA card or 2
Gigabit Ethernet in ISA–2GBA card.
Egress Buffer Management forwards packets across the Ethernet ports as long as the interface between
the ports are available; no failure and no flow control applied by the connected device.
Egress Buffering is applied by the Network Processor.
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Load Balancing

In order to prevent congestion in the ring each ISA–PR monitors the traffic, identifies congestion
conditions, communicates its status to other ISA–PR and responds to congestion reports by other

ISA–PR. This set of functions is collectively referred to as ”Load Balancing”.

Both ADM and Buffer Manager participate in Load Balancing.

Communicating the congestion status is done using OAM–like packets, called LB–OAM.
Each ISA–PR generates LB–OAM packets that traverse all the paths, originating at that ISA–PR.
While traversing the ring LB–OAM packets are stamped with the congestion levels of the bottlenecks
encountered in the path. At the end of the path the packets are sent back to their source ISA–PR.
In response to the congestion in the path, the originating ISA–PR adjusts the channel BW in order to
reduce the load of traffic in congested bottlenecks.
Adjusting the channel BW takes into account the relative SLA satisfaction of the affected services and
hence achieves fairness.

Channels

Channels are virtual pipes that aggregate traffic in the ring.
Each channel aggregates traffic that originates from a single ISA–PR and goes to one or more
destinations.
The total BW of the services in a channel is limited by the channel BW.
The originating ISA–PR controls the BW of each channel.
Traffic management uses channels to adjust ring traffic so the total forwarded traffic does not exceed the
available resources in any point in the ring.
In case of congestion the BW of channels that contribute to the congestion will be reduced and the
congestion will be relieved.
Reducing the bandwidth of a channel will cause the originating network element to forward less traffic
through the services of that channel. The reduction in bandwidth will take into consideration the SLA of
services in the channel and maintain fairness between customers.

Traffic in the physical network is divided into channels. Each channel carries traffic of multiple services.

Figure 131. Channels
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Bottlenecks

Each ISA–PR monitors the traffic traversing it on a number of ”bottlenecks”.
Bottlenecks are convergence points in the ring that might be congested when traffic load increases.

There are both Ingress and Egress bottlenecks.

Figure 132. Bottlenecks

Congestion Indications

Whenever a bottleneck is congested the node will notify the other nodes in the ring of the congestion by
sending a ”congestion indication”. The congestion indication reports the location of the congestion.
In reaction, each node reduces the allocated bandwidth to the channels that send traffic toward the
congested bottleneck, thereby relieving the congestion.
In case of severe congestion, the congested network element will send repeating congestion indications
causing larger bandwidth reduction in the relevant channels.

Fairness

Even in times of congestion on the ring, the ISA–PR assures that
– CIR is not affected
– EIR is affected in a fair manner
Reduction will be relative to the amount of BW the customer bought.
Maintaining fairness will be done by balancing the level of ”satisfaction” of channels in the network.
The level of satisfaction of a channel represents the difference between the amount of forwarded EIR traffic
and the amount of conforming EIR traffic, submitted by the customers.
”Non–conforming” traffic; i.e. traffic exceeding SLA BW, is marked Red by the Policer and not taken into
consideration for ”satisfaction” purposes.
The load balancing mechanism increases the BW of channels, which are more affected by the traffic load
while reducing BW of other channels, which are more ”satisfied”.
The bandwidth of each channel will be reduced whenever it gets a congestion indication. If a congestion
indication is not received during a period of time the channel bandwidth will be increased.
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3.7.2.3 Protection sub–system

The following protection mechanisms are provided:

– native packet ring protection, refer to point [1] on page 259

– Dual Attach, refer to point [2] on page 260.

– Customer Edge (CE) Dual Homing, refer to point [3] on page 261.

[1] Packet ring protection

The packet protection is provided by the MPLS–based Resilient Packet Ring (RPR) technology, via
“Wrapping” mechanism (see Figure 133. on page 259).
RPR is currently being standardized by the IEEE 802.17 Working Group and specifies a technology for
packet–based transport in ring topologies defining special functions that offer fast fault location and trigger
fast switchover at packet level.
RPR is used to optimize and manage the portion of bandwidth dedicated to packet traffic in SDH networks.
An RPR topology consists of two counter rotating fiber rings (or portion of SDH fiber rings bandwidth) in
which multiple nodes share the whole bandwidth (see Figure 133. on page 259)
Negotiation for bandwidth occurs among the nodes through specific fairness mechanism that guarantees
fair bandwidth allocation for customer traffic per each node. Nodes can send packets to other nodes either
by utilizing unicast (point–to–point) or multicast (multipoint) destinations, which enables multipoint
Ethernet VPN and Ethernet aggregation services be implemented over RPR.
When sending a packet, the node determines which ring direction to use, so the spans in the opposite
direction remains free for other customer traffic sent by other nodes.
A packet traveling on the ring is stripped by the destination node. This means that the packet does not use
all the ring bandwidth but only the span that it requires to go from source to destination. This features is
called “spatial reuse” as the bandwidth of the other span of the ring can be used by other paying traffic.
RPR protection protocol provides sub–50msec resilience for traffic in case of fiber or node failure.
Specific control packets are exchanged among the nodes to keep the ring constantly monitored.
“Wrapping” mechanisms is provided for packet protection switch accomplished by merging the frames
destined at the failed segment, into payload destined at the opposite direction by node adjacent to the
failed segment.
Additionally, RPR provides ring–wide QoS assurance mechanisms and three different CoS.

1660SM 1660SM

Figure 133. RPR protection mechanism
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MPLS–based RPR technology.
To extend the packet protection (and end–to–end QoS...) to a multiring network, it is necessary to put
MPLS as the “upper layer” on top of RPR. MPLS provides the technology to handle traffic in multiring
networks thus ensuring end–to–end resilience and QoS for carrier–class Ethernet services across such

a network.

In Figure 134. each ring is responsible of providing RPR protection while the MPLS upper layer working
on top of RPR guarantees end–to–end resilience and networking. This is achieved by using two
techniques:
– Martini MPLS encapsulation
– Dual attach protection (described in the following paragraph [2])

The Martini MPLS encapsulation is used to provide an end–to–end reliable support to Ethernet
networking. It specifies a technique by which Layer 2 Protocol Data Units (PDUs) such as Ethernet may
be tunneled through an MPLS enabled network. End–to–end Ethernet connectivity relations are
transported over specific MPLS Label Switched Paths (LSPs) that are switched through the network. This
allows for the provisioning of multiple, segregated customer networks over the Service Provider
infrastructure, creating a Virtual Private Network (VPN) for each customer.

1660SM 1660SM

Figure 134. Packet protection (and QoS assurance) in multiring network : MPLS over RPR

[2] Dual Attach protection

Refer to Figure 134. and Figure 23. on page 73.

The Dual Attach protection is a redundant connection to another ring or hub providing aggregate
protection.
It offers a mechanism that expands the protection capabilities of RPR to multi–ring architectures enabling
network–wide resilience.
Two RPR rings are interconnected in two points (nodes) so that networking is resilient to both node and
link failures. In addition, dual attach allows for multiple node or link failures across multiple RPR structures.
Considering Figure 134. , if either Node A fails or the link between Node A and the other ring fails, Node
B can forward packets to the other ring through its attachment keeping QoS and SLA levels unaltered.
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[3] Customer Edge (CE) Dual Homing protection

The CE dual homing consists in a CE connection to two nodes in a ring for protection of the access
interfaces.

This protection is described in the following Figure 135. and in Figure 23. on page 73

1660SM
1660SM

1660SM
1660SM 1660SM

1660SM

1660SM

Figure 135. Customer Edge Dual Homing
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3.7.2.4 Alcatel ISA Card Interworking
ISA–PR supports interworking with other OMSN’s portfolio’s ISA card types as for the following
Figure 136.

Core Core MPLS
Router Switch/Router

FX, FE
FX, FE GbE
GbE
Beo
atw
yr
Nks Beos
a tr
yw
Nk

ISA PR ISA PR

EMX3660 Overlay 1660SM
Packet Ring SDH
VC–4–Xv
Beos
a tr
yw
Nk
Ring Beo
a t rs
yw
Nk

Beos
a tr
yw
Nk Beo
a t rs
yw
Nk

ISA PR
ISA PR

CO ISA PR ISA PR

GbE GbE
GbE FE
ISA
ISA PR_EAw
ISA PR_EA
Bo
aw
yr
N
ek
ts Bo
ar
yk
Nes
t

PR_EA Br
aw
yo
Ns
ek
t
1650

STM–n
1650
Ring
1640 FE/GbE
16x0 Bo
aw
yr
N
ek
ts Bo
aw
yr
Nek
ts
Bo
aw
yrs
Nek
t Bo
aw
yr
N
ek
ts Bo
aw
yr
Ns
ek
t Bo
aw
yr
N
ek
ts

1640 ISA GbE
ISA GbE Br
aw
yo
Ns
ek
t ISA Eth
ISA Eth ISA Eth ISA Eth

FE FE FE GbE ISA Eth FE GbE

CE
FE

Figure 136. Relationship with other ISA Cards

Inter–working with the following ISA cards is supported:

– ISA Eth
– ISA GbE
– ISA PR_EA

The ISA–PR is designed to be deployed in conjunction with ISA Eth, ISA GbE and ISA PR_EA cards
deployed in OMSN node types. Customer deployment will often involve the use of some or all of these
ISA card types in an ”overlay” network, which may consist of point–to–point links, aggregation functions
and Packet Rings.

The ISA–PR_EA card is used to aggregate different ETH traffic flow, while guaranteeing per flow QoS,
coming from ISA–Eth or ISA–Gbe into GBE interface that can be connected to the ISA–PR.
Customer segregation and traffic management is provided by MPLS traffic segregation on the link
between the two ISA–PR and ISA–PR_EA cards.

The ISA PR_EA cards attaching to the ISA PR may utilize Dual Attach for protection.
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3.8 ISA – ETHERNET management sub–system

3.8.1 LAN to LAN transport service

OMSNs can be equipped with Ethernet units to allow LAN to LAN service as a point to point connection
between two routers or switches through a SDH network, as depicted Figure 147. on page 277. The board
acts as a gateway towards the SDH network.

In order to guarantee the end to end transparency each Ethernet stream/interface of the board is mapped
in a specific SDH VC (by means of “GFP” encapsulation algorithms, according to ITU–T G.7041 Rec.)
performing a one to one Ethernet traffic mapping into the SDH network.

A transport network based on OMSNs equipment provides flexible link service among remote LANs
carrying Ethernet traffic, as shown on Figure 137.

OMSN STM–N OMSN

STM–N STM–N

STM–N
OMSN OMSN
Ethernet Ethernet
LAN A over OMSN STM–N over LAN B
SDH SDH

STM–N STM–N STM–N
STM–N

OMSN OMSN
STM–N

Figure 137. Example of an Ethernet stream transport through a SDH network

– Transparency
The Ethernet frames are forwarded to the output port with no protocol termination. This cause no
impact on service management architecture due to transport network insertion
– Low latency
The transport network provides a very low end–to–end delay; the removal of storeforward need in
the intermediate nodes using continuous data flow is another consequence of transparency
– High availability
The LAN–to–LAN service makes use of the same resources and infrastructures of the other
transported services (ATM, MPLS, PDH and SDH streams...); so availability is very high
– High quality
All the features of the transport network, like very low BER, synchronization, alarms management,
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3.8.2 LAN to LAN functional description

The functional block diagram of a LAN to LAN service is shown in Figure 138.
The client sink termination function adapts the client interface; all the payload frames received are stored

into input buffer queue.

The source SDH adaptation function draws the frames from the memory emptying the cluster and making
it available again; then maps the frame into SDH Virtual Container applying the GFP encapsulation
procedure.
SDH paths are considered as traffic pipes carrying a continuous data flow.
At the output port the dual operation is performed: the output buffer queue is written with payload frames
received from SDH line and then the client source termination draws from memory and forwards these
frames to the client according to the interface characteristics.
Input buffer size = 80 frames
Output buffer size = 80 frames, without concatenation
528 frames, VC–3 concatenation (N x VC–3)
2064 frames, VC–12 concatenation (N x VC–12)

Port A Port B

Client SDH SDH pipe – A to B SDH Client
sink source sink source

input output
Client buffer Bidir. SDH pipe buffer Client
A (N x path) B

Client SDH SDH pipe – B to A SDH Client
source sink source sink

output input
buffer buffer

Figure 138. LAN to LAN service block diagram

Three types of Ethernet interfaces are provided
– 10 Mbit/s – Ethernet
– 100 Mbit/s – Fast Ethernet
– 1000 Mbit/s – Giga Ethernet
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Different Ethernet interfaces types can be used at the termination ends: e.g. an Ethernet client interface
in one side and a Fast Ethernet one in the other side.

A SDH pipe can be configured as

– a single SDH path or

– a concatenation of paths:
• N x VC–12
• N x VC–3
• N x VC–4

Depending on client types and SDH pipe a bandwith limit can occur.

A flow control mechanism is used to adapt the client rate to the transport pipe.

3.8.3 Main features description

3.8.3.1 Encapsulation

All the types of client
– Ethernet
– Fast Ethernet
– GigaBit Ethernet
are mapped into SDH Virtual Containers using encapsulation algorithms for variable lenght packets,
according to ITU–T G.7041 Recommendation “Generic framing procedure (GFP)”.
GFP has been adopted to solve the incompatibility between the Ethernet traffic, based on discontinuous
data, and the SDH traffic needing a continuous data stream.
GFP is able to map lenght–variable data.
The Ethernet frames are GFP encapsulated, to be then mapped into SDH Virtual Containers.
In this application the client signals are Ethernet MAC (PDU oriented) type. The GFP encapsulation is
shown on Figure 140. on page 268.
For each pipe three different GFP frame formats can be configured, as shown on Figure 139. on page 266:
– GFP without FCS
– GFP with FCS
– Extended GFP.
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PLI PLI PLI
PLI Core PLI PLI Core
Header Header
cHEC cHEC cHEC
cHEC cHEC cHEC
PTI+PFI+EXI PTI+PFI+EXI TYPE
UPI Payload UPI Path Status
tHEC Header tHEC Circuit Status
tHEC tHEC Circuit Status Payload
Header
Ethernet data Ethernet data Link Status
Ethernet data Ethernet data Link Status
Ethernet data Ethernet data pcHEC
Client
Payload pcHEC
Field
Ethernet data
Ethernet data
Ethernet data
Client
Ethernet data Ethernet data
Payload
pFCS Field
FCS pFCS
Field
pFCS
pFCS Ethernet data

GFP without FCS GFP with FCS Extended GFP
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Figure 139. GFP frame format

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According to the type, the GFP frame format consists of a Core Header, a Payload Header, a Client
Payload field and FCS field.

The Core Header, made up of 4 octets, supports frame delineation procedures and essential data link

operations functions independent of the higher layer PDUs (Protocol Data Unit).

The GFP Core Header consists of the following fields
– PLI: it is the PDU Length Indicator field 16 bits length, containing a binary number representing the
number of octets in the GFP Payload Area. Zero length means no payload area, i.e. idle frame; this
is intended for use as a filler frame for the adaptation process
– cHEC: it is the Core Header Error Control field 16 bits lenght, containing a CRC–16 generated
sequence that protects the integrity of the contents of the Core Header by enabling both single–bit
error correction and multi–bit error detection.

The Payload Header, is a variable–length area, made up of
– 4 octets in GFP without FCS and GFP with FCS frame format
– 8 octects in Extended GFP frame format,
provides payload information like GFP type; when Extended GFP is used this area provides also
information used in Packet Concatenation.
According to the frame format, in the following are described the various types of fields:

– GFP without FCS and GFP with FCS frame format
• the first two octects constitute the GFP type field of the Payload Header, indicating the content
and format of the GFP Payload field. The Type field distinguishes between services in a
multi–service environment. This field consists of
– PTI, Payload Type Identifier, a 3–bit field
• PTI=0 for GFP user frame conveying client data
• PTI=1 for GFP user frame conveying far–end Client Signal Fail indications
– PFI, Payload FCS Indicator, 1–bit field
• PFI=0, Payload FCS is present
• PFI=1, Payload FCS is absent
– EXI, Extension Header Identifier, 4–bit field
– UPI, Used Payload Identifier, 8–bit field
• tHEC: the 3rd and 4th octets constitute the Type Header Error Control field containing a CRC–16
generated sequence that protects the integrity of the contents of the Type Field by bit error
detection.

– Extended GFP
• the first octect is made up of the TYPE fields that provides format and frame type
• from 2nd to 6th octet the information about Path Status, Circuit Status and Link Status are given
• in the last two octets, the FCS type information are given, in pcFCS fields.

The Payload Field contains the Ethernet frames; this variable–length area may include from 64 to 1574
bytes. The client user/control PDU is always transferred into the GFP Payload field as an octet–aligned
packet stream.

The payload Frame Check Sequence (pFCS) is an optional field, 4–bytes long. If selected, it’s a frame
check sequence containing a CRC–32 sequence used to detect any packet corruption inside the transport
network.
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Ethernet MAC frame GFP frame
Octets Octets

7 Preamble 4 Core Header

1 Start of frame delimiter 4
8 Payload Header
6 Destination Address (DA)
6 Source Address (SA)
Client
2 Lenght/Type
Payload
MAC client data Field
Pad
Frame check
4 sequence (FCS)
Bit # 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Ethernet MAC Frame fields:

– Preamble: the preamble is a 7–octet field that is used to allow the PLS (Physical Signaling) circuitry to
reach its steady–state synchronization with the received frame’s timing.

– Start of Frame Delimiter: the SFD field is the sequence 10101011. It immediately follows the preamble
pattern and indicates the start of a frame.

– Destination Address (DA): the Destination Address field specifies the station(s) for which the frame is
intended.

– Source Address (SA): the Source Address field specifies the station sending the frame.

– Length/Type: this two–octet field takes one of two meanings, depending on its numeric value:
– If the value of this field is less than or equal to the value of max Valid Frame, then
the Length/Type field indicates the number of MAC client data octets contained in
the subsequent data field of the frame (Length interpretation).
– If the value of this field is greater than or equal to 1536 decimal (equal to 0600 hexa-
decimal), then the Length/Type field indicates the nature of the MAC client protocol
(Type interpretation).
The Length and Type interpretations of this field are mutually exclusive.

– MAC client data and PAD: The data field contains a sequence of n octets; full data transparency is pro-
vided. If the length of the data field is less than the minimum required for proper operation of the protocol,
a PAD field (a sequence of octets) will be added at the end of the data field but prior to the FCS field.

– Frame check sequence (FCS): a cyclic redundancy check (CRC) is used by the trnsmit and receive algo-
rithms tp generate a CRC value for the FCS field. The frame check sequence (FCS) field contains a
4–octet (32–bit) cyclic redundancy check (CRC) value. This value is computed as a function of the con-
tents of the source address, destination address, lenght, LLC data and Pad (that are all the fields except
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the preamble, SFD, FCS and extension).

Figure 140. GFP encapsulation of the MAC frames

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3.8.3.2 Flow control

To avoid buffer saturation probems at the termination end, flow management is very important. When an
excessive traffic is received, a control mechanism can be used to slow down the transmitter avoiding a

packets loss.

Three different control options are used:
– input control
– output control
– external control.

In the following the relative actions are described.

As you can see from Figure 141. on page 269, the input control is performed at the input port; it is always
enabled regardless the GFP type. When the input buffer of Port A crosses a fixed threshold of 48 frames,
a pause request is sent back to the transmitter; no input frame is thrown away till 80 frames filling
occurence. The pause request message is defined in IEEE 802.3x; the transmitter is asked to be paused
for 32 quanta.
The transmitter will be re–qualified (pause request stopped) when the input buffer of Port A crosses the
44 frames threshold.

Client Port A Port B Client
A B

Client SDH 3 x VC–12 SDH Client

output
input buffer
100 buffer Bidir. SDH pipe 100
Mbps (N x path) Mbps
pause request

+
control+ output
buffer input
data flow buffer

Figure 141. Flow control mechanism: input control
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As you can see from Figure 142. on page 270, the output control is performed at the output port only when
Extended GFP is used. When the output buffer of Port B crosses a fixed threshold of
– 272 frames, when VC–3 concatenation is used (N x VC–3)
– 1040 frames, when VC–12 concatenation is used (N x VC–12)

a flow control action is performed to reduce the traffic received from the SDH network: a pause request

is sent back to the SDH source of Port B and then, by means of the SDH pipe, to the SDH source of Port
A. This fact could cause the queue filling of the input buffer of the Port A: in this case the input control
previously described is applied.
The transmitter will be re–qualified (pause request stopped) when the input buffer of Port B crosses the
– 240 frames threshold, when VC–3 concatenation is used (N x VC–3)
– 1008 frames threshold, when VC–12 concatenation is used (N x VC–12)

If the received client throughput is higher than SDH pipe capacity, idle frames are sent to fill the SDH virtual
container.

Client Port A Port B Client
A B

pause request

input output
100 buffer Bidir. SDH pipe buffer 10
Mbps (N x path) control+ Mbps

pause request
data flow

+

output
buffer input
buffer

Figure 142. Flow control mechanism: output control

See Figure 143. on page 271. The external control is performed at the output port. When a pause activity
is requested from the external client, the output transmitter is stopped for the relative period.
The external control is planned for future releases.

This fact could cause first the queue filling of the output buffer of Port B activating the output control
previously described, and then the queue filling of the input buffer of Port A activating the input control.
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Client
A Port A Port B Client B
Client SDH 1 x VC–3 SDH Client Client Client

sink source sink source sink source

pause request
100 input Bidir. SDH pipe output 10/100 output
buffer buffer buffer
Mbps (N x path) Mbps

pause request
Client SDH 1 x VC–3 SDH Client Client Client
source sink source sink source sink
+
output input control+ input
buffer buffer buffer
data flow

Figure 143. Flow control mechanism: External control

3.8.3.3 Concatenation

Two different VC–n concatenation mechanisms are employed in OMSN Lan to Lan transport service:

– Virtual Concatenation for VC–4 concatenation in Gigabit Ethernet clients

– Packet Concatenation for VC–12 and VC–3 concatenation in Ethernet/Fast Ethernet clients

In both cases differential delay of the network is compensated at path Termination Sink.

When Virtual Concatenation is used each Ethernet frame is sent by dispatching one byte per VC in rotation
mode. Thus the message to be transmitted by means of the SDH network is splitted byte per byte among
the paths making up the Pipe.

The Virtual Concatenation Termination feature is according to ITU–T G.707 and G.783 Recs.
Transmission Network

33 2 11
VC–4
Client A Client B

33 2 21

VC–4
Message Message Message Message Message Message
3 2 1 3 2 1

33 2 21
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VC–4
Figure 144. Messages dispatching via Virtual Concatenation

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When the Packet Concatenation is used, each Ethernet frame is not shared among different paths (VCs)
of a certain pipe as in Virtual Concatenation mode; but each message is dispatched on a single path/VC
of a certain pipe.
When a failure occurs inside the network, unavailable paths are not used and traffic is kept by using the

remaining available paths.

The bandwidth can be increased/decreased with no impact on traffic (hitless link adjustment).
Obviously the messages can be sent through different ways and have to be realigned in reception to
restore the proper sequence.

Transmission Network

Message
1
VC–12 or VC–3
Client A Client B

Message
2
VC–12 or VC–3
Message Message Message Message Message Message
3 2 1 3 2 1

Message
3
VC–12 or VC–3

Figure 145. Messages dispatching via Packet Concatenation
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3.8.4 Technical specification

Latency data

[1] GigaBit Ethernet board latency

• 1 x VC–4

– 64 bytes = 205 µs

– 512 bytes = 201 µs

– 1518 bytes = 193 µs

[2] Fast Ethernet board latency

• 1 x VC–4

– 64 bytes = 101 µs

– 512 bytes = 125 µs

– 1518 bytes = 178 µs

• 1 x VC–3

– 64 bytes = 72 µs

– 512 bytes = 147 µs

– 1518 bytes = 317 µs

• 1 x VC–12

– 64 bytes = 517 µs

– 512 bytes = 2108 µs

– 1518 bytes = 5841 µs

• 2 x VC–3

– 64 bytes = 277 µs

– 512 bytes = 1462 µs

– 1518 bytes = 3997 µs

• 8 x VC–12

– 64 bytes = 657 µs

– 512 bytes = 3452 µs

– 1518 bytes = 5824 µs
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Herebelow is given an example of the end to end delay; it is the sum of the following values:
– physical line delay = 5 µs/Km
– delay for each OMSN pass through = 5
10 µs/NE
– latency.

In a 1000 Km long network (5us/Km) and made up of 100 OMSNs equipment (5
10 µs/NE) using a Fast
Ethernet board 8 x VC–12 / 512 bytes mapped, the end to end delay is equal to:

(1000 Km x 5 µs) + (100 x 10 µs) + 3452 µs = 9452 µs

Allowed differential delay in case of concatenation

VC–12 concatenation = 35 ms


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3.8.5 Ethernet boards

Two types of ETHERNET boards are foreseen for 1660SM :

– 10/100 Mb/s Ethernet unit (refer to paragraph 3.8.5.1 on page 275)

– Gbit Ethernet (rate adaptive) unit (refer to paragraph 3.8.5.2 on page 279)

3.8.5.1 10/100 Mbit/s Ethernet unit

1660SM can also be equipped with 10/100 Mb/s Ethernet unit to allow LAN to LAN connections
as a point to point connection between two routers or switches through an SDH network, as
depicted Figure 147. on page 277. The board acts as a gateway towards the SDH network.

The 10 or 100 Mb/s Ethernet traffic flows are mapped into VC12, VC3, or VC4 SDH transport
structures, more precisely each Ethernet traffic interface of the board is mapped in a specific
VCn (n=12, 3, 4), one to one Ethernet traffic mapping in the SDH network is performed, in order
to guarantee the transparency end to end.
In fact the Ethernet traffic is transported transparently in the SDH Network and it is terminated
in the ADMs nodes where Ethernet traffic is dropped towards switches or routers without
terminating the Ethernet frames.
Mapping Ethernet flow inside VC–12/3/4 implies a compression of the total available bandwidth
of the physical ethernet protocol. The IEEE802.3 is the standard algorithm used to adapt each
customer flow inside an independent VC.

Main functional aspects:

Ethernet frames are mapped over a SDH VC using Generic Framing Procedure (GFP)
encapsulation (see Figure 140. on page 268, and Recc. ITU–T G. 7041 for details).

All the Ethernet access connectors are on the front panel of the unit. The architecture of the
board is represented in Figure 146. on page 276. It is constituted by two cards, an access card
that provides 14 Ethernet interfaces 10BaseT or 100BaseT, and a main board that provides 11
Ethernet interfaces 10BaseT or 100BaseT (the physical connector is always the same). The
Ethernet traffic, opportunely mapped in the SDH transport structures, is then sent toward the
SDH matrix through the back–Plane which has 4 STM–1 equivalent throughput.
– The board allows the mapping provisioning between the Ethernet (10 Mbit) or Fast
Ethernet (100 Mbit) interfaces and the SDH VC as follows:

• Ethernet interface to a single:

– VC–12 or
– VC–3;

• Fast Ethernet interfaces to a single:

– VC–12 or
– VC–3
– VC–4

The back–Panel can support a maximum throughput of 622 Mb/s divided in 4 STM–1
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flows. This constitutes a constraint respect to, for example, a configuration of the board
with 25 Fast Ethernet interfaces mapped into 25 VC–4 (not possible because overcome
the throughput).

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This is a typical problem of resource allocation where in one side there are up to 25 VC–n
transport structures on the other side there are 4 tubes of STM–1 capacity, and the
Operator has to find the mapping VCn–tube which best fits the available resources (622
Mbit/s).

Summarizing, the operator first provisions the board defining the interface types, second

he creates the VCx defining in the mapping between the interface and VC, since the
relationship between interface and VC is one to one. More complex is the association
between the VC–n and STM–1 back–Plane flow in order to best fit the resources.
– One Ethernet Interface is mapped in one SDH VC: no grooming of Ethernet frames in the
SDH network
– No Virtual Concatenation of Lower Order SDH VCs
– Protection occurs at SDH level

Figure 146. Board Ethernet 10/100: System architecture
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03
Ethernet frames
are mapped in SDH
VC–12. VC–3, VC–4 Site to Site Traffic is
mapped on a dedicated
SDH VC

SDH RING NETWORK

Figure 147. Example of Ethernet service application

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Legenda:

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SDH level
The LAN to LAN
Customer box:
protection board is present
either LAN Switch or Router
only at each
terminating node
1660SM
with LAN to LAN board

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Ethernet MAC Frame and GFP Frame fields:

– Preamble: the preamble is a 7–octet field that is used to allow the PLS (Physical Signaling) circuitry
to reach its steady–state synchronization with the received frame’s timing.

– Start of Frame Delimiter: the SFD field is the sequence 10101011. It immediately follows the
preamble pattern and indicates the start of a frame.

– Destination Address (DA): the Destination Address field specifies the station(s) for which the frame
is intended.

– Source Address (SA): the Source Address field specifies the station sending the frame.

– Length/Type: this two–octet field takes one of two meanings, depending on its numeric value:
– If the value of this field is less than or equal to the value of max Valid Frame, then
the Length/Type field indicates the number of MAC client data octets contained
in the subsequent data field of the frame (Length interpretation).
– If the value of this field is greater than or equal to 1536 decimal (equal to 0600
hexadecimal), then the Length/Type field indicates the nature of the MAC client
protocol (Type interpretation).
The Length and Type interpretations of this field are mutually exclusive.

– MAC client data and PAD: The data field contains a sequence of n octets; full data transparency is
provided. If the length of the data field is less than the minimum required for proper operation of the
protocol, a PAD field (a sequence of octets) will be added at the end of the data field but prior to the
FCS field.

– Frame check Sequence (FCS): a cyclic redundancy check (CRC) is used by the transmit and receive
algorithms to generate a CRC value for the FCS field. The frame check sequence (FCS) field contains
a 4–octet (32–bit) cyclic redundancy check (CRC) value. This value is computed as a function of the
contents of the source address, destination address, length, LLC data and pad (that is, all fields
except the preamble, SFD, FCS, and extension).

– PLI: the two–octet PLI field contains a binary number representing the number of octets in the GFP
Payload Area.

– cHEC: the two–octet Core Header Error Control field contains a CRC–16 generated sequence that
protects the integrity of the contents of the Core Header by enabling both single–bit error correction
and multi–bit error detection.

– Type: the GFP Type field is a mandatory 2–octet field of the Payload Header that indicates the
content and format of the GFP Payload field

– tHEC: The two–octet Type Header Error Control field contains a CRC–16 generated sequence that
protects the integrity of the contents of the Type Field by enabling both single–bit error correction and
multi–bit error detection.

– GFP Extension Header: a 0–to–60 octets extended field that supports technology specific data link
headers such as virtual link identifiers, source/destination addresses, port numbers, Class of
Service, extended header error control, etc.

– GFP Payload: The GFP Payload Area consists of all octets in the GFP frame after the GFP Core
Header. This variable length area may include from 4 to 65 535 octets.
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3.8.5.2 Gbit Ethernet (rate adaptive) unit

The task of the Gigabit Ethernet functionality inside 1660SM is to carry Gigabit Ethernet packets over SDH
Virtual Containers. It can be achieved in two different ways using :

[1] “Gigabit Access card” + “10/100 Mbit Ethernet board”: only two Gigabit interfaces are supported.

[2] “Gigabit Ethernet rate adaptive board”: up to 4 Gigabit interfaces are supported.

[1] “Gigabit Access card” + “10/100 Mbit Ethernet board”

This functionality is achieved using the 10/100 Mbit/s Ethernet board (Fast Ethernet) in conjunction with
the Gigabit Ethernet Access Card as depicted in Figure 148.

The function performed by the Access card is the interfacing on one side with the 1 Gigabit line and on
the other side with the 10/100 Mbit/s Ethernet board ( where the signal is processed) through two 1.2 Gbit/s
serial busses.
Only two of the four interfaces ( pluggable module alternatively 1000 BASE–LX , 1000 BASE–SX, 1000
BASE–ZX) on the Gigabit Access card can be used .
Gigabit interface are mapped through Generic Frame Protocol in one VC–4. with a compression ratio of
1:7; 802.3 Ethernet Flow Control is supported.
The Ethernet traffic mapped in the SDH transport structures, is then sent toward the SDH matrix through
the back–Plane which has 4 STM–1 equivalent throughput.
In the configuration depicted in Figure 148. the 10/100 Mbit Ethernet interfaces present on the
ETHERNET board can also be used taking into account the limit of the backplane.

Gigabit Eth 1

Gigabit Eth Gigabit
not used Access Card
not used 4

2 x 1.2 Gibit/s busses (through backplane)

10/100 Mbit Eth 1

10/100
ETHERNET
SDH SDH
Matrix Port
BOARD
10/100 Mbit Eth
10/100 Mbit Eth 11

Backplane : 622 Mbit/s
throughput
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Figure 148. Gigabit Ethernet System architecture: Gigabit access with Fast Ethernet board

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[2] “Gigabit Ethernet rate adaptive board”

The board, named Gb Ethernet with GFP mapping (mnemonic label GETH–MB), supports up to four Gb
Ethernet interfaces in the main boards depicted in the following Figure 149.

Ethernet Modules:
1000 Base LX
1000 Base SX
1000 Base ZX Gbit ETH
Main board

1660SM (Slot not Enhanced)

Figure 149. Gigabit Ethernet System architecture:Gigabit Ethernet main board

The Gb Ethernet interfaces (pluggable module) plugged in main board, are named Small Formfactor
Pluggable (SFP) Transceivers and they can be considered as independent items hardware, in fact they
have an own Remote Inventory. At the moment three types of Small Formfactor Pluggable Transceivers
are provided:

1. Gb Ethernet Long Haul optical interface 1000BASE–LX

2. Gb Ethernet Short Haul optical interface 1000BASE–SX

3. Gb Ethernetl optical interface 1000BASE–ZX

Each Gb Ethernet interface can be mapped through the Generic Frame Protocol (GFP) into 1, 2, 3, 4, 5,
6 or 7 VC4s. The mapping determines the rate of compression of the data throughput that can be
respectively from 1:7 to 1:1. As for the Fast Ethernet this compression is allowed thanks to the flow control
algorithm and considering the Ethernet traffic profile is typically bursty and the mean throughput is less
than the peak rate.

If the board is into an enhanced slot of 1660SM the back panel throughput is of 1.2 Gb/s instead of
622Mb/s, this determines that the maximum number of VC–4 mappable to the Gb/s Ethernet Interfaces
is 8 instead of 4. This, for example, allows the transparent (without compression) transport of a Gb
Ethernet interface into the SDH network.

In order to provide for the Gb Ethernet a rate compression less than 1/7, more than one VC4 can be used
to transport the Ethernet traffic, until a maximum of 7 VC4 where the transparent transport is obtained,
in fact 7 times 150Mb/s (VC4 payload rate) is 1050Mb/s. Note, if no compression is configured (i.e.
mapping on 7 VC4s), also another Gb/s interface can be mapped on a single VC4 (maximum compression
level), in order to use all the backpanel bandwidth (8 VC–4 equivalent).

The possibility of configuring more VC–4s, referring to the same client, is obtained by High Order virtual
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concatenation, where the level, the number of VC4s virtual concatenated, is provisioned by the operator.

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3.9 ISA – ES (Ethernet Switch)

3.9.1 General

Today’s evolving telecommunications services environment is highly competitive. There is a growing
demand from Enterprise customers for simple, wide–area Broadband Data services which meet their
needs for plentiful, competitively priced and flexible connectivity. Historically the success of Ethernet as
the predominate technology within the Enterprise infrastructure, has been driven by very low capital and
operational costs, the high degree of flexibility offered by the technology and importantly its easy of use
– the plug and play model. Thus enterprises are now looking for data services outside of the building (in
the WAN), which match the Ethernet technology used internally for LAN based services, without the need
for expensive conversion equipment. These new services offered by the public network in the Wide Area
are referred to a Metro Ethernet services.

Similarly network operators and service providers are looking to new services like Metro Ethernet in order
to develop new high–value revenue streams. An example of which is enhancing basic Ethernet
connectivity this through the use of value added capabilities such as Layer 2 VPNs and multiple Qualities
of Service (QoS) per connection. Deployment of Ethernet as a simplistic point–to–point technology will
only result in canalization of existing Leased Line, Frame Relay and ATM based services. Only through
the provision of Value–Added Services (VAS) of basic Ethernet connectivity to provide differentiation will
Metro Ethernet services deliver incremental revenues and ultimately profitability.

The ISA–ES series modules can deliver a full set of Ethernet services that are described in the next points
[1] to [4].

[1] Ethernet Private Line

EPLine service connects two ports of a client between each other in a transparent fashion (using
transparent mode).

Traffic originating from one Customer Port is forwarded to the other one without any filtering and
maximum level of security possible (physical segregation through different SDH infrastructure). The
service emulates an Ethernet ”wire” which actual bandwidth is determined by the SLA and by network
load. EPLine does not require MAC learning or MAC–based forwarding.

Figure 150. Ethernet Private Line service
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[2] Ethernet Virtual Private Line

EVP–Line service connects two ports of a client between each other (using bridging mode).

Traffic originating from one Customer Port is classified and forwarded accordingly to the other end.

The service emulates an Ethernet ”wire” which actual bandwidth is determined by the SLA and by
network load. Thanks to the available Eth Multiplexing Function provided by the ISA–ES series
modules, different Virtual Private Line services can be defined on the same UNI belonging to different
applications and with different QoS SLA.

EVPLine adopts MAC learning and MAC–based forwarding according to the need.

Figure 151. Ethernet Virtual Private Line service

[3] Ethernet Virtual LAN

EVP–LAN service connects two or more ports of a client between each other (using bridging mode).

Traffic originating from one Customer Port is classified and forwarded accordingly to the other end.
The service emulates an Ethernet LAN which actual bandwidth is determined by the SLA and by
network load. EVP–LAN adopts MAC learning and MAC–based forwarding with aging timeout.
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Figure 152. Ethernet Virtual LAN

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[4] Broadband access

In this service, a number of customers are connected to a common Aggregate Port (e.g. typically
connected to an ISP point of presence) Traffic is only delivered from individual Customer Ports to the

Aggregate Port.

Broadband Access can distinguish between various customers’ traffic at the Aggregate Port using
VLAN tags.

For each customer that is attached to the BA service it is possible to define a specific QoS SLA.

Figure 153. Broadband Access service
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3.9.2 ISA–ES series modules

ISA–ES series modules provide ETH 10/100/1000 interfaces connectivity for LAN based clients premises
inside the metro area.

Beyond mapping ETH flows onto the SDH metro network by means of standard mechanisms (as specified
in ITU G.7071, ITU G.7042 and ITU G.707) the ISA–ES series cards introduce wire speed classifying,
policing and scheduling capability empowered by carrier class Ethernet switching engine.

Per customer traffic flow management with low bandwidth granularity, segregation and QoS are just few
of the value added arguments that these series of modules offer to the carrier operators at a competitive
price.

ISA–ES series is composed by:

– ISA–ES1 module



The ISA–ES series modules are modules that can be plugged according to the bandwidth and interface
count demand inside the OMSN product family.

Some of the resources available in the SDH infrastructure can be utilized in order to realize a converged
multi service network into which different streams (e.g. TDM, ETH, ATM) can travel together in fat big pipes
reducing capital and operational expenses for the operator.

The major benefits that can be experienced utilizing an ISA–ES card in the SDH networks are:

– Interfaces cost reduction

– Bandwidth policing according to clients needs and operator’s policy

The interface cost reduction is achieved thanks to the native ETH interfaces provided from the equipment
that allow a cost effective replacement of useless and expensive up–link ports an external devices to
connect to the public network (e.g. POS (Packet Over SDH/SONET) or FR uplinks).
This leads to an infrastructure’s optimization for the operator and an induced cost reduction for the
end–user devices.
Furthermore bandwidth can be allocated and consequently controlled by the operator (through CIR, PIR
and burstiness specification) to the end users in accordance with the real need, independently from the
(physical) interface type used case by case.
Operators are, as such, enabled to offer more services with enhanced flexibility and granularity, optimizing
the bandwidth through the SDH network and opening new value added services from a common set of
equipments being the technology TDM, ATM or ETH.

As for the other ISA modules the ISA–ES series modules are connected to the main SDH matrix via
specific back–panel wires.

The capacity available from the card to the back panel gives the overall card trunking capacity that is
available for traffic to flow from and to the SDH resources (e.g. SDH ports that carry ETH traffic into SDH
VC).
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The number to the right of the ISA–ES series card gives that amount in VC–4 equivalents.
Hereafter are reported the available trunking capacity for each of the ISA_ES series cards:



– SA–ES16 has up to 16 VC–4 of bandwidth available

Each of the ISA–ES series modules has specific ETH access ports and SDH trunks.

– ETH access ports may reside on the card itself of may be provided through other access cards.

– SDH trunks are connections (SDH VCs) through the back panel to the SDH matrix and to SDH ports
(STM–n).

ETH access ports on the ES series modules are:

– ISA–ES1 8FE has 8 Ethernet ports (10/100 Base T) on the front of the card

– ISA–ES1 8FX has 8 Ethernet ports (100 Base FX) on the front of the card

– ISA–ES4 8FE+1GE has 8 Ethernet ports (10/100 Base T) and 1 GB Ethernet port (1000 Base
SX/LX/ZX SFP) on the front of the card

– ISA–ES16 is a port less card that can use specific access modules:

• 14 x FE access module: 14 x Fast Ethernet ports (10/100 Base T)

• 4 x GE access module: 4 x GB Ethernet ports with SFP plugs (Optical SX, LX, ZX)

Different ISA–ES series modules can be equipped in the same equipment. In this case it is also possible
to realize back–to–back trunking between them via specific cross connections inside the SDH matrix
(without the need of cabling).
Traffic can flow between two or more cards and the amount of it can be specified according to the need
(refer to Figure 154. on page 285).

ISA–ES1

ISA–ES16

Access card

SDH
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Figure 154. ISA–ES access port

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Figure 155. provides an high level overview of the traffic flow and processing in the ISA–ES series
modules.

The pipeline is composed of five main processing steps that are described in the next paragraphs.

De–mapping Classifier Policer Forwarding Scheduler Mapping

Encap packet frame mapping
Header PIR Ports +
De– assembly reassembly
? =
= CIR Bridge
Frame/packet

Figure 155. Traffic flow and processing in ISA–ES series

[1] Mapping

ISA–ES series modules are a family of Ethernet switching modules that provides native ETH access to
an SDH infrastructure.

Beyond just providing the physical ETH connectivity this family of modules has a full carrier class set of
functionality for optimal and efficient handling of ETH traffic flows with QoS.

An ISA–ES module receives and sends ETH traffic through two kinds of ports (refer to Figure 156. ):

• ETH physical interfaces (10/100 Base T, 100 BASE FX or 1000 Base SX/LX/ZX)

• ETH over SDH (also referred as trunk ports)

These ports are connected to a carrier class Ethernet switching engine that processes each flow and takes
care of the frame forwarding.

Eth Eth
I/O Switch

ETH Back
ETH Over SDH Panel
ports ports N x VC

Figure 156. ISA–ES series ports
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The following standards apply to ETH physical ports:

• IEEE 802.3 10BASE–T Ethernet (twisted–pair copper)

•

IEEE 802.3u 100BASE–TX Fast Ethernet (twisted–pair copper)

• IEEE 802.1z (Gigabit Ethernet)

• ANSI/IEEE 802.3 Auto–negotiation

• IEEE 802.3x Flow Control

• Data transfer rate from client equipment is limited in accordance with the specified traffic
characteristics by the standard IEEE 802.3x flow control mechanism.

Flow control frames are used to prevent congestion of the network that may cause packet discarding at
the egress of the network; the flow control mechanism stops the client source until the bandwidth allocated
to the service is able to absorb the extra traffic.
The result is that no packets are lost even in case of congestion. Flow control can be disabled according
to the operator’s choice.

The following standards apply to the ETH over SDH ports:

• ITU–T G.7041 GFP (Generic Framing Procedure)

• ITU–T G.7042 LCAS (Link Connection Adjustment Scheme)

• G.707 (SDH VC Virtual Concatenation at Low and High Order VC–12, VC–3 and VC–4 nv)

The Ethernet mapping scheme on the trunk ports adheres to the Generic Framing Procedure (ITU–T G.
7041).

The Ethernet traffic, opportunely mapped in the SDH transport structures, is then sent by the trunk ports
toward the SDH matrix from the back–plane and than to the corresponding SDH port.

A trunk port is realized by a bundle of SDH VCs (VC–12, VC–3, VC–4) grouped together according to
ITU–T G.707 (Virtual Conc) and ITU–T G.7042 (LCAS).

The bandwidth of the trunk port in normal operational mode corresponds to the available bandwidth of the
grouped VCs (e.g. 5xVC–12 equals 10 Mbps).
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[2] Traffic classification

ISA–ES series module can classify ETH traffic according to a wide set of standard specified criteria in order
to provide a feature reach set of capability.

Each classified traffic is referred in the next paragraphs as a classified flow.

Classification criteria are the following:

• Port (Physical ETH or ETH over SDH)

• IEEE 802.1Q (VLAN tagging)

• IEEE 802.1p (ETH frame priority)

• IEEE 802.3 Source/Destination MAC address (also according to IEEE 802.1ad)

The ISA–ES16 module expands the classification criteria by means of also supporting:

• MPLS label (according to IETF Martini draft ETH over MPLS)

• IP–TOS/DSCP fields

[3] Policing and metering traffic with QoS

ISA–ES series modules allow service providers and carrier operators to specify per flow traffic QoS.

ETH flows quality of service is enforced at the ingress of the network and inside the network by traffic
conformance check made by the policing function.
Policing is performed by means of a token bucket algorithm (dual rate on the ISA–ES16).

Traffic QoS is specified by a set of parameters that control its max, mean rate and the relative burst window
size in bytes.

Policing parameters are specified per classified flow according to:

CIR = committer information rate
CBS = burst window size at the CIR
PIR = excess information rate
PBS = burst window size at the PIR

Burst window size (bytes)

PBS
Yellow
EBS

CBS
EIR
Green
Rate (bps)

CIR PIR
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Figure 157. ISA–ES series traffic parameters

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Through the specification of per flow traffic parameters the ISA–ES series modules can support the
following SLAs:

a) Guaranteed SLA

Typically serves High priority traffic for mission critical applications that require loss–less delivery and
minimal delay.

Guaranteed SLA denotes BW (CIR = PIR 0 in 100Kbps increments), which is always available
regardless of any congestion conditions. Traffic delivered using Guaranteed BW, is policed to the CIR
value with a burst window equal to the CBS.

Guaranteed traffic is always composed of green packets and gets the highest priority in the
processing chain.

b) Regulated SLA

Typically serves Medium priority traffic, which relies on transport layer protocol (per OSI stack) to
recover from occasional loss and requires moderate delay; e.g. client–server applications.

Regulated SLA denotes BW (PIR CIR 0 in 100Kbps increments), which may be overbooked per
network operator’s overbooking policy. The portion of bandwidth between CIR and PIR (aka EIR)
may therefore be partially available under congestion conditions. This SLA is available only from the
ISA–ES16 card.

Regulated traffic is composed of green and yellow (Excess of CIR) packets.

c) Best–Effort SLA

Typically serves Low priority traffic, which relies on transport layer protocol (per OSI stack) to recover
from loss and tolerates large delay; e.g. email and file transfer applications.

Best Effort denotes BW (PIR CIR = 0 in 100Kbps increments), which may or may not be available
per network operator’s reservation for Best Effort policy. It may therefore be unavailable under
congestion conditions.

Regulated traffic is composed of yellow packets.

[4] Congestion avoidance and Scheduling

Congestion avoidance techniques serve to anticipate and avoid network congestion conditions wile
maximizing network utilization and good–put of the traffic flows.

Congestion avoidance in ISA–ES series modules is based on a combination of Tail Dropping and WRED
(Random Early Detection); these techniques are designed to provide preferential treatment for premium
(CIR) class traffic under congestion situations while concurrently maximizing network throughput and
capacity utilization and minimizing packet loss and delay.

a) Tail drop

Tail drop treats all traffic equally and does not differentiate between classes of service. Queues fill
during periods of congestion. When the output queue is full and tail drop is in effect, packets are
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b) WRED

The packet drop probability is based on the minimum threshold, maximum threshold, and mark
probability denominator.

When the average queue depth is above the minimum threshold, RED starts dropping packets. The
rate of packet drop increases linearly as the average queue size increases until the average queue
size reaches the maximum threshold.

The mark probability denominator is the fraction of packets dropped when the average queue depth
is at the maximum threshold. For example, if the denominator is 512, one out of every 512 packets
is dropped when the average queue is at the maximum threshold. When the average queue size is
above the maximum threshold, all packets are dropped.

WRED is applied to yellow packets (Regulated (traffic beyond CIR) and Best Effort traffic quality).

1

Mark probability

0

Minimum Maximum
threshold threshold

Average queue size

Figure 158. WRED Congestion avoidance mechanisms

c) Scheduling

Scheduling of packets is performed on egress ports combining HOL (FIFO queue) and DRR (Deficit
Round Robin) queues.

HOL is used for Guaranteed traffic that gets highest priority.

DRR is applied to Regulated and Best Effort traffic
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[5] Switching and forwarding

ISA–ES series modules are based onto a carrier class Ethernet switching engine with auto learning
bridges according to IEEE 802.1ad.

This engine is either wire speed performing (all the functions are performed in hw) and highly flexible and
configurable.

On a per port basis it can be used in two modes:

Transparent mode: the engine forwards all the traffic incoming from one port to another without inspection
at the specified rate.

Bridging mode with Stacked VLAN capability: a group of configured ports (ETH phy or ETH over SDH) are
bridged together with MAC auto learning function according to IEEE 802.1ad.

Transparent Mode

Eth Back Panel
I/O N x VC–4
Bridge Mode

Figure 159. ISA–ES series operational modes

a) Multiple service per UNI port

ISA–ES series modules allow multiple services to be deployed from a single UNI Ethernet port.
Thanks to the Ethernet Multiplexing Function capability different traffics can coexist on the same port
and be differentiated between them by the classification process thus get the desired QoS per flow.

CUSTOMER
SITE B

CUSTOMER
SITE C
ETH UNI

EMF
CUSTOMER
SITE A
CUSTOMER
SITE D
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Figure 160. Ethernet Multiplexing Function

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b) Multiple customers per NNI port

The ISA–ES series modules allow a single NNI interface to be used for different customers while
guaranteeing high levels of segregation, security and per customer QoS ability.

ISA–ES series modules allow ETH frames to be tagged before being sent at the NNI interface. The
modules have full VLAN tag agility in the sense that VLAN tags can be pushed, swapped and popped
by the cards. The provider is able to add its own tags to the customer flows in order to segregate
different customers inside common network resources. This taggagility functionality allow service
providers to spread the capital expenditures among different customers and as a consequence to
offer highly competitive price levels for the offered services to their customers.

CUSTOMER A

CUSTOMER B ETH UNI
SVLAN 1
SVLAN 2
SVLAN 3

CUSTOMER C

Figure 161. Multiple customers on a single NNI

c) Customer traffic Isolation

All ISA–ES series modules ports and services provide customer traffic isolation, such that traffic
belonging to a given customer is isolated from traffic of any other customer using an identical or
different service.

d) Customer Address Space Isolation

All ISA–ES series modules ports and services provide isolation customer of customer specific
addresses, such that VLAN tags and MAC addresses belonging to a given customer are isolated
from VLAN tags and MAC addresses of any other customer using an identical or different service.

e) VLAN Uniqueness

VLAN at the access interfaces need not be unique. Same value can be used at different ports of the
same node or at different nodes. The guarantee of VLAN uniqueness within a port in the ISA PR EA
comes from the encapsulation of the Ethernet frames in MPLS LSP’s that segregate Ethernet traffic.
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3.10 4 x ANY HOST C subsystem

The unit is able to perform time division multiplex/demultiplex of client channels. The client streams are
mapped in 16 virtually concatenated VC–4s according to a proprietary–mapping algorithm. Provisioning

parameters and alarm collection are managed through two control interfaces.

The board has a highly modular fabric consisting of a housing card that can accommodate up to 4 modules,
one for each aggregated traffic.

The client data rates that the module can manage are reporte in Table 40. :

Table 40. Relationship between 4xANY optical modules and client type

Client type Bit rate Associated module

Type Wavelenght Acronym
Fast Ethernet @125 Mb/sec Low Speed
p 1310 nm OL–IN
850 nm OL–MM
FDDI @125 Mb/sec Low Speed
p 1310 nm OL–IN
850 nm OL–MM
ESCON @200 Mb/sec Low Speed
p 1310 nm OL–IN
850 nm OL–MM
Digital Video
g @270 Mb/sec Low Speed
p 1310 nm OL–IN
850 nm OL–MM
Fiber Channel @1.0625 Gb/sec High Speed
g p 1310 nm OH–IN
850 nm OH–MM
FICON @1.0625 Gb/sec High Speed
g p 1310 nm OH–IN
850 nm OH–MM
Gigabit Ethernet
g @1.25 Gb/sec High Speed
g p 1310 nm OH–IN
850 nm OH–MM

The 4xANYC modules configuration requires the operator to specify the client type to be transported on
each module.

The Table 41. below reports the number of VC–4 istantiated for managing a data stream of each client
type
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Table 41. 4xANY HOST C client type

Client type Number of istantiated VC4

Fiber Channel 8

FICON 8

Gigabit Ethernet 8

Digital Video 2

ESCON 2

Fast Ethernet 1

FDDI 1

The max throughput made available by the 4xANY HOSTC port is STM16 (2.5 Gb/s). The capability to
handle the whole throughput in terms of cross–connectivity depends on the equipment of the port in
“Enhanced H.S slots” rather than in “H.S. slots” of 1660SM shelf as explained on points [1] and [2].

Insertion of the board across hybrid slot (“Enhanced H.S slots” + “H.S. slots”) is not allowed.

[1] 4 x ANY inserted in enhanced slot (2526, 2829, 3435, 3738)

In ’Enhanced H.S.’ slot, the connection port –matrix can exploit two NGI links per type (i.e. 2 ’H’
/ 2 ’X’ / 2 ’L” links), each one operating at 622 Mb/s (equivalent 4xSTM1’s), with a total connection
bandwidth of 1.2 Gb/s per slot; then, the port equipped in two ’Enhanced’ slots, allows the user to
use up to 2.5 Gb/s throughput according to the client allocation grid showed in Figure 162.
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Modules Links towards
configured Client allocation inside 4xANY board
MATRIX
AU4 #0
AU4 #1 GE, NGI link #0

AU4 #2

ESCON, DV
AU4 #3 FE, FDDI FC,
AU4 #4
#1 #3
AU4 #5 FICON
NGI link #1
AU4 #6 FE, FDDI
ESCON, DV
AU4 #7
AU4 #8
ESCON, DV
#2 #4 AU4 #9 FE, FDDI GE,
NGI link #2
AU4 #10
AU4 #11 FC,
AU4 #12
AU4 #13 FE, FDDI FICON
ESCON, DV NGI link #3
AU4 #14
AU4 #15

Figure 162. 4xANY HOST–C: Client allocation grid in “enhanced” slot

Consequently, module configuration allowed are as reported in the following Figure 163.

FE, FDDI, FE, FDDI, GE, FC,
ESCON, DV ESCON, DV Not eq. FICON,
#1 #3 #1 #3
Not eq. Not eq. Not eq.

FE, FDDI, FE, FDDI, FE, FDDI, FE, FDDI,
#2 ESCON, DV #4 ESCON, DV #2 ESCON, DV #4 ESCON, DV

Not eq. Not eq. Not eq. Not eq.

#1 ESCON, DV #3 ESCON, DV #1 Not eq. #3 FICON,


GE, FC, GE, FC,
#2 Not eq. #4 FICON, #2 Not eq. #4 FICON,

Not eq. Not eq.

Figure 163. 4xANY HOST–C: module configuration in “enhanced” slot
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Same considerations of Figure 163. are showed in Table 42. :

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Table 42. Modules configuration in “Enhanced HS” slot
Module Module type Client configured Configuration Constraints
number by operator

#3 OH MM, OH IN
OH–MM, OH–IN Fiber Channel In conjunction with this clients on

FICON module#3, the module#1cannot be
,
Gigabit Ethernet used
OL MM, OL IN
OL–MM, OL–IN Digital Video
ESCON
Fast Ethernet
FDDI
#1 OH–MM, OH–I cannot be configured
in module#1
OL MM, OL IN
ESCON
Fast Ethernet
FDDI
#4 OH MM, OH IN
OH–MM, OH–IN Fiber Channel In conjunction with this clients on
FICON module#4, the module#2 cannot be
,
Gigabit Ethernet used
OL MM, OL IN
ESCON
Fast Ethernet
FDDI
in module#2
OL MM, OL IN
ESCON
Fast Ethernet
FDDI
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[2] 4 x ANY inserted in not enhanced slot (3031 and 3233)

In ’H.S.’ slot, the same connectivity is based on one NGI link per type (i.e. ’H’ / ’X’ / ’L’); with a total
connection bandwidth of 622 Mb/s per slot; then, the equipment of the port in two ’H.S.’ slots, allows

the user to use up to 1.2 Gb/s throughput. In Figure 164. , the client allocation, concerning Gb

Ethernet, Fiber Channel, FICON and the relationship with NGI links available for connecting Matrix
card, are showed.

Client allocation inside 4xANY board Links
AU–4 towards
optimization MATRIX
AU4 #0 AU4 #0 GE,
Modules AU4 #1 GE, AU4 #1 FC,
configured AU4 #2 NGI link #0
ESCON, AU4 #2 FICON
AU4 #3 FE, FDDI DV FC, AU4 #3
AU4 #4 AU4 #4 AU4’s
AU4 #5 FICON AU4 #5 not NGI link #1
#1 #3 not
AU4 #6 FE, FDDI ESCON, AU4 #6 available available
AU4 #7 DV AU4 #7
AU4 #8 ESCON, AU4 #8 GE,
#2 #4 AU4 #9 FE, FDDI DV GE, AU4 #9 FC,
NGI link #2
AU4 #10 AU4 #10 FICON
AU4 #11 FC, AU4 #11
AU4 #12 FE, FDDI ESCON, AU4 #12 AU4’s
AU4 #13 DV FICON AU4 #13 not NGI link #3
not
AU4 #14 AU4 #14 available available
AU4 #15 AU4 #15

Figure 164. Client allocation grid in “HS slots” with GE/FC/FICON

In Figure 165. , the ’optimized’ client allocation, concerning Fast Ethernet, FDDI, ESCON, Digital
Video, , and the relationship with NGI links available for connecting Matrix card, are showed.
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Client allocation inside 4xANY board Links
AU–4 towards
optimization MATRIX
FE,
AU4 #0

AU4 #0 FDDI ESCON

Modules AU4 #1 GE, AU4 #1 DV
configured AU4 #2 NGI link #0
ESCON, AU4 #2 ESCON

AU4 #3 FE, FDDI DV FC, AU4 #3 FE,
FDDI
DV

AU4 #4 AU4 #4 AU4’s
#1 #3 AU4 #5 FICON AU4 #5 not NGI link #1
not
AU4 #6 FE, FDDI ESCON, AU4 #6 available available
AU4 #7 DV AU4 #7
AU4 #8 ESCON, AU4 #8 ESCON
#2 #4 FE,
AU4 #9 FE, FDDI DV GE, AU4 #9 FDDI
DV
FE,
NGI link #2
AU4 #10 AU4 #10 FDDI ESCON
AU4 #11 FC, AU4 #11 DV

AU4 #12 FE, FDDI ESCON, AU4 #12 AU4’s
AU4 #13 DV FICON AU4 #13 not NGI link #3
not
AU4 #14 AU4 #14 available available
AU4 #15 AU4 #15

Figure 165. Client allocation grid in “HS slots” with FE/FDDI/ESCON/DV

Consequently, module configuration allowed are as reported in the following Figure 166.

ESCON, DV ESCON, DV Not eq. FICON,
#1 #3 #1 #3

FE, FDDI, FE, FDDI, Not eq. Not eq.
#2 ESCON, DV #4 ESCON, DV #2 #4
Not eq. Not eq.

Figure 166. module configuration in “HS” slots
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Same considerations of Figure 166. are showed in Table 43.

Table 43. Modules configuration in “HS” slot
Module Module type Client configured Configuration Constraints

number by operator

#3 OH MM, OH–I
OH–MM, OH I Fiber Channel In conjunction with this clients on
FICON module#3, all other 3 modules cannot
,
Gigabit Ethernet be used
OL–MM, OL–IN
OL MM, OL IN Digital Video
ESCON
Fast Ethernet
FDDI
in module#1
OL MM, OL IN
ESCON
Fast Ethernet
FDDI
#4 OH MM OH I cannot be configured
OH–MM, OH–I
in module#4
i d l #4
OL–MM, OL–IN
OL MM, OL IN Digital Video
ESCON
Fast Ethernet
FDDI
in module#2
OL MM, OL IN
ESCON
Fast Ethernet
FDDI
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3.11 Coarse WDM sub–system

The following items are considered:

– STM16 colored port (2 two slots wide) to be equipped in “Basic area” and supporting the 8 channels

’CWDM’ ITU–T grid;

– COADM 1ch unit (2 two slots wide) to be equipped in “Access area”, supporting the 8 channels
’CWDM” ITU–T grid;

– COADM 2ch unit (2 two slots wide) to be equipped in “Access area”, supporting the 8 channels

– MUX/DEMUX 8ch unit (2 two slots wide) to be equipped in “Access area”, supporting the 8 channels

– Double channel ’multirate’ Transponder unit (100 Mb/s B 2.7 Gb/s) (one slot wide) to be equipped
in every slot of “Basic area”, supporting both wavelength assignment function (B/W to ’col’) and
wavelength regeneration function (’colored’ to ’colored’) and performing the transparent transport of
the following ’client’ signals:

• FDDI, (not operative in current release)

• Fast Ethernet, (not operative in current release)

• STM1/OC3, (not operative in current release)

• ESCON, (not operative in current release)

• Digital Video, (not operative in current release)

• STM4/OC12, (not operative in current release)

• Fiber Channel, (not operative in current release)

• FICON, (not operative in current release)

• Gb Ethernet, (not operative in current release)

• 2 Fiber Channel, (not operative in current release)

• STM16/OC48,

• 2 Gb Ethernet, (not operative in current release)

• STM16 w/ FEC (not operative in current release)
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03 ED
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 167. COADM functionality: example of equipment shelf
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
ÖÖ ÖÁ Á
Ö
ÖÖÖÖÖÁÁÁ
Ö ÖÁ Á ÊÊ ÔÔÔ
ÊÊ ÔÔÔ ÔÔ
Ô
ÖÖÖÖÖÁÁÁ
Ö ÖÁ Á
ÖÖÖÖÖÁÁÁ
ÖÖÖÖÁÁÁ
ÖÁ Á ÊÊ ÔÔÔ Ô
ÊÊ ÔÔÔ ÔÔ
ÔÔ
ÖÖ ÖÁ ÊÊ ÔÔÔ Ô
Basic

ÖÖÖÖÖÁÁÁ
Ö ÖÁ Á ÊÊ ÔÔÔ ÔÔ
Port HS

TPD

Port HS
Port HS

ÖÖÖÖÖÁÁÁ
4 X ANY
SMT–16 ”col”
Port LS–HS

SMT–16 ”col”

Port LS–HS
Port LS–HS
EQUICO

ÖÖÖÖÖÁÁÁ
Area

Port LS Spare – HS
MATRIX A (main)

STM–16 –BW

MATRIX B (spare)
ÖÖÖÖÖÁÁÁ
Ö ÖÁ Á
ÖÖÖÖÖÁÁÁ
Ö ÖÁ Á ÊÊ ÔÔÔ Ô
ÊÊ ÔÔÔ ÔÔ
Ô
ÖÖÖÖÖÁÁÁ
Ö ÖÁ Á
ÖÖÖÖÖÁÁÁ
Ö ÖÁ Á ÊÊ ÔÔÔ Ô
ÊÊ ÔÔÔ ÔÔ
ÔÔ
ÖÖÖÖÖÖÁÁÁ
ÖÖÖÖÁÁÁÁ
ÖÖ ÖÁ Á
ÖÖÁÖ ÁÁ ÊÊÊÔÔÔÔÔÔ
Ê Ô ÔÔ Ô
ÖÖ Ö Ö Ö Á Á
ÖÖÖÁÁ Á
ÖÖ Ö Ö Ö Á Á
ÖÖÖÁÁ Á Ê Ê ÔÔ Ô ÔÔ Ô Ô
Ô Ô Ô ÔÔ
Ê Ê ÔÔ Ô ÔÔ Ô Ô
Ô Ô Ô ÔÔ
ÖÖ Ö Ö Ö Á Á
Ô Ô Ô ÔÔ
Access

ÖÖ Ö Ö Ö Á Á
ÖÖÖÁÁ Á
ÖÖ Ö Ö Ö Á Á
Ô Ô Ô ÔÔ
Ô Ô Ô ÔÔ
COADM 1/2 ch.

Access Card LS
COADM 1/2 ch.
Access Card LS

ÖÖ Ö Ö Ö Á Á
Ô Ô Ô ÔÔ

Access Card LS/HS
CONGI A

CONGI B
SERVICE
Area

Access Card LS/HS
Access Card LS/HS
Access Card LS/HS
Access Card LS/HS
Access Card LS/HS
Access Card LS/HS
Access Card LS/HS
Access Card LS/HS
Access Card LS/HS
Access Card LS/HS
Access Card LS/HS
ÖÖ Ö Ö Ö Á Á
Ô Ô Ô ÔÔ
ÖÖ Ö Ö Ö Á Á
Ô Ô Ô ÔÔ for Ring application
ÖÖ Ö Ö Ö Á Á
Ô Ô Ô ÔÔ COADM 1/2 CHANNELS
ÖÖ Ö Ö Ö Á Á
ÖÖÖÖÁÁ
ÖÖÁÁ Á Ê Ê ÔÔ Ô ÔÔ Ô Ô
ÔÔÔ Ô ÔÔ Ô Ô
Ô Ô ÔÔ Equipment example with
ÖÖÖÖÁÁ
Ö
ÖÖÖÖÁÁ
ÖÖÁÁ Á
ÖÖ Ö Ö Ö Á Á
Á ÊÊ Ô Ô Ô Ô
Ô
ÔÔÔ Ô ÔÔ Ô Ô
Ô Ô ÔÔ
9 10 11 12 13 14 15 16 17 18 19 20 21 1 2 3 4 5 6 7 8
equipment is supposed to be limited to one shelf only.
to network with limited traffic demand (supported by 1 or 2 wavelengths). For this kind of use, also the

The example below reported, shows the equipment with COADM 1(2) channels unit, as for NE’s belonging

The shelf layout of resulting equipment is showed in the following figure.
3.11.1 Equipment facilities

1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
Basic Area Access Area Basic Area Access Area
EQUICO Access Card LS EQUICO Access Card LS

03
MATRIX A (main) Access Card LS/HS MATRIX A (main) Access Card LS/HS
Access Card LS/HS MUX / DEMUX
Port LS–HS Access Card LS/HS Port LS–HS 8 Channels

Ô
Ô
Ô
ÔÔ
Ô
Ô
Ô
Ô
Ô
Ô
Ô
Ô
Ô
ÔÔ
SMT–16 ”col” Access Card LS/HS SMT–16 ”col” Access Card LS/HS
Ô Ô ÔÔ
Ô Ô ÔÔ
Access Card LS/HS MUX / DEMUX

ÔÔÔÔÔÔ
Port HS Access Card LS/HS Port HS 8 Channels

Ô ÔÔ
ÔÔÔÔÔÔÔ
ÔÔÔÔÔÔÔ
ÔÔÔÔÔÔÔ
ÔÔÔÔÔÔÔ
ÔÔÔÔÔÔÔ
ÔÔÔÔÔÔÔ
ÔÔÔÔÔÔÔ
ÔÔÔÔÔÔÔÔ
Ô Ô
Ô ÔÔ
Ô Ô Ô ÔÔ
ÔÔÔÔÔÔÔÔ
Ô
ÔÔÔÔÔÔÔÔ
Ô Ô Ô ÔÔ
Ô Ô Ô ÔÔ


ÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔÔ
ÊÊÔÔÔÔÔÔ
ÊÊ Ô Ô Ô Ô Ô Ô Ô
ÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔÔ
ÔÔÔÔÔÔÔÔ
ÊÊ Ô Ô Ô Ô
ÊÊÔÔÔÔÔÔÔ
ÊÊÔÔÔÔÔÔÔ
ÊÊÔÔÔÔÔÔÔ
ÊÊ Ô Ô Ô Ô
ÊÊÔÔÔÔÔÔÔ
ÊÊÔÔÔÔÔÔÔ
ÊÊÔÔÔÔÔÔÔ

Access Card LS/HS Access Card LS/HS
Port LS–HS CONGI A Port LS–HS CONGI A
Port HS Port HS
SERVICE SERVICE
Port LS Spare – HS Port LS Spare – HS
Port LS–HS CONGI B Port LS–HS CONGI B
Port HS Port HS

ÖÁ Á

Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
ÁÁÁ
ÁÁÁ
Á
Á


Á
Á ÖÁ Á
Á ÖÁ Á
ÁÁÁ Ö ÁÁ Á
Á ÖÁ Á
Á ÖÁ Á
ÁÁ Ö Á Á
ÖÖÁÁ
Á ÖÁ Á
Á ÖÁ Á
Á ÖÁ Á
Á ÖÁ Á
Á ÖÁ Á
ÁÁ Ö Á Á
ÁÁ Ö Á Á
ÖÖÁÁ
ÖÖÁÁ

Port LS–HS Port LS–HS

ÖÖ Ö Á Á
Ö Ö ÁÁ Ö ÁÁ Á
ÖÁ
ÖÖÁÖ Á Á
ÖÖÖÁÁ
ÖÖÖÁÁ
ÖÖÖÁÁ
ÖÖÖÁÁ
ÖÖÖÁÁ
ÖÖÖÁÁ
ÖÖÖÁÁ
ÖÖ Ö Á Á Á
ÖÁ
Ö Ö Á Á Ö ÁÁ Á
ÖÖÁÖ Á Á
ÖÖÖÁÁ
ÖÖÖÁÁ
ÖÖ Ö Á Á Á
Ö Á
ÖÖ Ö Á Á Á
ÖÖÖÁÁ
ÖÖÖÁÁ

MATRIX B (spare) MATRIX B (spare)

Ö Ö Ö Ö Á Ö ÁÁ Á
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á
Ö Ö Ö Ö Á Ö ÁÁ Á
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á
ÖÖÖÖ
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á
ÖÖ Ö Ö Á Á Á

Access Card LS Access Card LS

interface, 4xANY, double TPD, etc.) is the same in both equipment facilities.

706
A further example, shows the equipment with” MUX/DEMUX 8 channels units”.

3AL 91669 AA AA
are then required in order to host the needed amount of STM16 ’CWDM’ interfaces.
Figure 168. MUX/DEMUX functionality: example of shelf equipment
REQUIRED)
handling 4 CWDM
Equipment example with

(2 SEPARATE SHELVES
FOR RING APPLICATON
MUX/DEMUX 8 Channels

The capability to host within the single shelf, the items required for ’OADM’ application (STM16 ’colored’
In this case 4 wavelengths are supposed to be terminated by the node in ’ring’ application; two shelves

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3.11.2 Functional description

1660SM with WDM signal flow is functionally based, both in ’ring’ and ’linear’ application, on three
directions:

1660SM 1660SM function
interfacing

Figure 169. 1660SM signal flow diagram with WDM application

[1] “client” signals groomed by SDH matrix and carried by ’CWDM’ wavelengths;

[2] “client” signals not groomed by SDH matrix and carried, transparently, by ’CWDM” wavelengths
(wavelength assignment on B/W signals);

[3] “server” signals not groomed by SDH matrix and regenerated on same or different wavelength.
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3.11.3 “Ring” node functional scheme

In the following, different examples of 1660SM (WDM application) configured as a ’ring’ node are showed.

In every hypothesis, all the items involved (represented in gray color) are hosted in a 1660SM shelf.

Figure 170. 1660SM (WDM application) ’ring’ node functional scheme (1)

Specifically, the node represented in Figure 170. terminates on each side, two channels on STM 16
’colored’ interfaces. The wavelengths multi/demultiplexing is supposed to be performed by MUX/DEMUX
8 channels
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In Figure 171. the node realizes the wavelengths termination by using also ’Double channel transponder’
unit.

Optical multi/demultiplexing is, anyway, performed through MUX/DEMUX card.

Channels terminated into STM16 interfaces can be processed and cross–connected by SDH blocks till
the LO granularity; while channels terminated into ’Transponder’ are not groomed at any level but either
adapted to the transmission technique or recovered from line degradation.

Next Figure 172. and Figure 173. , show the functionality of a ’ring’ node using COADM 1 (2) ch. for
wavelengths multi/demultiplexing.

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It can be noticed that there is no difference with respect the use of MUX/DEMUX device as regards the
processing of terminated channels (both in SDH matrix and in ’Transponder’ unit); as a difference, the
COADM structure include a specific link for by–passing those channels of the grid not locally terminated.
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3.11.4 “Terminal” node functional scheme

As already considered for ’ring’ application, the following figures shows the functionality of 1660SM (WDM
application) configured as the end of a ’linear’ network (i.e. point–to–point connection).

Both cases of MUX/DEMUX unit (Figure 174. ) and COADM unit (Figure 175. ) used in ’end’ node are
depicted.

Figure 174. 1660SM (WDM application)’end’ node functional scheme (Mux/Demux)

Also in this application all the physical parts involved (showed in gray color) are hosted in 1660SM shelf.

No difference, with respect termination channels functionality, already depicted for ’ring’ application,
exists.
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Figure 175. 1660SM (WDM application) ’end’ node functional scheme (COADM)

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3.11.5 Optical span design

The aim of this paragraph is defining the optical performances of 1660SM based on CWDM technology.
The optical performances definition bases on the optical characteristics related to CWDM devices

supported by the equipment (Transceivers, Mux/Demux, OADM) and on the fiber cable characteristics

supposed.

The CWDM technology is characterized by channel spacing wider than Dense WDM and allows to realize
cost–effective applications, through a combination of un–cooled lasers (huge λ deviation versus
temperature range, e.g. 8 nm), relaxed laser wavelength selection tolerances (e.g. ± 2 nm) and wide
pass–band filters (e.g. 14 nm) inside the optical passive functions.

The following paragraphs concern:

[1] CWDM channels used
[2] the optical functions characteristics in terms of structures and insertion losses ( Mux/Demux/OADM
optical operations: structures and insertion losses);
[3] the fiber attenuation coefficient and fiber chromatic dispersion profile
[4] the transceiver optical characteristics necessary for power budget calculation

[1] CWDM channels table

The set of wavelengths used in the 1660SM equipment is a subset of the nominal central wavelengths
grid defined in the ITU–T G.694.2 Recommendation for coarse WDM systems. The complete CWDM
wavelengths grid range is from 1270 nm to 1610 nm with spacing of 20 nm. This spacing is the trade–off
between the coarse technological aspects and the need to maximize the number of channels available.

Table 44. CWDM channels grid supported by 1660SM

Nominal central wavelengths (nm)
used in the CWDM 1660SM

1470

1490

1510

1530

1550

1570

1590

1610
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[2] Mux/Demux/OADM optical operations: structures and insertion losses

1660SM supports the following WDM functions:

– multiplexing and demultiplexing of 8 CWDM channels without ’channels pass–through’ link through

COMDX8;

– multiplexing and demultiplexing of 2 CWDM channels with ’channels pass–through’ link through
COADM2;

– multiplexing and demultiplexing of 1 CWDM channel with ’channels pass–through’ link through
COADM1.

Figure 176. shows a generic application of the optical functions listed above with the definitions used in
the following paragraphs.

Table 45. shows the maximum insertion losses (dB) between:

– demux ’In’ and generic channel ’Drop’;

– generic channel ’Add’ and mux ’Out’;

– demux ’In and mux ’Out’ (’Pass–through’ connection).

Note – Channel loop insertion–loss is given by adding demux ’In’ and generic channel ’Drop’ to generic
channel ’Add’ and mux ’Out’.

Pass–through
Demux

Fiber Fiber
Mux

In Out
Loop

Drop Add

West East
Pass–through
Demux

Fiber
Mux

Out Loop In Fiber

Add Drop
Board #1 Board #2
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 176. Passive optical operation

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Note – Insertion loss values related to ’In – Drop’ channel and ’Pass–through’ includes an assumed
0.5 dB insertion loss due to ’CWDM LOS detection stage’ equipped in Mux/Demux/OADM boards

Note – Contribution of Chromatic Dispersion related to Mux/Demux/OADM optical operations has

been considered equals 0 ps/nm (range currently considered in devices specification is ± 30 ps/nm).

Table 45. Boards insertion loss

Optical function Add Ch. Out insertion Loss (dB) Pass.–th
Channels (um) I.L. (dB)

1.47 1.49 1.51 1.53 1.55 1.57 1.59 1.61

MUX (COMDX8) 1.05 1.35 1.65 1.95 2.25 2.55 2.85 3.15

COADM2 1.55 1.55 1.55 1.55 1.55 1.55 1.55 1.55 2.5

COADM1 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 2.1

Optical function In – Drop Ch. Insertion Loss (dB) Pass.–th
Channels (um) I.L. (dB)

1.47 1.49 1.51 1.53 1.55 1.57 1.59 1.61

DEMUX (COMDX8) 1.05 3.15 2.85 2.55 2.25 1.95 1.65 1.35

COADM2 1.55 1.55 1.55 1.55 1.55 1.55 1.55 1.55 2.5

COADM1 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 2.1

Figure 177. , Figure 178. , Figure 179. highlight the ’Insertion loss’ values as regards COMDX8,
COADM2, COADM1.

In the 8 ch.s Mux/Demux operation (COMDX8), the specific equalization (to be considered for device
implementation) of the channel loop ’Insertion loss’ versus channels, can be noticed: the result is a
constant channel loop insertion loss from 1.49 to 1.61 um wavelength, while a minor value occurs at 1.47
um.

This solution allows to optimize ’span length’ performance, considering both ’typical’ attenuation profile
of the Standard SMF, wavelength and number of intermediate nodes within a referenced span: the benefits
are in terms of possible longer distances between the nodes or greater power margins between the optical
interfaces.

In 2 ch.s Mux/Demux operation (COADM2) the channel loop insertion loss has the same value for every
couple of wavelengths.
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1.05 2.1 1.05
3.15 1.35

2.85 1.65

Fiber

Demux
Fiber In 2.55 1.95 Out

Mux
2.25 5.5 2.25
1.95 2.55
1.65 2.85
1.35 3.15

West East
1.05 2.1 1.05
1.35 3.15
1.65 2.85

Demux
Fiber Out 1.95 2.55 In Fiber
Mux

2.25 5.5 2.25
2.55 1.95
2.85 1.65
3.15 1.35

Board #1 Board #2

Figure 177. COMDX8 insertion loss

1.25 2.5 1.25

1.55 3.1 1.55
Demux

Fiber In Out Fiber
Mux

1.55 1.55

West East
1.25 2.5 1.25

1.55 3.1 1.55
Demux

Fiber Out In Fiber
Mux

1.55 1.55

Board #1 Board #2
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 178. COADM2 insertion loss

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1.05 2.1 1.05

Demux
Fiber

Fiber In 1.25 2.5 1.25 Out

Mux

West East
1.05 2.1 1.05

Demux
Fiber Out 1.25 2.5 1.25 In
Mux Fiber

Board #1 Board #2

Figure 179. COADM1 insertion loss

[3] Fiber Technical Data

The referenced fiber for span length evaluation is the Standard Single Mode (SSMF) ITU–T G. 652.

The parameters in Table 46. and they are based on data coming from ITU–T G.957 Recommendation.
The column ’Typical Attenuation Coefficient’ includes losses due to installation splices, repair splices, and
the operating temperature range.
The column ’Maximum Attenuation Coefficient’ is obtained by considering a maximum attenuation
coefficient of about 0.3 dB/Km1. in the 1500 ÷ 580 nm and, in general, assuming a +30% tolerance over
the whole wavelength range supported by the equipment.

Table 46. Fiber technical data

Lambda Typical Attenuation Max. Attenuation Max. Chromatic Dispersion
(um) Coefficient (dB/Km) Coefficient (dB/Km) Coefficient (ps/nm/Km)
1.47 0.28 0.36 13.10
1.49 0.24 0.31 14.50
1.51 0.22 0.29 15.80
1.53 0.21 0.27 17.30
1.55 0.21 0.27 18.50
1.57 0.22 0.28 19.60
1.59 0.22 0.29 20.50
1.61 0.23 0.30 21.50
1AA 00014 0004 (9007) A4 – ALICE 04.10

1. The 0.3 dB/Km value is in compliance with the system calculation purposes indicated in the ITU–T
G.957 Recommendation.

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[4] Line transceivers and optical interface power budget (Tx–Rx)

The optical interfaces considered for power budget, span power budget and span length calculation have
the main optical characteristics showed in Table 47.

These optical interfaces are realized through ’2R’ transceivers integrated in SFP MSA device.

Three specific devices allows to achieve the best ’performance/cost’ ratio, matching specific network
characteristics.

The two modules are:

– SFP with PIN detection, consistent with span length around 40 Km (called hereafter BRONZE
version);

– ’standard’ SFP with APD detection, consistent with span length around 70 Km (called hereafter
SILVER version);

Table 47. Optical transceiver characteristics

PARAMETER Unit Symbol BRONZE SILVER REFERENCE

Transmitter Output Optical power dBm POUT Min. 0 0
(EOL)
Typ.

Max. 5 5

Chromatic dispersion ps/ D*Km Min. 1000 1600
nm

Receiver Average Rx dBm RSENS Max. –18 –28 1
Sensitivity@OC–48+FEC

Maximum input power dBm PMAX Min. –3 –9

Optical Path Penalty dB Max. 1 2

REFERENCE:

1 – Worst–case extinction ratio (8.2dB). Measured with a PRBS 223–1 test pattern, @2.67Gb/s,
BER10–12, EOL.
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3.12 Controller sub–system

The 1660SM control sub–system is based on a two level model :

– Equipment Controller (EC) implemented by the EQUICOE (PQ2/EQC) card.
– Shelf Controller (SC) implemented as part of the MATRIXE card.

The EC provides the HW resources (physical interfaces) and the SW functionalities (protocol stack)
required for the communication between NE and Management system ( OS, craft terminal, etc).
It performs as well all the SW functions related to the control and management activities like info–model
processing, event reporting and logging, equipment data base management, SW downloading and
management, etc.
To support these activities, the EC function requires a non volatile mass storage device (flash card).
The SC provide the resources to support the SW functions related to the control and management
operation of the boards. To perform its functions, the SC directly interfaces the ASICS on the board
implementing the SDH functions for data collection (faults or alarm event detections, performance
monitoring data) and configuration provisioning.
As the SC is involved in critical activities ( for instance EPS ) , is 1+1 protected.

Internal bus
For the controller sub–system the following busses are defined:

– ”Management bus” that allows:

• connection between SC and boards for configuration data provisioning
• remote inventory data acquisition
• data collection ( alarms ) and commands handling (ex. loops)

– “ISSB bus” used for communication among the Equipment Controller, the Shelf Controllers and
the Local Microprocessor (present for example on ISA board).

External interfaces toward Craft Terminal, OS and Mediation Device

F interface : available from the EC function for connection to a local Craft Terminal; the electrical interface
and connector are provided by the EQUICOE card.
The standard implementation of the physical layer for the F interface consists of an RS–232 UART port
accessible from the EQUICOE card front panel.

USB interface :The USB interface is foreseen as an alternative option for connection to external PC
supporting the Craft Terminal function; it is currently not operative.
QECC interface: is a TMN related communication interface based on the use of the Embedded
Communication Channels available in the SOH portion of the SDH frame. Through the QECC interface
the 1660SM can exchange management messages with a remote OS.
In the 1660SM up to three full duplex ECC channels can be terminated from each SDH interface: one
DCC_M at 576 kbit/s, one DCC_R at 192 Kbit/s and one DCC_P 64 Kbit/s(F2, F3 bytes of VC4 ).
QAUX interface: is provided as an additional TMN communication interface for message exchange
between the NE and a Remote OS station based on the use of a 2 Mbit/s proprietary protocol.
QMD interface: a Q2/RQ2 mediation function interface is provided to connect the 1660SM to non–SDH
NEs; both the master mode and slave mode operations are supported.
1AA 00014 0004 (9007) A4 – ALICE 04.10

The RS–485 interface and the cable connector are provided on the CONGI card.

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QB interface: it is dedicated to an OS station connection. QB3 options is supported for the connection
to a LAN through a 10BASE2 or a 10BASET interface; the physical interfaces are provided by CONGI
card.

RE / HK interface: this interface consists of parallel I/O signals used for remote alarms and for

housekeeping signals.
The relevant electrical interfaces are placed on the two CONGI cards, and are controlled by the EC
function through parallel I/O ports.

RA interface: it is dedicated to send commands toward the rack to light up the relevant lamps.

REMOTE
Rack leds NON SDH OPERATION OPERATION
EQUIPMENT SYSTEM SYSTEM

Remote andHousekeeping Alarm

QB
QAUX
RA QMD
RE/HK RE/HK

EXTERNAL EXTERNAL EXTERNAL
INTERFACE INTERFACE INTERFACE

CONGI a CONGI b SERVICE

Local Management BUS
F
Craft Terminal

USB SC SC
not operative EC

QECC ISSB

FLASH
CARD

PQ2/EQC MATRIX a MATRIX b

Management BUS

Local Access
STM–1 Microprocessor Modules
STM–1
ISA units
1AA 00014 0004 (9007) A4 – ALICE 04.10

SDH units PDH units

Figure 180. 1660SM Control Sub–system

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3.12.1 Network management interfaces
(See Figure 181. on page 318 and Figure 182. on page 318)

The management of the equipment is realized by :

• a Craft Terminal (CT).

• an Operations System (OS) made up of one or more Workstation, whose function is widened
to networks management. Further it permits the connection to the Telecommunications
Management Network (TMN).

Figure 181. on page 318 illustrates an example of management architecture of the equipment.

The Craft Terminal interface is an EIA–RS232 type (F interface). It can be:

– local, connecting the Craft Terminal via the F interface.

– remote, from another SDH equipment or SDH gateway of the network where a Craft Terminal is
connected (to the F interface), addressing the actual equipment. In this case the management
information is transported by the optical network, utilizing DCC bytes (Qecc link), or routed by a LAN.
When Remote Craft Terminal option is used, a max of 32 equipments are manageable by means of
one F interface. This equipment can address and manage remote SDH nodes by means of this
functionality.

Interface QB3 permits to establish connection with the OS; the management information can be
transported by the optical network, utilizing DCC bytes (Qecc protocol) or by a dedicated LAN network.

It supports dual addressing to OS, allowing OS redundancy protection.

The connection mode is indicated in the following (see Figure 182. on page 318).The Equipment
Controller EC ( physically on the EQUICOE unit) transfers messages between QB3 and DCC.
To forward TMN messages towards other NE’s, the Equipment Controller uses the QECC bus connected
with the STM–1 ports.
In this way the messages are transmitted on D1:D12 bytes of STM (DCC). The connected NE extracts
the messages from these bytes and sends them to the Equipment Controller.

In the selected NE the Equipment Controller uses the MANAGEMENT BUS to exchange data with the
units.
This data is then transferred towards the Operative System via the STM–1 DCC. In all the NE not involved
the Equipment Controller lets through the DCC between the two opposite STM–1 port (STM–1 port A and
STM–1 port B in the example of Figure 182. on page 318).
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LAN

OPERATION 1660SM OPERATION
SYSTEM GATEWAY SYSTEM

LAN
LAN DCN LAN
BRIDGES BRIDGES

QB3
1660SM F CRAFT 1660SM F 1660SM F
GATEWAY TERMINAL GATEWAY

DCC DCC

DCC
1660SM 1660SM 1660SM F
NE NE NE

F

CRAFT
F TERMINAL DCN : DATA COMMUNICATION NETWORK

Figure 181. 1660SM general management architecture

OPERATION
SYSTEM

LAN

QB3

CONGI

STM–1 EC STM–1
port A port B
QECC QECC

QECC BUS NE
STM–1 MANAGEMENT BUS
port B

NE ( 1660SM–GATEWAY)
MANAGEMENT
BUS
E
C

STM–1
port A
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 182. Connection Mode for TMN

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3.12.2 ATM/IP/MPLS over SDH Management

The management of SDH equipments is organized as required by the 7–layers ISO/OSI protocol stack,
while the ATM/MPLS equipments are usually managed by means of SNMP (Simple Network Management

Protocol), that is an application of the TCP/IP reference model.

By carrying the data traffic (ATM,MPLS, Ethernet) over the SDH network structures there is the need to
manage together and contemporarily SDH and ATM/MPLS equipments; this function is accomplished by
means of the encapsulation of SNMP messages inside the OSI layers (”IP over OSI tunneling”). In this
way the ATM/MPLS management information is transported over the existing SDH networks.

The various protocols relations are illustrated in Figure 183. on page 319.

An example of ATM/IP/MPLS/SDH network management is shown in Figure 184. on page 320.
In this example, the OS enters the network management messaging over an Ethernet link (IEEE–802.3
protocol) of a Gateway NE (GNE); here the messages are transported over the optical Qecc links by
means of the LAPD protocol; at the remote managed nodes, the messages are acknowledged as
belonging to:

• OSI reference model, for SDH management

• TCP/IP (SNMP) reference model, for IP/ATM management.

Application Lay7

Presentation Lay6

SNMP Session Lay5 ISO/OSI protocols
Internet
protocols TCP Transport (TP4) Lay4

IP Network
(CLNP) Lay3

3
4 2 1

TMN protocols Ethernet LAPD Lay2
(QB3) TMN protocols
QB3 ECC Lay1 (Qecc)

1): OSI stack for SDH management (Qecc interface)
2): IP over OSI tunneling for IP/ATM management (Qecc interface)

3): OSI stack for SDH management (Qb3 interface)

4): IP over CLNP tunneling for IP/ATM management (GNE entry from OS, IEEE–802.3)
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 183. Protocol stack for SDH/ATM management

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SDH (OSI) ATM/IP/MPLS (SNMP)
OS
TMN
QB3
802.3

QECC LAPD QECC

Gateway NE
(GNE)
F
CT OSI
LAPD F
SDH+ATM/IP/MPLS SDH NE LAPD OSI
SNMP
NE

QECC QECC

F SDH+ATM/MPLS
CT SDH NE OSI
LAPD OSI F
NE LAPD
SNMP

QECC

QECC
LAPD

SNMP
OSI F

SDH+ATM/IP/MPLS
NE
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 184. Example of management of a network with SDH and ATM/IP/MPLS traffic

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3.13 Protection sub–system

The types of protections are:

• Equipment protection (EPS)

The EPS protection is supported on the 1660SM equipment for the following cards :

Equipment Boards Protection Scheme Number of protec- Mode
tion schemes

MATRIXE 1+1 1 Not revertive

Low Speed ports : N+1 (N max = 6) 1 Revertive
– 63x2Mbit/s

High Speed electrical N+1 (N max=15) 1 to 8 Revertive
ports :
– 4xSTM–1 elect.
– 16xSTM–1 elect.
– 3x34/45Mbit/s

ATM matrix 4x4 1+1 2 Not revertive

ATM matrix 8X8 1+1 2 Not revertive

ISA ES16 1+1 4 Not revertive

MPLS boards
– PR_EA Matrix 1+1 2 Not revertive
4xEthernet
– PR_EA Matrix 1+1 2 Not revertive
1xGB–Ethernet

N.B. Note that for the LS and HS ports, the protection scheme 1+1 is a particular case
of an 1+N EPS protection scheme (is then revertive).

• Network protections:

– MSP (Multiple Section linear trail Protection)

• 1+1 linear single–ended
• 1+1 linear dual–ended
• 1 : N linear dual–ended

– SNCP/I and SNCP/N
It is used on ring, linear and mesh network topology. Switching occurs on the path,
selecting (Rx side) the signal transmitted to both Tx A and Tx B ( A and B are two different
directions) sides.

– Drop Continue
It is an architecture to connect sub–networks, in order to improve traffic availability.
1AA 00014 0004 (9007) A4 – ALICE 04.10

– Collapsed dual node ring interconnection
It is an architecture to connect sub–networks, in order to improve traffic availability with
hardware resource reduction (two nodes collapse in one node).

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– Collapsed single node ring interconnection
It is an architecture to connect sub–networks, in order to improve traffic availability with
hardware resource reduction (four nodes collapse in one node).

– 2F MS–SPRING, 2 fibres Multiple Section Shared Protection

The switching information is also indicated on the Craft Terminal screen.

3.13.1 EPS Protections

[1] Matrix card protection

The positions of main and spare MATRICES are fixed :

• Slot 23 : MATRIXE main

• Slot 40 : MATRIXE spare

[2] Low Speed (LS) port protection

As Low Speed ports (LS) are intended the 2 Mbit/s speed ports . The Low speed port can manage up
to 63 x 2 Mbit/s port.

The LS ports are connected in a fixed way to the pertaining access cards (refer to para 2.3 on page 110)
using point–to–point connections.

To connect the 63 2 Mbit/s streams 3 access cards are needed : twenty one bidirectional links are used
for each connection between LS port and LS access card.

The spare LS port is connected with all the access cards using point–to–multipoint connections.

Only one protection group N+1 revertive can be created because the spare port card must be in a fixed
position :

• Slot 32 : spare card

The switches to select between main links and protection links are located on the access cards and
managed by a microprocessor. The switch is activated in case of failure.

Figure 185. on page 323 shows the connection between main ports, spare card and access card in case
of 63 x 2 Mbit/s port.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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63 x 2 Mbit/s
ACCESS CARDS
MAIN PORT CARDS

21 main links 21 protection links

ÉÉÉÉÉ SLOT 1

SLOT 2
MainÉÉÉÉÉ
ÉÉÉÉÉ SLOT 3
Slot 24
ÉÉÉÉÉ
ÉÉÉÉÉ 2 Mbit/s from/to DDF
SLOT 4

Main
ÉÉÉÉÉ
ÉÉÉÉÉ SLOT 5

SLOT 6
Slot 27
ÉÉÉÉÉ
ÉÉÉÉÉ
2 Mbit/s from/to DDF

SLOT 7

Main
ÉÉÉÉÉ
ÉÉÉÉÉ SLOT 8

Slot 30 SLOT9
ÉÉÉÉÉ
ÉÉÉÉÉ
SLOT 13

Main
ÉÉÉÉÉ
ÉÉÉÉÉ SLOT 14

Slot 33 SLOT 15
ÉÉÉÉÉ
ÉÉÉÉÉ

SLOT 16

Main
ÉÉÉÉÉ
ÉÉÉÉÉ SLOT 17

Slot 36 SLOT 18
ÉÉÉÉÉ
ÉÉÉÉÉ 63 x 2 Mbit/s
SPARE PORT CARD
ÉÉÉÉÉ SLOT 19
ÎÎÎÎ Spare
Main
ÉÉÉÉÉ SLOT 20 ÎÎÎÎ Slot 32
ÉÉÉÉÉ
Slot 39
ÉÉÉÉÉ SLOT 21 ÎÎÎÎ
ÎÎÎÎ
ÉÉÉÉÉ
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 185. Low Speed Link Connections

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[3] High Speed (HS) port protection

As High Speed ports (HS) are intended the 34 Mbit/s , 45 Mbit/s and 155 Mbit/s speed ports.

Up to 16 HS ports can be housed in the basic area.

For the electrical HS ports the corresponding access cards have to be put in the access area with fixed
relations (refer to para 2.3 on page 110 ).

More than one protection group N+1 revertive can be created , depending on the equipment configuration.
For each group N + 1 protected group the revertive mode is supported.

The spare card position can be assigned in a flexible way . The only constraint are the following :

• the access card corresponding to the protecting card must be an HPROT card
• the HPROT card has to be plugged at the left side of the access card group
• the main/spare ports have to be adjacent.
• the protecting card has to be plugged at the left side of the protected group of ports
• the protecting/protected group of ports have to be of the same type. The only exception is for
the 3x34/3x45 port card : it can be a protecting card for both 3x34 or 3x45 port card i.e. a mixed
group of ports can be protected by the same spare card.

Figure 186. on page 324 gives some examples of EPS protection scheme.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
ÖÖÖÖÖÁÁÁ
ÖÖ Ö Ö Á Á Á
ÖÖÁÁÁ
ÖÖÖÖÖÁÁÁ
ÖÖÖÁÁÁ ÊÊÊÔÔÔÔÔ
ÊÊ Ô Ô Ô Ô Ô
ÔÔÔÔÔ
ÔÔÔÔ
ÊÊÊÔÔÔÔÔ
ÊÔÔÔÔÔ
Ô
access card 21 x 2 Mbit/s

Access
ÖÖÖÖÖÁÁÁ
ÊÔÔÔÔÔ
Ô
access card 4 x STM1


Area
ÖÖÖÖÖÁÁÁ
ÊÔÔÔÔÔ
Ô
SERVICE
CONGI B
CONGI A

HPROT

HPROT
HPROT

ÖÖÖÖÖÁÁÁ
ÖÖÖÁÁÁ
ÖÖÖÖÖÁÁÁ
ÊÔÔÔÔÔ
Ô
ÊÊÊÔÔÔÔÔ
ÊÔÔÔÔÔ
Ô
ÖÖÖÖÖÁÁÁ
ÖÖÖÁÁÁ
ÖÖÖÖÖÁÁÁ
ÊÔÔÔÔÔ
Ô
ÊÊÊÔÔÔÔÔ
ÊÔÔÔÔÔ
Ô
ÖÖÖÖÁÁÁ
Ö Ê Ô
ÊÊÔÔ
ÖÖÖÖÖÖÁÁÁÔÊÊÊÊÔÔÔÔÔÔ
ÖÖÖÖÁÖÁÔ ÊÊÔÊÔÔÔÔ
Ö Ö Ö ÖÁ Á
ÖÁÁÁ Á ÊÔÔÔÔ
ÖÖÖÖÁÁÁÔÊÊÊÔÔ ÔÔ
ÖÖÖÖÁÁÔÊÊÊÔÔ ÔÔ
Ö ÖÁ Á Ô Ê
ÁÁÔ Ê
port 4 x STM 1 electrical

port 3x34 / 45 switchable
port 63 x 2 Mbit/s (spare)

ÖÖÖÖÖÁÁÔÊÊÊÔÔ ÔÔ
Ö Ö ÖÁ Á Ô Ê
Á
MATRIX B (spare)
MATRIX A (main)

port 63 x 2 Mbit/s

port 63 x 2 Mbit/s

Ö Á
ÖÖÖÖÖ
PQ2/EQC

Basic ÖÖÖÖÁÁÁÔÊÊÊÔÔ ÔÔ
Ö ÖÁ Á Ô Ê
ÁÁÔ Ê
Area
Ö Ö ÖÖ Á Ô Ê
Á
Ö Ö ÖÁ Á Ô Ê
Á
Ö Á
ÖÖÖÖÖ
Ö ÖÁ Á Ô Ê
ÁÁÔ Ê
Ö Ö ÖÁ Á Ô Ê
Á
Ö Á
ÖÖÖÖÖ
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Figure 186. Example of EPS protection schemes
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Manual Switch and force switch commands can be given via software by the user to activate the spare
cards.
The protections status is reported to the EC.

Figure 187. on page 326 shows an example of High Speed connections for the 2+1 protection.

Each access card is connected also with the previous one and with the next one; in this way N+1 protection
is provided using HPROT card in last position at the left side of the access cards pertaining to the protected
port group.

Each electrical High Speed port can manage up to 4 HS streams.

Input side ( from the access module point of view)

The CMI encoded signal coming from the line and connected to the access card is NRZ decoded. The
clock CK is extracted from the data. By means of the back panel connections , NRZ data and CK are
forwarded to the pertaining main port and to the spare port.
Moreover NRZ data and Clock are sent to the next access card if present to perform N +1 protection.
The spare port should not be devoted to a specific main port therefore a distributed switch matrix (on every
access card ) is used to allows the signal to gain the spare port.
The command criteria for the distributed switch matrix comes from the matrix unit via serial interface.

Output side ( from the access module point of view )

The signal , coming from Main and Spare ports via back panel connections , is coded into CMI format.
The spare port is not devoted to a specific main port, therefore the signal transmitted from the spare is
distributed to all access cards involved in the protection scheme. The connections are functionally
point–to–multipoint but physically every access card realizes a point –to–point connection towards the
previous and the next access card using a buffer to decouple and regenerate the signal.

Hardware failures types

The hardware failures causing automatic EPS protection switch can be grouped as :

– failures causing the internal equipment link loss as powering KO, Clock loss, card missing (referred
as LOS/LOF)

– failures causing traffic loss (the internal link is preserved) as for instance unlocked oscillator, optical
module defective, electrical interface defective and so on.

– failures not causing traffic loss nor internal link loss but causing loss of management as ISBP failure
or SPI failure.

Moreover some failures can cause equipment malfunctioning ( as remote inventory fault, laser degrade,
loss of DC/DC synchronism ).
These hardware faults are signalled to the management system and do not provokes an automatic switch.

Figure 188. on page 327 shows an example of 16X STM1 High Speed connections for the 3+1 protection.
The protection scheme operation for 16xSTM–1 is similar to the above described for 3x34 Mb/s, 3x45 Mb/s
and 4xSTM–1 boards, with the exception that the signals exchanged among the board are at 1.66 Gbit/s
(Input/Output SERDES bit rate).
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03
Input Output Input Output
NEXT PREVIOUS

CMI CMI CMI
CMI

CMI
CMI

CMI
CMI
NRZ
NRZ

NRZ
NRZ
MAIN MAIN
HPROT ACCESS CARD ACCESS CARD

NRZ–CK NRZ–CK
NRZ–CK
MUX

MUX
MUX

MUX
MUX MUX

Buf. Buf. NRZ–CK
NRZ–CK
NRZ–CK
Buf. Buf.

MUX MUX

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3AL 91669 AA AA
NRZ–CK NRZ–CK NRZ–CK NRZ–CK

Figure 187. High Speed connections (3x34, 3x45, 4x155 Mbit/s)
NRZ–CK NRZ–CK

MAIN PORT MAIN PORT
SPARE PORT

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16 x STM1 electrical EPS protection scheme (example)

1 16 1 16 1 16

HPROT
Spare Path STM–1 Spare Path STM–1 Spare Path STM–1
Mapper/Demapper Mapper/Demapper Mapper/Demapper

ACCESS ACCESS ACCESS
CARD N+1 CARD N CARD N–1

SERDES SERDES SERDES
CK 19.44
Spare Path Spare Path
MHz Spare Path

SERDES SERDES SERDES SERDES
CK 19.44 CK 19.44 CK 19.44
MHz MHz MHz

Figure 188. High Speed connections (16xSTM–1)

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SPARE FAULTY
PORT CARD PORT CARD PORT CARD PORT CARD
N+1 N N–1

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[4] ATM MATRIX (ATM4x4, ATM4X4V2 , ATM4X4D3 and ATM8x8) protection

(see Figure 189. on page 329)

N.B. The following description is applicable to ATM4x4, ATM4X4V2, ATM4X4D3 and ATM8x8

boards; unless otherwise specified.

The ATM MATRIX boards can be protected in 1+1 equipment protection scheme.
In this configuration the ATM MATRIX and all indirect interfaces connected to it are protected against ATM
module failure.
This does not apply to the local STM–1 interfaces of the ATM4x4 board.
In this configuration when the working ATM matrix fails the spare becomes active and the indirect
interfaces are rerouted to it.
The traffic from the local interface of the ATM4x4 board is lost.

The following ATM protection group can be created:

ATM board type Max. number of protection Mode
groups
ATM4x4 2 1+1 not revertive
ATM4x4V2 2 1+1 not revertive
ATM4x4D3 2 1+1 not revertive
ATM8x8 2 1+1 not revertive

The spare card position can be assigned in a flexible way; no restrictions for position of main and spare
ATM MATRIX board are present.


The ATM MATRIX is managed by SDH EC, SC, Platform and ATM EC. In outline the management can
be divided in:

• SDH side Management: involving SDH EC, SC and Platform, it mainly applies to the Equipment
Domain of ATM MATRIX board.
In particular:

– SDH EC: management of Equipment Protection Groups and interface towards the SDH
Network Management System (e. g. creation of Protection Schemes, operator
commands, autoswitch notifications)

– SC/ Platform: management of HW

• ATM side Management: involving ATM EC, it mainly applies to the ATM Transmission Domain
of ATM MATRIX board.

Figure 190. on page 330 represent the messages exchanged between the EC (on the PQ2/EQC board)
and the ATM MATRIX boards in protection group.
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1660SM

EXAMPLE #1

SERVICE
CONGI B
CONGI A
Protection Board Slot # Slot #
group # Type board main board spare

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
ÔÔÔÔ
ÔÔÔÔ 1
ATM
MATRIX 25 24
4X4
ÁÁÁÁÑÑÁÁÁÁÔÔÔ
ÁÁÁÑÑÁÁÁÁÔÔÔ
ÁÁÑÑ Á Á Ô ÔÔÔÔ
ÁÁÁÁ ATM
2 MATRIX 30 31 28 29
Spare

Spare
Main

Main

Á ÁÑÑ Á Á
ÁÁÑÑ Á Á Ô ÁÁÁÁ 8x8

MATRIX B (spare)
MATRIX A (main)

Á ÁÑÑ Á Á
Á Ô ÁÁÁÁ
PQ2/EQC

ATM MATRIX 4X4
ATM MATRIX 4X4

ATM MATRIX 8x8

ATM MATRIX 8x8

Á ÁÑÑ Á Á
Á Ô
Á
Á ÁÑÑ Á Á
Á ÁÑÑ Á Á
Á Ô
Ô
Á ÁÑÑ Á Á
Á Ô
Á ÁÑÑ Á Á
Á
Á
ÁÁ
Á Ô
Ô
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

1660SM

EXAMPLE #2
SERVICE
CONGI B
CONGI A


ÔÔÔÔ ATM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 MATRIX 27 24

ÔÔ ÁÁÔ
Á
ÔÔÔÔ
ÁÁÁÁ ÁÁÁ Á Á Ñ 4X4
ATM
ÁÁÑ
ÁÁÁÁ ÁÁÁ Á Á Ñ 2 38 39 28 29
Spare

Spare

MATRIX
Main

Main

ÔÔ 8x8

ÁÁÁ
ÁÁÔ ÁÁÑ
ÁÁÁÁ ÁÁÁ Á Á Ñ
MATRIX B (spare)
MATRIX A (main)

ÔÔ Á
Ô ÁÁÁÑ
ÁÑ
PQ2/EQC

ATM MATRIX 4X4

ATM MATRIX 4X4

ATM MATRIX 8x8

ATM MATRIX 8x8

ÔÔ ÁÁÔ
Á ÁÁÁ Á Ñ
Á
ÔÔ
ÔÔ ÁÁÔ
Á
ÁÁÔ
Á ÁÁÁ Á Á Ñ
ÁÁÁÑ
ÁÑ
ÁÁÁ Á Á Ñ
ÁÁÑ
ÔÔ
ÔÔ ÁÁÔ
Á
ÁÁÔ
Á ÁÁÁ Á Á Ñ
ÁÁÑ
ÁÁÁ Á ÑÑ
ÁÁÑ
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
ÔÔ ÁÁÔ
Á Á
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 189. Examples of ATM MATRIX EPS protection scheme

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Figure 190. Messages exchanged between the EC and the ISA–ATM boards in EPS group
boards
towards both ATM MATRIX
(including PNNI messages)
The SC bridges traffic
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏÏ ATM traffic
ÏÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ carrying
Traffic (including PNNI protocol)
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ SDH ports
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏÏÏÏ
Agent
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Agent
spare
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ main ATM MATRIX
ATM MATRIX ATM MATRIX towards the Spare
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ATM NMS massages
in charge of forwarding
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ The main ATM MATRIX is
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ EC SC
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ PQ2/EQC MATRIXN
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 1660SM
and dynamic data are aligned
NMS and PNNI), their static
the same messages (from
Since both the agents receive
NMS



[5] MPLS (PR_EA) ports protection

(see Figure 191. on page 332)

The MPLS boards (PR_EA MATRIX 4xETHERNET, PR_EA MATRIX 1xGIGABIT ETHERNET) can be

protected in 1+1 equipment protection scheme (EPS) against board failure.
The 1+1 EPS cannot be applied to the local interfaces (4xethernet, gigabit ethernet). In case of failure the
traffic carried by the ethernet local ports will be lost.

In this configuration when the working PR_EA Matrix...board fails the spare becomes active and the
indirect interfaces are rerouted to it.
The traffic from the ethernet local interface is lost.

Only one protection group 1+1 not revertive can be created, depending on the equipment configuration.

The spare card position can be assigned in a flexible way; no restrictions for position of main and spare
PR_EA boards are present.

The 1+1 EPS protection scheme of PR_EA boards is the same of ATM boards one.

The PR_EA EPS is managed by SDH EC, SC, Platform and PR_EA EC. In outline the management can
be divided in:

• SDH side Management: involving SDH EC, SC and Platform, it mainly applies to the Equipment
Domain of the PR_EA... board.
In particular:

– SDH EC: management of Equipment Protection Groups and interface towards the SDH
Network Management System (e. g. creation of Protection Schemes, operator
commands, autoswitch notifications)

– SC/ Platform: management of HW

• MPLS side Management: involving PR_EA... EC, it mainly applies to the MPLS Transmission
Domain of the PR_EA... board.

Figure 192. on page 333 represents the messages exchanged between the EC (on the PQ2/EQC board)
and the PR_EA Matrix... boards in protection group.
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1660SM

EXAMPLE #1

SERVICE
CONGI B
CONGI A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
ÔÔÔ
ÔÔÔ 1
PR_EA
MATRIX 25 24

ÁÁÁÁÑÁÁÁÁÁÔÔÔ
ÁÁÁÑÁÁÁÁÁÔÔÔ
ÁÑÑ ÁÁÁÁ Ô ÔÔÔ
Spare
Main

ÁÁÑÑ ÁÁÁÁ Ô

MATRIX B (spare)
MATRIX A (main)

PQ2/EQC

PR_EA MATRIX
PR_EA MATRIX

ÁÁÁÑÑ ÁÁÁÁ Ô
Á
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

1660SM

EXAMPLE #2
SERVICE
CONGI B
CONGI A


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
ÔÔÔ
ÔÔÔ 1 PR_EA
MATRIX
27 24

ÔÔ ÁÔ
ÔÔ ÁÁ Á Á Ñ
ÁÁÁÑ
ÁÁÑ
Spare

Main

ÔÔ ÁÔ
Ô ÁÁ Á Á Ñ
ÁÁ Á Á Ñ
Á ÁÑ
Á
MATRIX B (spare)
MATRIX A (main)
PQ2/EQC

ÔÔ
ÔÔ ÁÔ
Ô
Ô
Á Á ÁÑ
ÁÁÑ
Á
ÁÁ
Á
PR_EA MATRIX
PR_EA MATRIX

ÔÔ
ÔÔ ÁÔ
ÔÔ
ÁÔ
Ô ÁÁ Á Á Ñ
ÁÁÁÑ
ÁÁÑ
ÁÁ Á Á Ñ
Á ÁÑ
ÁÁÑ
ÔÔ
ÔÔ ÁÔ
Ô
ÁÔ
Ô ÁÁ Á Á Ñ
Á ÁÑ
Á
ÁÁ Á ÑÑ
Á
Á
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
ÔÔ Ô
Á Á
ÁÁ
Á
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 191. Examples of MPLS (PR_EA..) boards protection scheme

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1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 192. Messages exchanged between EC and ISA–PR_EA Matrix... boards in EPS group
PR_EA Matrix
towards both the
The SC bridges traffic
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏÏ MPLS traffic
ÏÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ carrying
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Traffic SDH ports
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏÏÏÏ
Agent
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Agent
spare
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ main PR_EA Matrix
PR_EA Matrix PR_EA Matrix towards the Spare
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ MPLS NMS messages
in charge of forwarding
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ The main PR_EA Matrix is
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ EC SC
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ PQ2/EQC MATRIXN
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 1660SM
are aligned.
their static and dinamic data
the same messages from NMS,
Since both the agents receive
NMS


[6] ISA ES–16 ports protection

ISA ES–16 board supports the EPS protection scheme as well as ISA ATM and ISA PR_EA boards.

The EPS protection scheme is 1+1, where the main and spare positions are assigned by

managementsystem in a flexible way (Note).

Note: The board main and the board spare have to be configured on throughput equivalent slot (i.e. both
not enhanced slots or both enhanced slots).

The characteristics of the protection scheme: the switching type is unidirectional (single–ended), the
operation type is Not Revertive (this means that WTR time is not applicable), the external commands are:
Manual Switch working, Manual Switch spare, and Clear. The command Lockout of spare is not provided,
as well Force switch working and Force Switch spare.

The access cards (Fast Ethernet and Gigabit Ethernet) are not protected by the EPS protection scheme,
this means if the board switches the Ethernet traffic carried by the local physical interfaces is lost, unless
a protection scheme is configured on the client side like dual attach protocol for the Gigabit Ethernet
interfaces.
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3.13.2 MS linear trail Protection (1+1 linear APS)

(See Figure 193. page 336 and Figure 194. page 336)

The MS Linear Trail Protection is a 1+1 linear APS (single ended/dual ended) line protection for STM–N

synchronous interfaces only.

Switching might be caused by line failure or hardware faulty on another system connected to the one being
considered.
The switching criteria are : Loss of Signal, Loss of frame, MS–AIS, Excessive BER and, with software
setting, Signal Degrade.

Note that each STM–1 electrical stream can be protected by an optical stream and vice versa.

This feature permits a 1+1 protection in a linear link, where a path signal is protected by another dedicated
path which carries the same signal. The protection can be set both in single and in dual ended mode.
In single ended mode the protection is accomplished by switching only the signal affected by the failure.
In dual ended mode the protection is accomplished by switching both the affected and the unaffected
signals.
The switching signalling is carried over the APS channel (K1 and K2 bytes), using the K–byte protocol.

Figure 193. page 336 shows an example of linear single ended 1+1 protection, and the case of signal
switching after an unidirectional failure on the main link (FERF=Far End Receive Failure, APS=Automatic
Protection Switching). Note: the FERF signal is actually called MS–RDI =Remote Defect Indication.

Figure 194. page 336 shows an example of linear dual ended 1+1 protection, and the case of signal
switching after an unidirectional failure on the main link.

Table 48. shows the MSP protection schemes for the STM–N port cards for the 1660 SM .

Table 48. MSP protection schemes

Protec-
Protected Entity tion Mode Features Notes
Status

Each STM–1 stream
STM–1 of 4xSTM–1 elect/opt port unidirectional/bi-
can be protected by an
not re-
re stan
directional stan-
1+1 electrical or optical
vertive dard (K1–K2 pro-
stream of the same port
STM–1 of 4xSTM–1 electrical port tocol)
or of another port.

STM–4 optical port unidirectional/bi-
not re-
re directional stan-
stan
1+1
vertive dard (K1–K2 pro-
STM–16 optical port tocol)

The standard Linear Multiplex Section 1+1 with K1–K2 protocol compliant whit ITU–T G.841
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Single ended 1+1

1

MAIN MAIN
2

1
SPARE SPARE
2
a) Normal conditions

APS SWITCH
1
MAIN MAIN
2
FERF

1
SPARE SPARE
2

b) Unidirectional failure

Figure 193. Linear 1+1 single ended protection

Dual ended 1+1

1
MAIN MAIN
2

1
SPARE SPARE
2


APS
1 SWITCH
MAIN MAIN
2
APS

1
SPARE SPARE
SWITCH 2

b) Unidirectional failure

Figure 194. Linear 1+1 dual ended protection
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3.13.3 MS linear trail Protection (1:N linear dual–ended APS)

1:N (N= 15 max.) linear protection without extra traffic.

One section is used as spare resource to protect one of the N main sections when in failure.

The implementation is compliant with the G841 7.1 clause MSP protocol compatible with the 1:N MSP
operation..

Only revertive mode is supported.

Fixed WTR is supported of 5 minutes .

When the protection section is not in use, null signal is indicated on both sent K1 and K2 bytes. The
operation switch is bi–directional, which means that both Tx side and Rx side switch will occur (using K1/K2
messages) in compliant with the G841 protocol operations.

In this mechanism the priority can be assigned to the main resource so that in case of double failure the
high priority traffic is restored.

This protection protects against transmission failures (LOS, LOF, MS_AIS) or section degradation
(MS_SD or MS_EXBER) or HW failure, which affects the traffic.

Protection takes place within 50ms.

Different physical interfaces can be mixed in the same MSP protection group: e.g. at STM–1 level the
feature is applicable at both electrical and optical ports.

Operator command are according G.841 and the following one are supported:

– Manual to protection: to switch from protected (main resource)) to protecting unit (Spare resource).
This command is Y if no failure is present on protecting unit;

– Force to protection:to switch from protected (main resource)) to protecting unit (Spare resource).
This command is Y if no failure is present on protecting unit;

– Lockout: the protection is locked, the traffic is managed by protected unit independently of its status,
in failure or not in failure;

– Clear: release command which is active;

– Clear WTR: supported;

– Exercise : not supported
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Dual ended 1:N without extratraffic

1 1

2 2
MAIN MAIN
1 1

2 #1 #1
2

1 1

2 2
MAIN MAIN
1 1

2 #N #N 2

SPARE SPARE

1 1

2 2
MAIN MAIN
1 1
#1 #1
2 2

Link failure

SWITCH SWITCH
1 1

2 2
MAIN MAIN
SWITCH 1 1 SWITCH

#N #N
2 2

SPARE SPARE
b) Failure conditions

Figure 195. MSP Linear 1:N Dual–Ended protection
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3.13.4 SNCP (Sub–Network Connection Protection)

Subnetwork Network Connection protection is a dedicated protection mechanism that can be used to

protect a path (e.g. that portion where two separate path segments are available) or the full end–to–end

path. It may be applied at any path layer in a layered network.
Two types of SNCP are possible:
• SNCP/I (Inherent monitoring) that switches on SSF criteria (AU–AIS and AU–LOP).
• SNCP/N (Non–intrusive monitoring) where POH is monitored by the POM enable before the
matrix. The switches criteria are SSF and one or more of ExBER, TIM, UNEQ, SD; in this case
the same selection must be made on each N.E. of the ring.
SNCP is employed on ring networks on which several equipments have been installed.
It can be also employed in Linear or Meshed network topology.
Two operating mode can be selected for single VC SNCP:

• revertive (the signal is switched back into the working channel, after recovery of the fault)
In the revertive operation the ”Wait time to restore” (WTR) is fixed at 5 min.
• not revertive
As illustrated in the example shown in Figure 196. on page 340 several equipment (numbered 1 to 5) are
ring–connected on a looped path.
Each of the equipment on the node is bidirectionally connected (Side A and Side B). One of the two
directions represent the main path (clockwise).The opposite direction will utilize a second fiber line for the
spare traffic (counter clockwise).
The SNCP automatic protection intervenes upon detecting path failure (SSF).
Each transmitting signal node is permanently connected (bridge) in the main traffic direction (clockwise)
and in the protected traffic direction(counter clockwise).
The Tx signal reaches destination through two different paths thus enabling the node receiving it to select
the best one (switch).
The switching decision can be taken at the NE level (automatic switch) or at the OS level (management
switch).
The example of Figure 196. on page 340 illustrates the connection between two signals (T1, between
nodes 2 and 5 and T2 between nodes 1 and 4 ) and relevant input/output nodes with associated
pass–through.
Figure 197. on page 341 illustrates two examples of failures and subsequent SNCP switching
mechanism.
A failure or degrade on the main path causes to switch over to the spare one .
When the receiving end switches no information is sent to the corresponding Tx side to activate the
switching operation at the remote end. (Single ended ”switching operation)
To manage switching the SNCP architecture utilizes the data inherent to the Path and not to the Line.
Switching is in fact activated by defective operations occurring at the VCn levels (AU–AIS, AU–LOP,
ExBER).
When the path is no longer available, an AIS signal is transmitted on the same path to activate protection.
In this manner SNCP can protect the paths following cable break–down or failures along the fiber and
nodes.
Cable break–down concerns all the fibers it contains hence it places traffic in both directions out–of–
service, while a failure concerns only one fiber.
The units are provided with a path switching circuit (bridge + switch).
1AA 00014 0004 (9007) A4 – ALICE 04.10

Its enabling depends on the equipment configuration.
With SNCP each working path has a dedicated protection path.

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Side B 3 Side A

T1, T2 Pass–through

2 Side A Side B 4
BRIDGE
T2

T1
T2 Pass–through T1 Pass–through
T1 Drop/Ins Prot. T2 Drop/Ins Prot.

SWITCH Side B Side A
COUNTER
CLOCKWISE
CLOCKWISE
1 Side A 5
Side B
T1

T2 T1 Pass–through T2 Pass–through
T2 Drop/Ins Prot. T1 Drop/Ins Prot.

Side B
Side A

NOTES:
On Craft Terminal, the following terminology is used:
Pass–Through= Bidirectional Connection
Drop/Ins Prot.= Bidirectonal Protected Connection

Figure 196. Typical ring network with SNCP
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Cable break 3 AU–AIS on T1,T2

Switch on spare path
2 4 SSF

T1
T2

MAIN SPARE
1 Switch on spare path
5 SSF

T2
T1

Case of cable break between nodes 2 and 3

3
2 4

T1
T2

SSF

MAIN SPARE
1
5

T2
T1

SSF

Unidirectional failure

Case of unidirectional failure between nodes 5 and 1
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 197. Failure examples in SNCP ring

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As the 1660SM equipment can manage up to 96 STM–1 equivalent streams, a max of 32 streams can
be SNCP protected.

In fact , to perform SNCP protection, a group of three ports must be used.

Table 49. on page 342 shows some examples of equipment configuration using SNCP protection. The
max. port configuration for each signal hierarchy level has been taken into account.

In the first column are reported the number and the type of stream to be protected .
The second column reports the number and type of card to be used to protect the source.
The third column reports the total number of VC that can be protected for each configuration.

Table 49. Example of SNCP protected groups

Protected stream Protecting
Source stream # of protected signals
stream

# of port acronym # of port acronym

8 4x STM–1 4 STM–16 32 H.O VC4

6 63x2 Mbit/s 2 STM–16 378 L.O VC12

6 63x2 Mbit/s 2 STM–4 378 L.O VC12
+
2 4xSTM–1

6 3x34/45 Mbit/s 2 STM–16 18 L.O VC3

6 3 x 34/45 Mbit/s 2 STM–4 18 L.O VC3
+
2 4xSTM–1

Figure 198. on page 343 graphically shows the SNCP protection of eight 4x STM–1 protected by 4
STM–16. It is note–worthy that the 4 STM–16 can be connected with two different rings.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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TO RING A

4
4 4
STM–16 STM–16
4 4
4 4
Slot Slot
4
25 + 26 28 + 29

4XSTM–1 4XSTM–1 4XSTM–1 4XSTM–1

Slot 24 Slot 27 Slot 30 Slot 31

TO RING B

4
4 4
STM–16 STM–16
4 4
4 4 Slot
Slot
34 + 35 4 37 +38

4XSTM–1 4XSTM–1 4XSTM–1 4XSTM–1

Slot 32 Slot 33 Slot 36 Slot 39
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 198. SNCP example

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3.13.5 Drop Continue

(See from Figure 199. on page 345 to Figure 203. on page 347)

The Drop and Continue architecture has been implemented in the network to improve traffic availability.

Drop and Continue is a way of protecting a path crossing a number of sub–networks, e.g., rings.

The sub–networks should be connected through at least two nodes (so realizing two independent
connections).

The equipment is configured as ”DROP and CONTINUE” on each interconnection node.

The subnetworks’ equipment implement the connection between two SNCP rings.

The resulting architecture affords protection against multiple failures (evenly distributed one per
subnetwork) tolerated without traffic loss (node failure or single cable cut).

The Drop and Continue feature improves traffic availability as compared with the simple ”end–to–end
SNCP”. More subnetworks are connected the further is availability increased.

The Drop and Continue features simultaneously realizes the following on one node:

• unidirectional pass–through

• protected drop

• insertion in one direction

The achievable configurations are:

• D/C–A INS–A (called “Normal” on Craft Terminal)

• D/C–A INS–B (called “Inverse” on Craft Terminal)

D/C stands for ”Drop and Continue”, the letter after it (A = line side” A” ) indicates the ”drop ” side (e.g.,
“A” means “A main side”, and consequently the spare side is the “B” one).
The end letter (INS–B or INS–A) indicates the insert side.

N.B. The letters “A” and “B” are not referred to a specific board or ports in a physical slot of
the subrack; “A” and “B” are used in the figures of this paragraph to identify a Line
direction.

The ”Unidirectional pass–through” is always in the direction opposite to that of the ”insert” side (e.g., when
”INS B” the pass–through is from B side to A side).

For further information refer to Figure 199. on page 345 which shows the D/C–A INS–A configuration
(called “Normal” on C.T.) and Figure 200. on page 345 which shows the D/C–A INS–B configuration
(called “Inverse” on C.T.).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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LINE PORT LINE PORT
SIDE A SIDE B
Input Output

Output Input

Symbol used on Craft Terminal

PORT

Input Output

Figure 199. Drop and Continue D/C A INS A (called “Normal” on C.T.)

LINE PORT LINE PORT
SIDE A SIDE B
Input Output

Output Input

Symbol used on Craft Terminal

PORT

Input Output

Figure 200. Drop and Continue D/C A INS B (called “Inverse” on C.T.)

The ”Drop and Continue” featuring two connected SNCP rings (with dual node connection) is indicated
in Figure 201. on page 346. It shows the connection of a path signal between the two nodes 1 and 8.

The relevant path signal is:

The relevant path signal is:
connected in Drop and Continue (D/C A – INS A) in nodes 3, 4, 6 and 10.
connected in pass–through in nodes 2, 5, 7, 9.
connected in drop/ins protection in nodes 1, 8.
NOTE – the following terminology is used on Craft Terminal:
pass–through = Bidirectional connection
drop/ins protection = Bidirectional Protected connection

When in normal condition, the unidirectional way of traffic from 1 to 8 is supposed to be 1 ! 2 ! 3 ! 6
! 7 ! 8.

After a failure on the 1st ring between nodes 2 and 3 (see Figure 202. on page 347), the link direction
is: 1 ! 5 ! 4 ! 3 ! 6 ! 7 ! 8, with a switch on node 3.
1AA 00014 0004 (9007) A4 – ALICE 04.10

After a second failure on the 2nd ring between nodes 6 and 7 (see Figure 203. on page 347) the selected
direction on the link is: 1 ! 5 ! 4 ! 10 ! 9 ! 8. The operative switch is on node 8 and the previous
pass–through between nodes 4 and 3 is no more used.

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1

2 SNCP ring 5
D/CA INSA D/CB INS B
A Port 1 Port 2 B A Port 1 Port 2 B

INS
INS
A 3 4 B

Port 3 Port 3

Port 3 Port 3

6 10
INS
INS B
A

A Port 1 Port 2 B A Port 1 Port 2 B

D/CA INSA D/CB INSB
7 SNCP ring 9

8

Figure 201. Drop and Continue
1AA 00014 0004 (9007) A4 – ALICE 04.10

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
03
7
2

7
2
switched

6
3

6
3

switched
1

8

1

8
SNCP ring

SNCP ring
SNCP ring
SNCP ring

4

10

4

10
Figure 202. Drop and Continue – 1st failure

Figure 203. Drop and Continue – 2nd failure
5

9

5

9

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3.13.6 Collapsed dual node ring interconnection

(See from Figure 204. on page 349 to Figure 206. on page 350 )

The “Collapsed dual node ring interconnection” is a way of protecting a path crossing a number of

sub–networks, e.g., rings.

The sub–networks should be connected through at least two nodes (so realizing two independent
connections).

Respect to the configuration shown in Figure 201. on page 346 ( Drop and Continue”), “Collapsed dual
node interconnection” allows a Hardware reduction, since an OMSN contains several ports and a path
signal can be connected in protected mode, from a generic pot to another one, on the same equipment.

The subnetworks’ equipment implement the SNCP connection.

The resulting architecture affords protection against multiple failures (evenly distributed one per
subnetwork) tolerated without traffic loss (node failure or single cable cut).

The “Collapsed dual node ring interconnection” featuring two connected rings (with dual connection) is
indicated in Figure 204. on page 349.

SNCP protection is enabled throughout the equipment. When in normal condition, the unidirectional way
of traffic from 1 to 8 is supposed to be 1 ! 2 ! 3 ! 6 ! 8.

After a failure on the 1st ring between nodes 2 and 3 (see Figure 205. on page 350), the link direction
is: 1 ! 5 ! 4 ! 3 ! 6 ! 8.

Pass–through is used between nodes 4 and 3, and switch on node 3.

After a second failure on the 2nd ring between nodes 3 and 6 (see Figure 206. on page 350) the selected
direction on the link is: 1 ! 5 ! 4 ! 7 ! 8.

The operative switch is on node 8 and the previous pass–through between nodes 4 and 3 is no more used.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
2

6

03
3

C
A

Port 3
Port 1

8
Port 2

Port 4
1

D
B
SNCP ring

SNCP ring
C
A

Port 3
Port 1

Figure 204. Collapsed dual node interconnection

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Port 4

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B

4

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5

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1

2 5
SNCP ring

switched 3 4

SNCP ring
6 7
8

Figure 205. Collapsed dual node interconnection – 1st failure

1

2 5
SNCP ring

3 4

SNCP ring
6 7
8

switched
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 206. Collapsed dual node interconnection – 2nd failure

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3.13.7 Collapsed single node ring interconnection

(See from Figure 207. on page 351 to Figure 209. on page 353)

The “Collapsed single node ring interconnection” is a way of protecting a path crossing a number of

sub–networks, e.g., rings.

Respect to the configuration shown in Figure 201. on page 346 ( Drop and Continue”), “Collapsed single
node interconnection” allows the best Hardware reduction; as a matter of fact four nodes are collapsed
in one node.

The protection operating mode is similar to that described for the “Collapsed dual node Interconnection”
(see para. 3.13.6 on page 348).

1

2 SNCP ring
4
Port 1 Port 2

3

Port 3 Port 4

5 7
SNCP ring

6
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 207. Collapsed single node ring interconnection

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
2

5

03
switched

Port 3
Port 1

6
1

SNCP ring

SNCP ring

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Figure 208. Collapsed single node ring interconnection –1st failure
Port 2

Port 4
3

7
4

352 / 706

1AA 00014 0004 (9007) A4 – ALICE 04.10

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2

5

03
switched
Port 3
Port 1

6
1

SNCP ring

SNCP ring

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Figure 209. Collapsed single node ring interconnection –2nd failure
Port 2

Port 4
3

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4

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3.13.8 MS–SPRING protection

(See from Figure 210. on page 355 to Figure 215. on page 358 )

The following protection MS–SPRING is supported :

– 2 fiber MS–SPRING at STM–16

– 2 fiber MS–SPRING at STM–64

The supported MS–SPRING is compliant to the ITU–T Rec. G.841

The MS–SPRING protection is realized in the MATRIX card.
A 2 fiber MS–SPRING (Multiple Section–Shared Protection Ring ) consist of a set of NEs each equipped
with a two bidirectional port , one for the clockwise and the other for the counter–clockwise. The
MS–SPRING is said ”two fiber” because each pair of adjacent NEs is linked by two fibers , one for each
direction.
The MS SPRING protection is an alternative with respect to SNCP. While MS SPRING allows the
connection at the same time on the clockwise and on the counterclockwise direction on the same AU4
that can be inserted and extracted in each span, on the contrary the SNCP connection engages the same
AU4 on both sides for the whole link.

N.B. In the following the 2F MS–SPRING at STM–16 will be explained; the same description can be
apllied to 2F MS–SPRING at STM–64 taking into account that 64 AU– 4 are available and that
the bandwidth is divided into two halves of equal capacity called respectively ”working” (AU4#
1 to AU4# 32) and ”protection” capacity (AU4#33 to AU4# 64).

2 fiber MS–SPRING at STM–16 level
The bandwidth of a 2F MS–SPRING is divided into two halves of equal capacity called respectively
”working” (AU4# 1 to AU4# 8) and ”protection” capacity (AU4#9 to AU4# 16). The AU4# 1 is protected
by AU4#9 up to AU4#8 that is protected by the AU4#16. The ”working ” capacity is used to carry the ”high
priority traffic”, while the ”protection” capacity can be used for ”low priority” traffic that is lost in case of
failure. See Figure 210. on page355.
In this release the ”low priority” connection are not managed.
The MS SPRING algorithm starts as a consequence of the following Section alarms:
• LOS, LOF, MS AIS, EXBER (B2), SIGNAL DEGRADE (B2)
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PORT

B A B A

A 1 2 3 B
6 5 4 A
B

A B A B

WORKING CHANNELS (AU4#1 TO AU4#8)
PORT
PROTECTION CHANNELS (AU4#9 TO AU4#16)

Figure 210. 2F MS SPRING Connection

APS in 2–fiber MS–SPRING

In case of fibre break the APS for 2F MS–SPRING uses a synchronized sequence of ”bridge” and
”switch” operations that modify the internal connections of the two NEs adjacent to the failure and
permits the ”high priority” traffic to be restored.

Only the NEs adjacent to the failure are interested to the ”switch” and ”bridge” functions while for all other
NEs the final configuration is a ”pass through” of all ”protection” (low priority) AU4s.

Figure 211. and Figure 212. on page 356 , Figure 213. and Figure 214. on page 357 highlight how the
connections are modified as a consequence of a ”bridge ” or a ”switch” operation.
The Bridge operation is performed on the Tx side while the Switch is performed on the Rx side.

• The ”Bridge” operation on the B side has the effect of routing the outgoing ”high priority” A
traffic to the outgoing ”protection” B capacity.
The Bridge function adds a connection on the opposite side and on the relevant AU protection.

• When a ”Switch” operation is working on the B side all the connections having an AU4
belonging to the A working capacity as a source, are replaced by connections having the
incoming B protection traffic as a source. The signals maintain the same end point connection.
The Switch function replaces the incoming flow with a protection one, coming form the opposite
side.

In the same way :

• The ”Bridge” operation on the A side has the effect of routing the outgoing ”high priority” B
traffic to the outgoing ”protection” A capacity.
The Bridge function adds a connection on the opposite side and on the relevant AU protection.

• When a ”Switch” operation is working on the A side all the connections having an AU4
belonging to the B working capacity as a source, are replaced by connections having the
incoming A protection traffic as a source. The signals maintain the same end point connection.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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A B A B

A B A B

protection
working

BEFORE AFTER

Figure 211. Effect of a BRIDGE “B side” operation

A B A B

A B A B

protection
working

BEFORE AFTER

Figure 212. Effect of a BRIDGE “A side” operation
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A B A B

A B A B

protection
BEFORE working AFTER

Figure 213. Effect of SWITCH “B side” operation

A B A B

A B A B

protection
BEFORE working AFTER

Figure 214. Effect of SWITCH “A side” operation
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Figure 215. on page 358 depicts the final effect of Bridge and Switch synchronized steps for traffic
restoration in a network with one fault.
They are carried out via a protocol that uses the K1 and K2 bytes .The failed span is replaced by the
protection traffic of the span not affected by the failure.

The K1 and K2 are exchanged between the Node that are adjacent to the failure, instead the other Nodes
put K1 and K2 in passthrough.

SWITCH BRIDGE
side A side A SWITCH
PROTECTED BRIDGE
SIGNAL side B
side B

B A B A

A 1 2 3 B

6 5 4
B A

(*) (*)

A B A B

WORKING CHANNELS

PROTECTION CHANNELS PROTECTED
SIGNAL
BRIDGE

SWITCH
(*) All protection AU4 are put in Pass–through in the 5th and 6th NEs

Figure 215. Line break recovering operations
1AA 00014 0004 (9007) A4 – ALICE 04.10

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An example of 2F MS–SPRING is reported in Figure 216. on page 360.

In the example a ring of four nodes is protected with 2F MS–SPRING

AU4–1 carries the traffic of the span : C–B, B–A, A–D, D–C

AU4–2 carries the traffic of the span D–B (pass–through in C)

AU4–9 protects AU4–1.

AU4–10 protects AU4–2.

After a failure in the section C–B, the following actions are performed on :

– node B : Streams access 1 and 2, previously drop–inserted on AU4–1 and AU4–2
“side A”, are switched respectively on AU4–9 and AU4– 10 “side B” .
In this way, C is reached through nodes A and D.

– node C: Stream access 1, previously drop–inserted on AU4.1 “side B”, is switched on
AU4–9 “side A”.
In this way, B is reached through nodes D and A.
Rx AU4–2 “side A”, previously in pass–through on Tx AU4–2 “side B”, is looped
on Tx AU4–10 “side A”. In this way, B is reached through nodes D–A (signal
transmitted D to B).
Rx AU4–2 “side B” is no more received.
So, Rx AU4–10 “side A” is looped on the Tx AU4–2 “side A”.
In this way, the signal transmitted by node B follows the path :
A–D– C and here is looped to reaches node D again.

– nodes A and D do not switch

We can obtain from the example that is possible bandwidth re–used for some traffic patterns (AU4–9
protects four connection on AU4–1) having the same protection for some several connections (shared
protection).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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A
D A . AU4 1 A B : AU4 1

AU4.9–Prot. AU4.1

AU4.10 Prot. AU4.2

D B

C
D C : AU4 1 C B : AU4 1

D B : AU4 2

A

side B
D B
side A

side A side B

C

C B

side A side B side A side B
AU4 AU4 AU4 AU4
1 1 1 1
2 2 2 2
9 9 9 9
10 10 10 10

1 1 1 1
2 2 2 2
9 9 9 9
10 10 10 10

1 1 2
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 216. 2F MS–SPRING example of operation

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SQUELCHING FUNCTION

The Squelching function is activated when a node that carries Drop/Insert streams, remains isolated
because of a double failure.

In this case to avoid misconnections on the AU4 involved in MS SPRING protection, an AIS signal will be
inserted on Low Priority streams transmitted from the nodes adjacent to the isolated one. See Figure 217.

Before Node 2 isolation because of the double failure , the following connections were active using the
AU4#1

– Stream between Port 3 and Port 1

– Stream between Port 2 and Port 4

After a second failure, the Nodes adjacent to the isolated Node 2 send AIS on the Low Priority traffic
(AU4#9) by means of the Squelching function thus avoiding the misconnection between Port 3 and Port
4.

If the Squelch function were not active, the MS SPRING algorithm would activate the Bridge and Switch
functions on the nodes adjacent to Node 2 thus misconnecting Port 3 and Port 4 using AU4#9 as
protection. In virtue of squelching function the nodes adjacent to isolated Node 2 send AIS on Low Priority
AU4#9 avoiding in this way the misconnection between Port 3 and Port 4 in this case.
After the failure has been removed, a similar reverse sequence of operations on the NEs adjacent to the
recovered span will be activated. The reverse procedure can start after a step programmable WTR.

PORT 3 PORT 1 PORT 2 PORT 4

AU4 #1 AU4 #1 AU4 #1 AU4 #1
B A B A
BRIDGE SWITCH
side A side B

1 SWITCH
2 3
side A BRIDGE
side B

(SF/SD) (SF/SD) B
A
AIS ON AIS ON
AU4 # 9 AU4# 9
5 4
B
A
AIS ON AIS ON AIS ON
AU4 # 9 AU4 # 9 AU4 # 9
PASS–THROUGH PASS–THROUGH
6 PASS–THROUGH

A B A B

WORKING CHANNELS

PROTECTION CHANNELS

Figure 217. Squelching on isolated Node connection
1AA 00014 0004 (9007) A4 – ALICE 04.10

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MS – SPRING Interworking

When a 2f MS–SPRING is interconnected with another ring (either SNCP/I or MS–SPRING), the
interconnection of the two is performed by connecting two nodes per ring with HVC connections, as shown

in Figure 218. on page362.

Each VC4 that has to cross the ring boundary (only HVC level ring interconnections are considered here)
must be output by two nodes, one of which, the Primary Service Node (PSN) drops it and continues to the
Secondary Service Node (SSN). In the opposite direction, the SSN inserts a copy of the VC4 into the ring
and the PSN selects by means the Primary Node Service Selector function, between the VC4 coming
from the SSN and the VC4 that can be locally inserted by means an STM–1 Tributary. The selection is
made on the Path–AIS basis (AU–AIS).

The protection mechanism works on the hypothesis that the other ring selects one of the two versions
of the incoming VC4 and transmits two identical copies of the VC4 towards the PSN and the SSN ( this
is guaranteed if the other ring is an MS–SPRING or an SNCP ring).

Note that the PSN and the SSN need not to be adjacent and need not to be the same for all of the VC4
that cross the ring boundary: i.e. each crossing VC4 has two associated nodes that act as PSN and SSN.

2F MS – SPRING

side A
side B
side B side A
Secondary
SS Service
Node
Primary
Service
side A side B side A side B
Node

SNCP or MS–SPRING

SS = Service Selector
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 218. MS SPRING Drop and Continue, Insert Continues (protected)

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3.14 Synchronizing sub–system


The Equipment synchronization function is performed by the MATRIXE card.

Through the SETS (Synchronous Equipment Timing Source ) implemented on the matrix, the
synchronization signals are distributed to the equipment ports.

The working modes:

• locked
• holdover
• free running

are compliant to the ITU–T G.810, G.812 and G.813 Recommendations.

A PLL is present that maintains locked the System clock to the one selected as a input in case the
equipment works in the ”locked” mode.

An oscillator at 10Mhz high stability is present to guarantees an holdover or free running working mode
compliant to the ITU–T Recs.

Synchronization sources

The MATRIXE unit can select its reference signal among one of the following clocks :

• T1 : 2.048 Mhz clock extracted from the STM–N signals
• T2 : 2.048 Mhz clock extracted from the PDH signals coming from the 2 Mbit/s plesiochronous
ports
The maximum number of T1 + T2 reference clocks is 6.

• T3 or T6 (software selectable) : respectively a 2.048 Mhz clock or 2.048 Mbit/s signal coming
from an external synchronization source ( from SERVICE card that inserts the SSM algorithm)
The T3/T6 clocks are two ( i.e. T3a, T3b or T6a, T6b).

Automatic selection of one of these sources is achieved using quality (SSM algorithm) or priority criteria.
Switching between the references also depend on the alarm condition detected on the signals.

Generated Clocks

The MATRIXE card implements also the SETG (Synchronous Equipment Timing Generation) function.
It generates the following clocks :

• T0 : it is a system clock at 622 Mhz derived from a local oscillator. It can be locked to one of the
T1, T2 or T3/T6 clock references .
The clock at 622 Mhz is sent to all the port cards.
In case of ”free running working mode” , it can be locked to a clock at 10 Mhz generated by
another high stability local oscillator ( ± 4.6 ppm accuracy); the unit operate in this mode when
no valid synchronism signals are present nor Hold–over reference values are stored.

With regard to ”Hold–over”, the unit hold the last valid reference with a max. shift of 1 ppm/day
(or 0.37 ppm/day) unit. This operating mode is associated with thee loss of references selected
1AA 00014 0004 (9007) A4 – ALICE 04.10

by the operator.
The reference quality level utilized to generate T0 is inserted on the SSMB of the STM–N signals
outputting the equipment.

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• T4 or T5: the first is a synchronizing clock at 2.048 Mhz , the second is a 2 Mbit/s synchronizing
signal ; the selection between the two signals is made via software and the result is sent towards
the external. T4 or T5 is obtained from a digital PLL that can be locked to any of the T1/T2
references and can be squelched. This clock is sent to the SERVICE card that inserts the SSM

algorithm and generates the clock standard format to be output from the system.

The T4/T5 clocks are two (i.e. T4a, T4b or T5a, T5b).

The ”don’t use” criteria is sent to the ”NEi clock” which had supplied the synch. reference to obtain the
T0. This operation is carry out to prevent the ”timing reference” synchronizing the supplier NEi (timing
loop).

Other synchronizing signals generated by the MATRIXE

The MATRIXE generates the following synchronisms for internal use :
• CK38Mhz : it is derived from the system clock and it is distributed to the ports and to the
SERVICE and EQUICOE cards. Its frequence is 38 MHz
• MFSY : it is the multiframe synchronism at 500 Hz, obtained from the ck 38MHz. It is distributed
to all the ports and to SERVICE and PQ2/EQC cards.
• SY1S : it is a one second synchronism used on the MATRIXE for the Performance Monitoring
calculation.
As the MATRIXE is redundant, the synchronization function is redundant as well. The synchronization
system guarantees the Hitless switch because the two MATRIXE works in a Master–Slave mode. In order
to maintain locked and in phase the two G.A. some signal are exchange on the SYNC BUS.
T0 T4a, T4b/ T5a, T5b T0 T4a, T4b/ T5a, T5b
ck622 MHz ck2Mhz/ 2Mbit/s ck622 MHz ck2Mhz/ 2Mbit/s
(to the ports) (to SERVICE) (to the ports) (to SERVICE)

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
MATRIXE (a)
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
MATRIXE (b)
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ VCXO
622Mhz
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ VCXO
622Mhz
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ phase digital
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ phase digital
comp. PLL comp. PLL
SETG SYNC BUS SETG
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ SETS
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ SETS
OCXO OCXO
G.A.
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 10Mhz ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
10Mhz
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ G.A.

sy1s sy1s
1AA 00014 0004 (9007) A4 – ALICE 04.10

Ck38 mfsy T3a , T3b/ T6a, T6b T1,T2 mfsy Ck38
ck2Mhz/ 2Mbit/s ck2Mhz
(to the ports) (to the ports)
(from SERVICE) (from the ports)

Figure 219. Synchronization function : block diagram

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3.15 Auxiliary and DCC sub–system

(See Figure 220. on page366)

The SDH standard offers a considerable quantity of service channels in the Section Overhead bytes

(SOH) and Path Overhead bytes (POH) of the Synchronous frame. These bytes are used for alignment,
parity check, network management operations, performance monitoring.

Part of them are also used for user data and speech channels and are interface toward the STM–N port
through SERVICE unit.

SERVICE unit realize the analog speech by–pass between two ports and can also establish a connection
with external telephone set.

The SERVICE unit can be used as required:

– to externally access the service interface

– to connect the external access point to the SOH and POH bytes of the units (termination)

– to allows SOH and POH bytes to pass through the various units.

The external access point of the unit are:

– one local operator’s set for speech connection useful for service communication in the network.
The following types of connections are possible:
• between two station (selective call)
• among three stations (multi–selective call)
• omnibus call
For more details see para 4.53 on page 577.

– Engineering order wire extensions

– four V11 data channels

– four RS232 data channels

– four 64 Kbit/s G.703 data channels

– two 2 Mbit/s G.703 data channel

On the SERVICE units a not blocking matrix is present to perform SOH and POH bytes cross connections
The matrix cross connect the RS232, V11, and G.703 data channels.

The matrix also receives:

– DCC bidirectional link from PQ2/EQC (DCC–A) and STM–N port.

– AUX bidirectional link from STM ports
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STM–N port STM–N port STM–N port

G.A. G.A. G.A.
DCC/AUX DCC/AUX DCC/AUX
EXTRACTION EXTRACTION EXTRACTION

QAUX

QAUX DCC BUS A
DCC BUS A

PQ2/EQC SERVICE

DCC
DCC A
MANAGEMENT

INTERFACES

Engineering Order Wire Extension

2 x 2 Mbit/s G.703

4 x V11

4 x RS232

4 X G.703
64 Kbit/s

Figure 220. AUX and DCC management
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3.16 Power supply sub–system


The power architecture for 1660SM equipment is distributed : the two CONGI ( called “a” and “b” in

Figure 221. on page 369) provide the +Batt and –Batt to the other cards by selecting the highest voltage
supplied by the two station batteries.

One or more DC/DC converter may be present on the cards to generate the voltages required to feed
the electronic circuits present on the board itself : ASICS, FPGA, optical modules and so on .

In order to avoid EMI problems, all the DC/DC converters are synchronized with a synchronization clock
at 288 MHz derived from the on board G.A.

The major advantages of the distributed architecture are:

– the skill to generate , through the secondary converters, a number of independent, different end –use
voltage or functions from the high voltage distribution bus (usually 48V)

– the faults will affect only the board associated to the damaged converter in case of overvoltages or
short circuits.

– the skill to contain all that influential signals that do not cause system malfunction, but which may
cause problem with system performance, such as conducted and radiated noises, caused by
high–frequency clock or rapid transitions, by adding on board EMI filter.

The power supply sub–system has been subdivided in two levels:

– Input Power Stage

– Distributed Power Stage

INPUT POWER STAGE

Figure 221. on page 369 shows the equipment input power stage housed on the two CONGI cards.
It can be subdivided in three main block:

a) Main power block

It is used to select the input voltage of the system and to supply a surge protection.
It contains an EMI filter to permit the equipment to be reliable in presence of external EMI
interferences and to limit the internally generated EMI.
The voltages coming from the two station batteries, are applied to both CONGI boards by means
of the power connector located on the unit front panel ( ex. +BATT A –BATT A to CONGI “a” and
+BATT B –BATT B to CONGI “b” ).
The + Batt can be connected to a mechanical ground through a strap setting.

CONGI “a” and CONGI “b” cards can therefore select which of the two station batteries provides the
highest supply.
The selected voltages are ORed and sent to the equipment cards (+BATT and –BATT).
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b) Protection Circuit

The protection circuits are present in the CONGI cards and in all the boards where a DC/DC
converter is required i.e. input stage and distributed power stages . It is an interface between +BATT

– BATT and the DC/DC converter.

It provides the following functions:

• It insulated the DC/DC converter in case of input short circuit . Fuses are fitted in order to prevent
a failed unit from shortening the input bus. In fact a input short circuit failure can cause severe
fluctuations on the input power of the other DC/DC converters.

• It implements a start–up and an inrush current limiting system in order to provide controlled
charge–up for the input hold–up capacitor and therefore it prevents a current surge at the
module input when the board is plugged in.

• It insulated the DC/DC converter in case of input voltage lower than 33 V.

c) DC/DC 3.3 V block

A DC/DC converter generates a +3.3 voltage used to power the ”RIBUS I/F” interface.
For the function performed by the ”RIBUS I/F” interface see paragraph 3.17 Remote Inventory
Sub–system on page 370.

DISTRIBUTED POWER STAGE

All the boards receive the +BATT –BATT voltages generated by the input stage and the +3.3 V voltage
to power the ”RIBUS I/F” interface if it is present on the card.

A DC/DC converter generates the +3.3 or 5.2 voltages required to power the card.
As mentioned before the DC/DC converter is preceded by the protection circuit.
A divider circuit provides the frequency necessary to synchronize the DC/DC converter.
On the board can also be present step–down converters to generate other voltages when necessary.
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CONGI
+ Batt_A ”a”
MAIN POWER
– Batt_A BLOCK

+3.3 V + Batt

DC/DC PROTECTION
CIRCUIT
3.3 V BLOCK – Batt

Input power Stage

CONGI
+ Batt_B ”b” + Batt
MAIN POWER Distributed power stage
– Batt_B BLOCK – Batt
BOARD 1
+3.3 V DC/DC
PROTECTION Converter
DC/DC

– input +

– output +
CIRCUIT PROTECTION + 3.3 V
3.3 V BLOCK
CIRCUIT

ACCESS CARD
BOARD CIRCUIT
Input power Stage
Synch

SELECTOR
+ DC/DC
DIVISOR
Converter
Sync

– input +

– output +
G.A. +/– 5.2 V

RIBUS
I/F Synch

BOARD2
DC/DC
Converter

– input +

– output +
+ 3.3 V
PROTECTION
CIRCUIT

BOARD CIRCUIT

ACCESS CARD
or
Synch +/– 5.2 V

SELECTOR
+
DIVISOR
Sync
G.A.

RIBUS
I/F

BOARDn
DC/DC
Converter
– input +

– output +

+ 3.3 V
PROTECTION
CIRCUIT
BOARD CIRCUIT

ACCESS CARD
or
Synch +/– 5.2 V

SELECTOR
+
DIVISOR
Sync
G.A.

RIBUS
I/F

Figure 221. 1660SM –Input power stage and distributed power supply
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3.17 Remote inventory Sub–system

(See Figure 222. on page 370).

The Remote Inventory functions permits the operator to retrieve information about any card or module

present on the equipment.
The available information is: construction date, code number, maker name, Card–type, etc. (see details
in the Operator Handbook).
The Remote Inventory function is present in all the cards and modules or intra–card modules.

The relevant data are transported by a serial link (named RIBUS in the figure) that connects all cards or
modules of the equipment.
The block ”RIBUS–I/F” of figure implements the interface of the serial link with the remote inventory device
(named RI in the figure). Further it manages the slot identifier (ID) and the card type (CType). The CType
information is contained on the RI device.
The RI can be also present on some sub–modules assembled on the board (such as optical–electrical
modules, micro–controllers and so on).
This block can also manage the visual indications of the board (LEDs) and some I/O parallel
commands/contacts/alarms that can eventually be transferred by means of the RIBUS link.

RIBUS
RI I/F

SHELF RIBUS
CONTROLLER

MATRIX

Generic Board (or Module)
Board
X Indications

RIBUS Board
EQUIPMENT I/F
CONTROLLER RI
ID
.
.
.

Board I/O Intracard
RIBUS Module
RI I/F
PQ2/EQC Module
RI

.
.
.

Figure 222. Remote Inventory sub–system
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3.18 Frames Structure

The SDH Standard offers a considerable quantity of service channels in the Section OverHead (SOH)
bytes of the frame. These bytes are used for section maintenance (frame alignment, parity check, network

management operations, auxiliary communications, etc.).

For reader’s convenience, the structures of some SDH frames involved in the equipment are reported in
the following pages. Reference specifications: ITU–T G.707

139 264
x1 C-4 kbit/s

xN x1
ÉÉÉÑÑÑÑÑÑ
STM-N
ÉÉÉÑÑÑÑÑÑ AUG AU-4 .....
VC-4
x3

ÑÑÑÑÑÑ x1
ÉÉÉÉ TU-3 ......
VC-3 C-3
44736
kb/s
ÑÑÑÑ
ÑÑÑÑ TUG-3
x7
ÉÉÉÉ
ÉÉÉÉ 34368
kb/s
x3

x3

AU-3 ......
VC-3
ÉÉÉ ÑÑÑ
TUG-2
ÉÉÉ ÑÑÑ TU-12 ......VC-12 C-12 2048
kbit/s

ÍÍ
ÍÍ Pointer processing

Multiplexing
..... Aligning
Mapping
AU3/TU3 CONVERSION

Figure 223. 1660SM: SDH multiplexing structure and AU–3/TU–3 conversion
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8 bit
VC–12

POH of VC–12 V5 V5 = THE BYTE PROVIDES THE FUNCTIONS OF ERROR
CHECKING, SIGNAL LABEL AND PATH STATUS OF THE VC–12
G

W G = rrrrrrrr (r = BIT INTERVAL FOR FIXED JUSTIFICATION)

W = iiiiiiii (i = 2.048 Mbit/s TRIBUTARY BIT)
125 us W 32 byte J2 =USED TO TRANSMIT REPETITIVELY A LOW ORDER PATH
ACCESS POINT IDENTIFIER SO THAT A PATH RECEIVING
TERMINAL CAN VERIFY ITS CONTINUED CONNECTION
W
TO THE INTENDED TRANSMITTER. A 16–BYTE FRAME IS
DEFINED FOR THE TRANSMISSION OF PATH ACCESS
G POINT IDENTIFIERS.
J2
C1, C2 = JUSTIFICATION SIGNALLING BIT
C1 C2o o o r r
W o = OVERHEAD BITS

S1, S2 = NEGATIVE AND POSITIVE JUSTIFICATION
125 us W 32 byte
OPPORTUNITY REFERRED TO SIGNALLINGS C1 AND C2
N2 =THIS BYTE IS ALLOCATED TO PROVIDE A TANDEM
CONNECTION MONITORING (TCM) FUNCTION
W
K4 =THIS BYTE ARE ALLOCATED FOR APS SIGNALLING
G FOR PROTECTION AT LOWER ORDER PATH LEVEL
N2
C1 C2o o o r r
W

125 us W 32 byte
V5 STRUCTURE:
b1 b2 b3 b4 b5 b6 b7 b8
W
G R R
SIGNAL R
BIP–2 E F D
K4 I I LABEL
I
C1 C2r r r r S1
S2 i i i i i i i
W N2 STRUCTURE:

125 us b1 b2 b3 b4 b5 b6 b7 b8
W 31 bytes TC–APId,
Incoming
BIP–2 1 AIS TC–REI OEI TC–RDI,
ODI,
reserved
W
G

POH STRUCTURE (V5) : N2 STRUCTURE:
– 2 BITS TO ESTIMATE THE BER THROUGH THE BIP–2 – 2 BITS ARE USED AS AN EVEN BIP–2 FOR THE
ENCODING PROCEDURE PERFORMED ON THE PREVIOUS TANDEM CONNECTION
VIRTUAL CONTAINER (THE FIRST AND SECOND BITS OF – BIT 3 IS FIXED TO 1
BIP–2 CONSTITUTE THE PARITY BIT OF ODD AND EVEN
ORDER BITS) – BIT 4 OPERATES AS AN ”INCOMING AIS” INDICATOR
– 1 BIT TO INDICATE (TO THE REMOTE TERMINAL) THE – BIT 5 OPERATES AS THE TC–REI OF THE TANDEM
RESULT OF THE BER ESTIMATION DETECTED ON THE CONNECTION TO INDICATE ERRORED BLOCKS
OPPOSITE DIRECTION: VALUES 0 AND 1 OF BIT FEBE CAUSED WITHIN THE TANDEM CONNECTION
(FAR END BLOCK ERROR), (actually named REI) – BIT 6 OPERATES AS THE OEI (OUTGOING ERROR
RESPECTIVELY INDICATE ABSENCE OF VIOLATION AND INDICATING) TO INDICATE ERRORED BLOCKS OF
PRESENCE OF ONE OR TWO VIOLATIONS OF THE THE EGRESSING VC–n
PARITY LIMITS ESTABLISHED BY BIP–2
– BIT 7 AND 8 OPERATE IN A 76 MULTIFRAME AS:
– 1 BIT TO CHECK THE PATH TRACE THROUGH AN – THE ACCESS POINT IDENTIFIER OF THE TANDEM
APPROPRIATE PROTOCOL CONNECTION (TC–APId);
(RFI: path Remote Failure Inication) – THE TC–RDI, INDICATING TO THE FAR END THAT
– 3 BITS PRESETTABLE FOR THE SIGNAL LABEL DEFECT HAVE BEEEN DETECTED WITHIN THE
TANDEM CONNECTION AT THE NEAR END
– 1 BIT FOR THE FERF (FAR END RECEIVE FAILURE) TANDEM CONNECTION SINK;
ALARM INDICATION (actual RDI) – THE ODI, INDICATING TO THE FAR END THAT
TU–AIS HAS BEEN INSERTED AT THE TC–sink
INTO THE EGRESSING TU–n DUE TO DEFECT
BEFORE OR WITHIN THE TANDEM CONNECTION;
1AA 00014 0004 (9007) A4 – ALICE 04.10

– RESERVED CAPACITY (FOR FUTURE USE)

Figure 224. VC–12 Structure (asynchronous mapping of 2048 Kbit/s)

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TU–12
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
V1

ÉÉÉÉÉ
125 us ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ 35 byts

ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
V2
0
1
125 us

NEGATIVE
34 JUSTIFICATION OPPORTUNITY
V3
35 POSITIVE
JUSTIFICATION OPPORTUNITY

125 us

69
V4
70

125 us

104
ÇÇÇÇÇ
ÇÇÇÇ
V1 ÇÇ BYTES BELONGING TO
ÉÉ ÇÇÇÇ
Ç
105 THE PREVIOUS TU–12

125 us
ÇÇ
ÇÇ BYTES BELONGING TO
THE SUBSEQUENT TU–12

139
ÇÇÇÇÇ
ÇÇÇÇ
V2
ÇÇ
ÇÇÇÇ
Ç
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 225. TU–12 Structure

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85 bytes

J1
B3

C2

G1
VC–3
9 rows F2
C–3
H4
F3
K3
N1
POH OF VC–3

POH STRUCTURE:

• J1 (path trace) utilized to transmit in a cyclic mode a 64–octet configuration in order to check
the connection continuity.
• B3 resulting from the BIP–8 performed on the previous VC–3, before the scrambler. PM and
ex–BER supported at VC3 terminations.
• C2 (signal label) = the configurations are utilized to indicate if VC–3 is equipped or not, or the
payload structure. SLM and UNEQ supported at VC3 – TTP.
• G1 (path status) utilized to transmit information on the link status to the remote terminal. PM
near end / far end supported at LVC terminations. It contains:
– four bits for the REI (Remote Error Indication) (ex FEBE=Far End Block Error) indication,
where the decimal numbers 0–8 indicate the number of violations of BIP–8 (the illegal
values 9 to 15 indicate absence of errors);
– one bit for the RDI (Remote Defect Indication), (ex FERF= Far End Receiving Failure) and
other three digits not utilized.
• F2, F3: bytes utilized for the transportation of two user data channels via the AUX connections.
• H4: position indicator of inner lower order payloads, as a multiframe indicator.
• K3: for APS signalling (Automatic Protection Switching).
• N1: Network Operator byte, for Tandem Connection Monitoring (TCM).

Figure 226. VC–3 structure

86 bytes

H1
H2
H3
S VC–3 TU – 3
9 rows T PAYLOAD
U
F
F
I
N
G

• H1,H2,H3: TU–3 Pointer

Figure 227. TU–3 structure
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261 bytes

J1

B3
C2
G1 C–4
9 rows F2 or VC–4
H4 VC4 PAYLOAD
F3
K3
N1

POH of VC–4

J1 (path trace) utilized to transmit in a cyclic mode a 64–octet configuration in order to check the
connection continuity.

B3 resulting from the BIP–8 performed on the previous VC–4, before the scrambler.

C2 (signal label) the configurations are utilized to indicate if VC–4 is equipped or not or the
payload structure.

G1 (path status) utilized to transmit information on the link status to the remote terminal.
– four bits contain the FEBE Tx (Far End Block Error) signal, where the decimal numbers
0–8 indicate the number of violations of BIP–8 (the illegal values 9 to 15 indicate absence
of errors);
– one bit to carry the FERF Tx alarm signal and three unused bits.

F2 (path user channel) utilized to transmit and cross connect a data channel received from the
SERVICE unit.

H4 (position indicator) multiframe indicator (utilized for the payloads structured through TUG)
which indicates the subframe of each multiframe.

F3 (path user channel) utilized to transmit and cross connect a data channel received from the
SERVICE.

K3 Higher Order Protection (HOP), not operative in current release.

N1 network operator byte (for Tandem Connection Protocol)

Figure 228. VC–4 Structure and POH byte contents
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9 COLUMNS (Bytes) 261 COLUMNS (bytes)

A1 A1 A1 A2 A2 A2 J0

RSOH B1 E1 F1

D1 D2 D3

AU pointer(s) STM–1
PAYLOAD

9 rows
B2 B2 B2 K1 K2

D4 D5 D6

MSOH D7 D8 D9

D10 D11 D12

S1 M1 E2

A1 – A2 The six octets of type A1=11110110 and A2=00101000 constitute the alignment word.
J0 Regenerator Section Trace.
B1 This octet resulting from the BIP–8 procedure performed on the previous frame at the
scrambler output, is inserted into the current frame before scrambling; it is utilized to
estimate the BER in the regenerator section.
B2 These three octets, resulting from the BIP–Nx24 encoding performed on the previous
frame without the first three rows of SOH, are inserted into the current frame before
scrambling; they are not estimated again in the repeaters because they are utilized to
estimate the BER between multiplexer.
E1 – E2 (orderwire, EOW) Are utilized for service telephone communication between regenerators
(E1) and between muldex and muldex (E2).
D1 ÷ D3 Are utilized as a 192 Kbit/s channel for data communication (DCC=Data Communication
Channel) between regenerates in the TMN network.
D4 ÷ D12 Are utilized as a 576 Kbit/s channel for data communication (DCC) between multiplexers
in the TMN network.
F1 (user channel) Is utilized to transmits a data channel received from SERVICE unit (for
service and maintenance).
K1 – K2 Are utilized for APS indications (Automatic Protection Switching); the last three K2 bits
(b6÷b8) are used like MS–RDI multiplex section remote indication for FERF and AIS
alarms between the multiplexers.
S1 Indicates synchronization status (b5÷b8) of sync. path status.
M1 Indicates MS–REI Far–end Block Errors (FEBE) for the multiplex section.

Notes:
– bytes marked with X are reserved for national use.
– all unmarked bytes are reserved for future international standardization (for media
dependent, additional national use and other purposes).
– bytes marked with ∆ is a Media Dependent byte: not operative.
– bytes marked with • are not scrambled (like the whole first row).
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 229. STM–1 structure and SOH byte contents

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36 bytes

A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 J0 Z0 Z0 Z0

RSOH

B1 E1 F1

D1 D2 D3
9 rows

AU pointer(s)

B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 K1 K2

MSOH
D4 D5 D6

D7 D8 D9

D10 D11 D12

S1 M1 E2

1 261 1 261 1 261 1 261
1 9 1 9 1 9 1 9
#1 #2 #3 #4

AUG AUG AUG AUG

RSOH 1234,1234,.....
1234,1234,1....

MSOH
....1234,1234.

4 x 261
4x9
STM–4

A1 – A2 Alignment word A1=11110110, A2=00101000. Utilizes all slots of the four STM–1.
Z0 (Spare) These bytes are reserved for future international standardization.
B1 BIP–8 calculation result on the previous frame (after scrambling).
Utilized to assess error rate between regenerators. Uses slot of first STM–1.
E1 For EOW operations between regenerators. Uses slot of first STM–1.
F1 Available for the user (data from SERVICE unit). Uses slot of first STM–1.
D1 ÷ D3 Are used for 192 Kbit/s channel for DCC on TMN network. Uses slot of first STM–1.
B2 Result of BIP–Nx24 calculation on previous frame exempt of three RSOH rows.
Used to assess error rate between multiplexers. Uses all slots.
K1 – K2 For 1+1 MS Trail Linear Protection indications and FERF, AIS alarms.
Uses slot of first STM–1.
S1 Indicates synchronization status (b5÷b8) of sync. path status. Uses slot of first STM–1.
E2 For EOW operations between multiplexers. Uses slot of first STM–1.
M1 Indicates section FEBE (STM4). Uses slot of third STM–1.

Notes:
– bytes marked with S are not scrambled (like the whole first row).
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144 bytes

A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 J0 Z0

RSOH
B1 E1 F1

D1 D2 D3

AU pointer(s)
9 rows

B2 B2 B2 B2 B2 B2 K1 K2
D4 D5 D6

MSOH
D7 D8 D9
D10 D11 D12
S1 E2

M1

1 261 1 261 1 261 1 261

1 9 1 9 1 9 1 9
#1 #2 #3 #16

AUG AUG AUG AUG

RSOH 123.....1516,123...1516,.......

12...16,12...16,...

MSOH
123.....1516,123...1516.

16 x 9 16 x 261
STM–16

A1 – A2 Alignment word A1=11110110, A2=00101000. Utilizes all slots of the sixteen STM–1.
B2 Result of BIP–Nx24 calculation on previous frame except of three RSOH rows.
K1 – K2 For APS indications and FERF, AIS alarms. Uses slot of first STM–1.
S1 Indicates synchronism status. Uses slot of first STM–1.
M1 Indicates section FEBE (STM–16). Uses slot of third STM–1.

Notes:
1AA 00014 0004 (9007) A4 – ALICE 04.10

– bytes marked with S are not scrambled (like the whole first row).

Figure 231. Structure of STM–16 and SOH bytes contents

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576 bytes

A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 J0 Z0

RSOH
B1 E1 F1

D1 D2 D3

AU pointer(s)
9 rows

B2 B2 B2 B2 B2 B2 K1 K2
D4 D5 D6

MSOH
D7 D8 D9
D10 D11 D12
S1 E2

M1

1 261 1 261 1 261 1 261

1 9 1 9 1 9 1 9
#1 #2 #3 #64

AUG AUG AUG AUG

RSOH 123.....6364,123.....6364,.....

12...64,12...64,..

MSOH
123.....6364,123.....6364.

64 x 9 64 x 261
STM–64

A1–A2 Alignment word A1=11110110, A2=00101000. Utilizes all slots.
B2 Result of BIP–Nx24 calculation on previous frame except of three RSOH rows.
K1 – K2 For APS indications and FERF, AIS alarms. Uses slot of first STM–1.
S1 Indicates synchronism status. Uses slot of first STM–1.
M1 Indicates section FEBE (STM–64). Uses slot of third STM–1.

Notes:
– bytes marked with X are reserved for national use
dipendent, additional national use and other purposes)
1AA 00014 0004 (9007) A4 – ALICE 04.10

– bytes marked with S are not scrambled (like the whole first row)


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3.18.1 Synchronous 2048 Kb/s frames

The synchronous 2048 Kb/s signal is structured on a 256–bits frame, numbered 1 to 256; it is composed
by 32 time slots (TS), numbered 0 to 31 (TS0 to TS31), each time slot containing 8 bits. The frame

repetition rate is 8000 Hz (time period 125 µs).

TS0 is used as the OverHead of the frame, for purposes as: frame alignment, error integrity check,
messaging, etc.

The following figure shows the allocation of bits 1 to 8 (i.e. Time Slot 0, TS0) in the basic frame structure
of synchronous 2Mb/s signal.
The frames contain, alternatively, the 7–bits frame–alignment–signal (FAS = 0011011, bits 2 to 8).
Refer to ITU–T G.704 rec. for details information.

Bit
number
1 2 3 4 5 6 7 8
Alternate
frames
Si 0 0 1 1 0 1 1
Frame containing the
frame alignment signal
Note 1 Frame alignment signal

Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
Frame not containing the
frame alignment signal
Note 1 Note 2 Note 3 Note 4

Note 1 – Si = bits reserved for international use. One specific use is for multi–frame alignment and for
CRC–4 procedure: see Figure 234.

Note 2 – this bit is fixed at 1 to assist in avoiding simulations of the frame alignment signal.

Note 3 – A = Remote Alarm Indication (RAI).
In undisturbed operation, set to 0; in alarm condition, set to 1.

Note 4 – Sa4 to Sa8 are used for point–to–point specific messaging.

Figure 233. Synchronous 2048 Kb/s signal: basic frame overhead
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The following figure shows the allocation of bits 1 to 8 (i.e. Time Slot 0, TS0) in the CRC–4 Multiframe
structure of synchronous 2Mb/s signal. CRC–4 is the abbreviation for Cyclic Redundant Check–4, a signal
elaboration procedure to check the error integrity.
Each CRC–4 multiframe, which is composed of 16 frames numbered 0 to 15, is divided into two 8–frame

sub–multiframes (SMF), designated SMF–I and SMF–II which signify their respective order of occurrence

within the CRC–4 multiframe structure. Each sub–multiframe duration is 1 ms, rated 1000 Hz. The SMF
is the CRC–4 block size (i.e. 2048 bits).
Refer to ITU–T G.704 rec. for details information.

Sub–multiframe Frame Bits 1 to 8 of the frame
(SMF) number
1 2 3 4 5 6 7 8

0 C1 0 0 1 1 0 1 1
1 MF 1 A Sa4 Sa5 Sa6 Sa7 Sa8
1
2 C2 0 0 1 1 0 1 1
Ι 2
4 C3 0 0 1 1 0 1 1
3
6 C4 0 0 1 1 0 1 1
4
Multiframe
8 C1 0 0 1 1 0 1 1
5
10 C2 0 0 1 1 0 1 1
ΙΙ 6
12 C3 0 0 1 1 0 1 1
13 E 1 A Sa4 Sa5 Sa6 Sa7 Sa8
14 C4 0 0 1 1 0 1 1
15 E 1 A Sa4 Sa5 Sa6 Sa7 Sa8

Note 1 – E = Remote Error Indication (REI) .

Note 2 – Sa4 to Sa8 are used for point–to–point specific messaging.

Note 3 – C1 to C4 = Cyclic Redundant Check–4 bits.

Note 4 – A = Remote Alarm Indication (RAI).

Note 5 – MF1 to MF6 = Multiframe Alignment Signal (MAS = 001011).

Figure 234. Synchronous 2048 Kb/s signal: CRC–4 multiframe overhead
1AA 00014 0004 (9007) A4 – ALICE 04.10

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3.18.1.1 Organization of ISDN – PRA frames

For each direction of transmission the following functions are provided by the synchronous ISDN–PRA
2048 Kb/s frames (refer to recommendation ETS 300 233):

30 time slots at 64 kb/s (numbered 1 to 15 and 17 to 31) for the transport of any appropriate allocation
of the B, H0 and H1 channels.

1 time slot at 64 kb/s (numbered 16) for the transport of a D channel.

1 time slot at 64 kb/s (numbered 0) for frame alignment, multiframe alignment, CRC–4 procedure and
maintenance (rec. G.704).

3.18.1.2 ISDN – PRA communication channels

The communication channels transported by the ISDN–PRA (Integrated Services Digital Network –
Primary Rate Access) signal are the following:

– B–channel
it is rated 64 kb/s, as defined in ITU–T Rec. I.412; it permits the allocation of up to 30 independent
B–channels over the 2Mb/s synchronous frame.

– H0–channel
it is rated 384 kb/s, as defined in ITU–T Rec. I.412; it permits the allocation of up to 5 independent
H0–channels over the 2Mb/s synchronous frame.

– H1–channel
it is rated 1920 kb/s, as defined in ITU–T Rec. I.412; it permits the allocation of one H1–channel over
the 2Mb/s synchronous frame.

– D–channel
it is rated 64 kb/s, as defined in ITU–T Rec. I.412.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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3.18.2 ATM cells mapping into SDH/PDH frames

V5

34 D Bytes

J2

34 D Bytes
140
bytes
N2

34 D Bytes

K4

34 D Bytes

500us
D Data

Figure 235. Mapping of ATM cells into VC12

J1 ÉÉ
ÉÉ ÉÉ
ÉÉ
B3
C2
G1
VC–4/VC–3
F2
H4

F3

K3
N1
ÉÉ
ÉÉ ÉÉ
ÉÉ
VC–4/VC–3 POH

ATM Cell

ÉÉ
ÉÉ 53 octets
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 236. Mapping of ATM cells into VC4/VC3

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TS0 TS16: Reserved for signalling

256 bits / 125 µs

ÇÇ ÇÇÇ Header
ÇÇ ÇÇÇ
ÇÇÇ ÇÇ
ÇÇÇ ÇÇHeader
ÇÇÇ ÇÇ
ÇÇÇ ÇÇ Header

Ç Ç Ç ÇÇÇ
Header
Ç Ç Ç ÇÇÇ
ATM cell mapping field: 30 octets (TS1 : TS15 and TS17 : TS31)

Provides F3 OAM functions:
– Detection of loss of frame alignement
–Performance monitoring (CRC–4)
– Transmission of FERF and LOC
Ç Ç ÇÇÇ
ATM
cell
Ç Ç ÇÇÇ Header
–Performance reporting

53 octets

Figure 237. Mapping of ATM cells into 2048 kb/s frame

59 octets

ÇÇÇ
ÇÇ ÇÇÇÇÇ
ÇÇÇ
Ç ÇÇÇ
Ç Ç ÇÇ
ÇÇÇ
Ç ÇÇÇ ÇÇÇ
ÇÇÇ ÇÇÇ
9 rows

Ç Ç Ç ÇÇÇ
ÇÇÇÇ
Ç ÇÇÇÇ
ÇÇ ÇÇÇÇ ÇÇ Ç
ÇÇÇÇ
ÇÇ
ATM cells
ÇÇÇ
ÇÇÇ
53 octets

Overhead octet
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 238. Mapping of ATM cells into 34368 kb/s frame

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4 UNITS DESCRIPTION

In the following paragraphs are inserted the detailed information of each unit and subunit of the equipment.

4.1 21 x 2 Mbit/s access card (A21E1)

The 21 x2 Mbit/s access card provides the connections from back panel to the external line and viceversa
for 21 PDH signals. According to the type of line impedance (75 Ohm or 120 Ohm) and electrical
characteristics different types of access card are available.
In the following a generic description of the access card is given:
INPUT side
Under normal operating condition, the signal received from the line is sent to the 63 x 2 Mbit/s “main” port
card.
Under alarm condition, the signal received from the line is switched towards the “spare” port card. The
switching command SEL is received from the RIBUS I/F block.
A protection block is present to protect the incoming signal against spikes ( G.703).
OUTPUT side
The two signals received from the “main” and “spare” port cards 63 x 2 Mbit/s are sent to a selector.
The SEL command, received from the RIBUS I/F block, select the signal to sent to the line

Remote inventory
The RIBUS I/F is present to read/write inventory data as code, series number, construction data present
on the RI (see para. 3.17 on page 370 for details).
Power supply

The access card receive the +3.3 Vdc provided by the CONGI units.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Input–1 TO MAIN PORT
INPUT SPIKE
FROM LINE PROTECTION
TO SPARE PORT

SEL

Output–1
OUTPUT SPIKE FROM MAIN PORT
TO LINE PROTECTION FROM SPARE PORT

SEL

Input–21 TO MAIN PORT
INPUT SPIKE
FROM LINE PROTECTION
TO SPARE PORT

SEL

Output–21
OUTPUT SPIKE FROM MAIN PORT
TO LINE PROTECTION FROM SPARE PORT

SEL

SEL
FAIL

REMOTE RIBUS RIBUS
INVENTORY IF TO/FROM
CMISS MATRIXE

+3.3 Vdc F
FROM CONGI
21 x 2 MBIT/S ACCESS CARD

Figure 239. 21 x 2 access card – Block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.2 3 X 34 Mbit/s access card (A3E3)

( See Figure 240. on page 388)

The 3 x 34 Mbit/s access card provides the connections from back–panel to the external signals and vice

versa for three PDH 75 ohm signals in compliance with the ITU–T G.703 rec.

The following functions are implemented :

– Signal decoding, encoding and LOS alarm management
– Protection towards spare cards
– local and remote loopback
– control and inventory functions
– power supply

INPUT side

From the HDB3 signal received from the line the clock is recovered and the data are retimed and sent to
a decoder (NRZ format). LOS alarm is generated if no signal is detected.
In normal condition the backplane provides to send the signal to the main card .
The access card manages the EPS protection of the 3x34/45 port card; two mux by means of dedicated
command (SEL) coming from the RIBUS I/F block, sends to spare card Signal and LOS of actual or
previously access card.

OUTPUT side

On the output side the access card receives the NRZ data and clock from the main and spare port card.
By means of a mux in normal condition the signal coming from the main port card is then HDB3 encoded
and sent to the line.
When EPS is active, the RIBUS I/F block send a command (SEL) to the mux; in this case the signal coming
from the spare card is selected and sent toward the encoder.
The received clock and NRZ data from spare card are sent also to the next access card to perform EPS
protection.

Loopback functions

The access card provides line loopback and internal loopback.
When line loop is active the input signal coming from the line (DR) is sent back ,through a mux , to the
output signal performing line loopback.
When internal loop is active, the signal coming from the encoder (DT) is sent, through a mux, to the
decoder thus realizing the local loopback function.

Control section

The commands to drive the MUXs involved in EPS protection (SEL) and the loopback functions (LINE
LOOP and INT LOOP) are generated by the RIBUS I/F block that performs also remote inventory and card
status operations (FAIL).

Power Supply

The access card receive the following voltage:

– +3.3 Vdc from CONGI to supply the RIBUS I/F block
1AA 00014 0004 (9007) A4 – ALICE 04.10

– + 3.3 Vdc from the relevant Port Card; through an on board DC/DC converter is generated a + 5.3
Vdc starting from the +3.3 Vdc.

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CK
SIGNAL INPUT 1 EQUALIZER DECODER
FROM COAX HDB3/NRZ TO MAIN CARD

RETIMER
HDB3

DR

DT
DATA FROM
PREVIOUSLY MUX TO SPARE CARD
ACCESS CARD

LOS TO MAIN CARD
LOS

LOS FROM MUX LOS TO SPARE CARD
PREVIOUSLY
ACCESS CARD
ACCESS 1 – Input side SEL
DR

DT

SIGNAL OUTPUT 1
TO COAX PULSE LOOP ENCODER MUX FROM MAIN CARD
HDB3 SHAPER MUX NRZ/HDB3
LINE LOOP
INT LOOP

TO NEXT
ACCESS CARD
MUX FROM SPARE CARD

ACCESS 1 –Output side
SEL

ACCESS 2

ACCESS 3
LINE LOOP
INT LOOP

SEL

CMISS
FAIL

TO/FROM
REMOTE RIBUS RIBUS
MATRIXE
INVENTORY I/F
+3.3 Vdc F
FROM CONGI
+5.3 Vdc +3.3 Vdc
DC/DC FROM
RELEVANT PORT CARD
3 X 34 ACCESS CARD
+3.3 Vdc
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 240. 3 x 34 access card block diagram

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4.3 3 X 45 Mbit/s access card (A3T3)

( See Figure 241. on page 390)

The 3 x 45 Mbit/s access card provides the connections from back–panel to the external signals and vice

versa for three PDH 75 ohm signals in compliance with the ITU–T G.703 rec.

The following functions are implemented :

– Signal decoding, encoding and LOS alarm management
– Protection towards spare cards
– local and remote loopback
– control and inventory functions
– power supply

INPUT side

From the B3ZS signal received from the line the clock is recovered and the data are retimed and sent to
a decoder (NRZ format). LOS alarm is generated if no signal is detected.
In normal condition the backplane provides to send the signal to the main card .
The access card manages the EPS protection of the 3x34/45 port card; two mux by means of dedicated
command (SEL) coming from the RIBUS I/F block, sends to spare card Signal and LOS of actual or
previously access card.

OUTPUT side

On the output side the access card receives the NRZ data and clock from the main and spare port card.
By means of a mux in normal condition the signal coming from the main port card is then B3ZS encoded
and sent to the line.
When EPS is active, the RIBUS I/F block send a command (SEL) to the mux; in this case the signal coming
from the spare card is selected and sent toward the encoder.
The received clock and NRZ data from spare card are sent also to the next access card to perform EPS
protection.

Loopback functions

The access card provides line loopback and internal loopback .
When line loop is active the input signal coming from the line (DR) is sent back ,through a mux , to the
output signal performing line loopback.
When internal loop is active, the signal coming from the encoder (DT) is sent, through a mux, to the
decoder thus realizing the local loopback function.

Control section

The commands to drive the MUXs involved in EPS protection (SEL) and the loopback functions (LINE
LOOP and INT LOOP) are generated by the RIBUS I/F block that performs also remote inventory and card
status operations (FAIL).

Power Supply


– + 3.3 Vdc from the relevant Port Card; through an on board DC/DC converter is generated a + 5.3
1AA 00014 0004 (9007) A4 – ALICE 04.10

Vdc starting from the +3.3 Vdc.

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CK
SIGNAL INPUT 1 EQUALIZER DECODER
FROM COAX B3ZS/NRZ TO MAIN CARD
RETIMER
B3ZS

DR
DT

DATA FROM
PREVIOUSLY MUX TO SPARE CARD
ACCESS CARD

LOS TO MAIN CARD
LOS

LOS FROM MUX LOS TO SPARE CARD
PREVIOUSLY
ACCESS CARD
ACCESS 1 – Input side
SEL
DR

DT

SIGNAL OUTPUT 1
TO COAX PULSE LOOP ENCODER MUX FROM MAIN CARD
B3ZS SHAPER MUX NRZ/B3ZS
LINE LOOP
INT LOOP

TO NEXT
ACCESS CARD
MUX FROM SPARE CARD

ACCESS 1 –Output side
SEL

ACCESS 2

ACCESS 3
LINE LOOP
INT LOOP

CMISS
SEL
FAIL

TO/FROM
MATRIXE
REMOTE RIBUS RIBUS
INVENTORY I/F

+3.3 Vdc F
FROM CONGI
+5.3 Vdc +3.3 Vdc
DC/DC FROM
RELEVANT PORT CARD
+3.3 Vdc
3 X 45 ACCESS CARD
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 241. 3 x 45 access card block diagram

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4.4 2 x 140/STM–1 O/E adapter (A2S1)


The A2S1 access card can house two independent modules that can be both electrical , both optical or

a mix of the two.

For the description of the electrical module see paragraph 4.15 on page 425.

For the description of the optical module see paragraph 4.16 on page 427.

The access card houses also the RIBUS I/F block the function of which is described on para.3.17 on
page 370 and the Remote inventory.

Control section

The RIBUS I/F block is present to read/write inventory data as code, series number, construction data
implemented on the REMOTE INVENTORY block.
It also send and receive the following signal:

– FAIL: unit faulty

– CMISS1, CMISS2: card missing respectively of the upper and lower “electrical or optical module”

– INT LOOP1, INT LOOP2: Internal Loop command respectively for the upper and lower “electrical
or optical module”

– LINE LOOP1, LINE LOOP2: Line Loop command respectively for the upper and lower “electrical
or optical module”

Power Supply


– + 3.3 Vdc and + 5.2 Vdc from the relevant Port Card;
1AA 00014 0004 (9007) A4 – ALICE 04.10

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INT LOOP1
LINE LOOP1
CMISS1
INPUT
RI
ELECTRICAL LOS
OR
LINE1 OPTICAL LASER DEG
MODULE LASER FAIL
OUTPUT LASER SHUT DOWN
DATA AND CLOCK TO/FROM
PORT CARD

+3.3 Vdc +3.3 Vdc (Vs) +5.2 VDC

INT LOOP2
LINE LOOP2
CMISS2
INPUT
RI
ELECTRICAL LOS
OR
LINE2 OPTICAL LASER DEG
MODULE
LASER FAIL
OUTPUT
LASER SHUT DOWN
DATA AND CLOCK TO/FROM
PORT CARD

+3.3 Vdc +3.3 Vdc (Vs) +5.2 VDC
LINE LOOP1
LINE LOOP2
INT LOOP1
INT LOOP2
CMISS1
CMISS2

CMISS
FAIL

TO/FROM
RI MATRIXE
REMOTE RIBUS
RIBUS
INVENTORY I/F

+3.3 Vdc (Vs) F
+3.3 Vdc (Vs) FROM CONGI
+3.3 Vdc
FROM
+5.2 Vdc RELEVANT PORT CARD
2 X 140/STM–1 O/E ADAPTER

Figure 242. 2 x 140/STM–1 O/E adapter (access card) block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.5 4 x STM–1 electrical access card (A4ES1)


The A4ES1 access card is placed in the access area and allows the connection to the line coaxial cable

for the High Speed port cards 4x STM1.

INPUT side

On the input side the signal CMI coming from the coaxial cable, is equalized , decoded into NRZ code and
forwarded to main electrical port card.
The command criteria SWITCH coming from the RIBUS I/F block can select the MUX in order to send
toward the Spare card the local stream .
The LOS alarm, if present, is sent to the main board. The same alarm can also be sent ,through a MUX,
toward the spare card if the SWITCH command is active .

OUTPUT side

On the output side, the signal coming from the Main card, is coded into CMI code and then sent toward
the coaxial cable.
When EPS is active, the RIBUS I/F block send a command (SWITCH) to the MUX; in this case the signal
coming from the Spare card is selected and sent toward the encoder NRZ/CMI.

Control section

implemented on the RI.
It also send the following command:

– INT LOOP1 … INT LOOP4: Internal Loop commands for channels from 1 to 4

– LINE LOOP1 … LINE LOOP4: Line Loop commands for channels from 1 to 4

– SWITCH allows EPS facility

On the front cover plate a red/green led is available for card fail alarm indication.

Power Supply


– + 3.3 Vdc from the relevant Port Card;
1AA 00014 0004 (9007) A4 – ALICE 04.10

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CMI LOS
CMI PLL
INPUT TO MAIN CARD
NRZ NRZ

DR

NRZ TO SPARE CARD
MUX
DT

SWITCH
INT LOOP1
NRZ FROM PREVIOUSLY
LOS ACCESS CARD

MUX LOS TO SPARE CARD

ACCESS 1 – Input side SWITCH

DR
DT

CMI NRZ FROM MAIN CARD
CMI Mask
OUTPUT Adapter NRZ PLL MUX NRZ FROM SPARE CARD

SWITCH NRZ TO NEXT
LINE LOOP1 ACCESS CARD

ACCESS 1 – Output side

CMI
INPUT

CMI ACCESS 2
OUTPUT

CMI
INPUT

ACCESS 3
CMI
OUTPUT
CMI
INPUT

ACCESS 4
CMI
OUTPUT
LINE LOOP1
LINE LOOP2
LINE LOOP3
LINE LOOP4
INT LOOP1
INT LOOP2
INT LOOP3
INT LOOP4

SWITCH

CMISS
FAIL

TO/FROM
MATRIXE
REMOTE RIBUS RIBUS
INVENTORY I/F
+3.3 Vdc F
FROM CONGI
+3.3 Vdc
FROM
+5.2 VDC RELEVANT PORT CARD
4 X STM–1 ELECTRICAL ACCESS CARD
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 243. 4 x STM–1 access card block diagram

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4.6 Optical Access 12xSTM–1 (A12OS1E or A12OS1SE)


NOTE: the optical access card A12OS1E functinal description can be applied also to the A12OS1SE

access card. The only difference between the two boards is the mechanical dimension; as a matter of fact
A12OS1E is two slot wide instead of one slot wide of the A12OS1SE.

The A12OS1E is 12 X STM–1 Access Card that provides 12 X 155 Mbps STM–1 interface from external
line to the backplane and vice versa, for both Short–haul and Long–haul applications.

The P16S1–4E card along with A12OS1E card allows the transport of 16 optical STM1 streams by means
of 16 SFP optical transceivers. On the P16S1–4E card there are four of 16 SFP transceivers, while in the
A12OS1E card there are the other 12 SFP MSA compliant Transceivers

The Card recovers Data and Clock from the Optical input and passes them to the onboard “STM–1
MAPPER/DEMAPPER” block. .

The “STM–1 MAPPER/DEMAPPER” block makes customized frame and send it to serializer block
SERDES that passes the data to the backplane.

Remote inventory is provided by on the board using RIBUS I/F device RIBUS bus. It also contains circuitry
for management, configuration, and control of onboard devices through backplane RIBUS bus.

Following is the list of main features of A12OS1E Card:

SFP Optical Transceiver :

– Provides 12 X 155 M bits/sec STM–1 Optical Transmit Receive line side Interface for both
short–haul and Long–haul applications. The Optical interface is provided by Small Form factor
Pluggable (SFP) Duplex–LC Transceivers, compliant with MultiSource Agreement (MSA)

– Provides LOS and LASER FAULT status information. Also, the LASER can be switched ON/OFF
by controlling the signal LASER OFF.

– Provides EEPROM for identification information of the SFP Transceiver, which describes the
transceiver’s capabilities, standard interfaces, manufacturer and other information.

Clock Data Recovery :

– Provides Clock recovery for the 12 incoming STM–1 streams.

Data adaptation for backplane (“STM–1 MAPPER/DEMAPPER” block):

– Multiplex pair of 155 M bits/sec STM–1 data streams from “CLOCK AND DATA RECOVERY” block
to 414 M bits/sec customised data stream and send it to SERDES.

– In transmit path, de–multiplex 414 M bits/sec customised data stream from SERDES to pair of 155
M bits/sec STM–1 data streams and send it to SFP.

SERDES:

Serialise data from the STM–1 MAPPER/DEMAPPER” block and send to the back plane interface at 1.6G
1AA 00014 0004 (9007) A4 – ALICE 04.10

rate.

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In the transmit path, De–serialise data from Backplane and send it to the STM–1 MAPPER/DEMAPPER”
block.

Control and Status signal processing:

RIBUS I/F provides for power up status/configuration. Also, generation and monitoring of various status
and control signals are done through the ports of RIBUS I/F like read remote inventory data from the
EEPROM

Timing Circuitry

Provides a 19.44 MHz crystal oscillator and a 1:13 clock buffer for providing Reference clocks for the 12
“Clock Data Recovery” block.

Provides timing circuitry, which includes 622 MHz VCXO and associated circuits for external clock
generation and PLL function

LEDs

Provides one board STATUS LED (refer to Figure 68. on page 157)

Power Supply



– 48/60 Vdc from CONGI and generates throught on board DC/DC converters the following voltage:

• 3.3 Vdc
• 2.5 Vdc
• 1.8 Vdc
• 1.5 Vdc
1AA 00014 0004 (9007) A4 – ALICE 04.10

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CK1 TIMING
CIRCUITRY
CK19 MHz

1:13

CK12

Optical STM–1
Input/ #1
Output laser fault (LF)
1 1
laser off (LOFF)

P16S1–4E board
2

from lelevant
SFP 3 LOS
MODULE
DATA CK
RECOVERY
8x414 Mb/s
Data and alarms

MAPPER/DEMAPPER
CK1
2x1.66 Gb/s
STM–1 SERDES

1.8V
DC/DC
1.5V
1.2V CONVERTER
Optical laser fault (LF)
1
Input/ laser off (LOFF)
Output 2
SFP

CONGI A B
12 3 LOS 3.3 V DC/DC
MODULE
CONVERTER 48/60 V

FROM
DATA CK STM–1
#12
RECOVERY
PROTECTION

CK12

Configuration

Status

MAIN AND SPARE
MATRIXE

CMISS
Remote
Inventory ID
RIBUS RIBUS
I/F

Unit
CONGI A B

F + 3.3 Vdc
Failure
FROM

12xSTM–1 OPTICAL ACCES CARD
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 244. 12 x STM–1 optical access card block diagram (A12OS1E or A12OS1SE )

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4.7 Electrical Access 16xSTM–1 (A16ES1E)


The A16ES1E board is 16 X STM–1 Access Card that provides line interface at STM–1 rate of 155 Mbps

for 16 electrical signals using RF coaxial connectors. .

The Card contains devices which recovers Data and Clock from the input and performs LOS detection,
equalization, encoding and decoding functions.

The data and control signals are processed by “STM–1 MAPPER/DEMAPPER” block and passed on to
the Backplane interface through serializer SERDES device.

Remote inventory is provided on the board using RIBUS I/F device that read data from an EEPROM.

Following is the list of main features of A16ES1E Electrical Access Card:

Electrical line interface at STM–1 rate for 16 electrical signals.

Provides 16 X 155 Mbps STM–1 Electrical Transmit Receive line side Interface. The interface is provided
by RF coaxial connectors.

Clock Data Recovery

This block provides Automatic equalization, Clock and data recovery and LOS detection for the 16
incoming STM–1 Scrambled CMI encoded data streams.


The recovered data and LOS signals are provided to the “STM–1 MAPPER/DEMAPPER” block that
combines pair of STM–1 signal into a signal of data rate 414 Mbps.

The 414 Mbps signals are further processed by the SERDES device which serializes four such signals
into a signal of data rate 1.6 Gbps.

The reverse path interface for the data is also provided through the “STM–1 MAPPER/DEMAPPER” block.

Clock Data Recovery :

Provides Clock recovery for the 16 incoming STM–1 streams.


Multiplex pair of 155 M bits/sec STM–1 data streams from “CLOCK AND DATA RECOVERY” block to 414
Mbits/sec customised data stream and send it to SERDES.

In transmit path, de–multiplex 414 M bits/sec customised data stream from SERDES to pair of 155
Mbits/sec STM–1 data streams and send it to SFP.

SERDES:

Serialise data from the STM–1 MAPPER/DEMAPPER” block and send to the back plane interface at
1.6Gb/s rate.

In the transmit path, De–serialise data from Backplane and send it to the STM–1 MAPPER/DEMAPPER”
1AA 00014 0004 (9007) A4 – ALICE 04.10

block.

SERDES device processes the data from/to neighbouring Access Cards at 1.6 Gbps involved in an EPS
scheme (refer to paragraph 3.13.1 on page 322 for details).

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Control and Status signal processing:

RIBUS I/F provides for power up status/configuration. Also, generation and monitoring of various status
and control signals are done through the ports of RIBUS I/F like read remote inventory data from the

EEPROM

Timing Circuitry

Provides timing circuitry, which includes 622 MHz VCXO and associated circuits for external clock
generation and PLL function

LEDs

Provides one board STATUS LED (refer to Figure 68. on page 157)

Power Supply



– 48/60 Vdc from CONGI and generates throught on board DC/DC converters the following voltage:

• 3.3 Vdc
• 2.5 Vdc
• 1.8 Vdc
• 1.5 Vdc
1AA 00014 0004 (9007) A4 – ALICE 04.10

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P16S1–4E board
from/to relevant
CK19 MHz

622 MHz

OSC

ACCESS CARD
from/to previous
2x1.66 Gb/s
LOS

STM–1
#1 16x414 Mhz
Data Data and alarms
DATA CK
RECOVERY Ck

P16S1–4E board
Electrical Line

from/to relevant
Input/ I/F 2x1.66 Gb/s
Output #1 Data
1 SERDES

MAPPER/DEMAPPER
STM–1

ACCESS CARD
from/to next
2x1.66 Gb/s

LOS
1.8V
DC/DC
1.5V
1.2V CONVERTER

Data
DATA CK

CONGI A B
3.3 V DC/DC
RECOVERY Ck CONVERTER 48/60 V

FROM
Electrical Line STM–1
Input/ I/F
Output #16 #16
Data PROTECTION
16

Configuration

Status
MAIN AND SPARE
MATRIXE

CMISS
Remote
Inventory ID
RIBUS RIBUS
I/F

Unit
CONGI A B

F + 3.3 Vdc
Failure
FROM

16xSTM–1 ELECTRICAL ACCESS CARD
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 245. 16 x STM–1 electrical access card block diagram (A16ES1E)

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4.8 High Speed protection access card (HPROT)


The HPROT access card is used to realize EPS protection for High Speed ports. It realizes the connection

between the Access Cards and Spare HS Port if protection request. See para 3.13.1 on page 322 for
details.
It receives the signals coming from the access card via back panel .

Control section

implemented on the RI.

Power Supply


– + 3.3 Vdc from the relevant Port Card;

On the front cover plate a red/green led is available for card fail alarm indication.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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NRZ NRZ
FROM CK CK TO
PREVIOUS NRZ NRZ SPARE HSBOARD
ACCESS CK CK
CARD LOS LOS

NRZ NRZ
FROM CK CK
PREVIOUS NRZ NRZ TO
ACCESS SPARE HSBOARD
CK CK
CARD LOS LOS

NRZ NRZ
FROM CK CK
PREVIOUS NRZ NRZ TO
ACCESS SPARE HSBOARD
CK CK
CARD LOS LOS

NRZ NRZ
FROM CK CK
PREVIOUS NRZ NRZ TO
ACCESS CK SPARE HSBOARD
CK
CARD LOS LOS
FAIL

TO/FROM
REMOTE RIBUS RIBUS MATRIXE
INVENTORY I/F
+3.3 Vdc F
FROM CONGI
+3.3 Vdc
FROM RELEVANT PORT CARD

HPROT ACCESS CARD
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 246. HPROT access card block diagram

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4.9 ISA – Ethernet access card (ETH–ATX)


The ETH–ATX access card is placed in the access area and is able to provide 14 x 10 /100 Mb/s Ethernet

Interfaces to allows LAN to LAN connection.
On the ETH–ATX access card only the physical interface function is implemented, so it must be used
in conjunction with the relevant ETHERNET port where the signal is processed in order to be transported
in a SDH VCx.
INPUT side

The 14 Ethernet flows coming from the line are sent to 14 transformer to implement the crossover
functionality.

Subsequently the Ethernet flows are managed by the “Self Rate Adapting” block. This block at start–up
auto–negotiate the maximum rate accepted by the interface (10Mbit/s, 100 Mbit/s, Half duplex, Full
duplex) and after having processed the signal, data are sent through a serializer (PISO SIPO block) to
the relevant Ethernet port.
The Rate interface (10Mbit/s, 100 Mbit/s, Half duplex, Full duplex) can also be forced by the
Microcontroller present on the relevant ETHERNET PORT through the “Rate Adapting Forced Rate”
command.

A VCX0 is present on the board to deliver a 125 MHz clock to the “Self Rate Adapting” block.
OUTPUT side

The complementary operation described in the “Input side” are performed.

Control section

The RIBUS I/F block is present to read/write inventory data as code, serial number, construction data
implemented on the RI and also send programming info to the “Self Rate Adapting” block.

Power Supply


– 48/60 Vdc from the CONGI;

On the front cover plate 14 10BASE T connectors and a red/green led are available; the last gives fail
alarm indication for the access card.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Rate adapting
VCX0 forced settings
125MHz

1 ÎÎÎ
ÎÎÎ

ETHERNET PORT
ÎÎÎ
ÎÎÎ

10/100 Mb/s
ETHERNET INTERFACE 10 BASE T

2

from/to
ÎÎÎ
ÎÎÎ
SELF RATE ADAPTING
1.2 Gb/s DATA
Full–duplex
Half–duplex SIPO
10 Mbit/s
13 ÎÎÎ
ÎÎÎ
100 Mbit/s
PISO

14
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ Program

MATRIXE MAIN AND SPARE
CMISS

from/to
Remote
Inventory
RIBUS
RIBUS ID
I/F F +3.3 Vdc
Unit
Failure
FROM CONGI

3.3 V
DC/DC 48/60 V
2,5 V CONVERTERS

ETHERNET ACCESS

Figure 247. Ethernet Access –Block Diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.10 ISA – Gigabit Ethernet access Card (GETH–AG)


The GETH–AG access card is placed in the access area and can be equipped with up to 4 “Optical

Transceiver modules at 1.25 Gb/s” providing Gigabit Ethernet Interfaces to allows LAN to LAN
connection.

For the description of the optical module refer to paragraph 4.19 on page 430.

On the GETH–AG access card only the physical interface and some control functions are implemented,
so it must be used in conjunction with the ETHERNET or GIGABIT ETHERNET port where the signal
is processed in order to be transported in a SDH VCx.
Refer to paragraph 3.8.5.2 for details on ethernet architecture in 1660SM.
INPUT side

The four Gigabit Ethernet flows coming from the “Optical Transceiver “ (DATA#1...DATA#4) are sent to
a block that performs the following functionality according to IEEE 802.3:

– Physical Coding Sublayer (PCS);allows to couple the Gigabit Media Independent Interface (GMII)
and the Physical Media Attachment (PMA).
The functions performed are:

• Serializer/de–serializer

• 8B/10B coding ; 8 data bits are coded in a 10 data bits.

– Auto–negotiation; negotiation of common data service functions with the device on the other end of
the link.

– Gigabit Media Independent Interface (GMII)

Subsequently the four 1.25 Gb/s Ethernet flows are sent towards the relevant “Ethernet port” or “Gigabit
Ethernet port” where the signals will be processed and mapped onto SDH–VC

A VCX0 is present on the board to deliver a 125 MHz clock .
OUTPUT side

The complementary operation described in the “Input side” are performed.

Control section

The RIBUS I/F block is present to read/write inventory data as code, serial number, construction data
implemented on the Remote Inventory and also send programming info to the “Alarms Remote Inventory
Management” block.
On the front cover plate a red/green led is available giving fail alarm indication for the access card.
The presence of the Optical Transceiver modules is detected by the RIBUS I/F block by means of the
SI1...SI4 signals.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Alarms Remote inventory Management

This block manage the alarms and commands receive/sent by/to the Optical Transceiver modules (LOS,
LASER FAIL, LASER SHUTDOWN). Also the Optical Transceiver modules Remote inventory data are

read through the RI1.....RI4 signals (for example the laser type). Further all this data are sent via ISFB

bus to the relevant port card and than to the Shelf Controller on the MATRIX card where are processed.

The Alarms Remote Inventory Management block is configurated by the RIBUS I/F; an external
configuration interface is also available on the board, but the use is for Alcatel personnel only.

Power Supply


– +3.3 Vdc (Vs) from CONGI to supply the RIBUS I/F block
– 48/60 Vdc from the CONGI;

A DC/DC converter generates the following voltages starting from the station battery:

– 3.3 Vdc
– 2.5 Vdc
– 1.8 Vdc
1AA 00014 0004 (9007) A4 – ALICE 04.10

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+3.3 Vdc
125 MHz 125 MHz
SI1 OSC.
INPUT OPTICAL RI1

MODULE

Line #1 LOS *1
1000BASE–SX LASER FAIL
LASER SD Reset
1000BASE–LX
OUTPUT 1000BASE–ZX

ETHERNET PORT 10/100 Mb/s

GIGABIT ETHERNET PORT
DATA #1 #1
PCS sublayer

4X 1.2 Gbit/s to/from
( Serializer/Deserializer #2
8B/10B Coding/Decoding )

or
#3
+3.3 Vdc GMI Interface
SI2 Autonegotiation #4
INPUT OPTICAL RI2
MODULE
LOS *2
Line #2 LASER FAIL
1000BASE–SX 3.3 Vdc
LASER SD
1000BASE–LX 2.5 Vdc DC/DC

CONGI
FROM
OUTPUT 1000BASE–ZX DATA #2 Converters 48/60 V
1,8Vdc

Internal use only
+3.3 Vdc
SERIAL EXT.
OPTICAL SI3 CONFIGURAT. CONF.
INPUT MODULE RI3 PROM INT:

1000BASE–SX LOS

CONFIGURATION
Line #3 *3
1000BASE–LX LASER FAIL
LASER SD
1000BASE–ZX
OUTPUT
DATA #3
(*)

ETHERNET PORT 10/100 Mb/s

GIGABIT ETHERNET PORT
*1
+3.3 Vdc *2
SI4 *3 Alarms ISFB
INPUT
OPTICAL RI4

to/from
Remote Inventory

or
MODULE *4
Line #4 LOS RI1 Mangement
1000BASE–SX *4
LASER FAIL RI2
1000BASE–LX LASER SD RI3
OUTPUT 1000BASE–ZX RI4
DATA #4
CONFIGURATION

(*)
RESET
SI1
SI2

SI3
SI4

CMISS

TO/FROM
REMOTE MATRIXE
INVENTORY RIBUS RIBUS
FAIL I/F

+3.3 Vdc (Vs) F
+3.3 Vdc (Vs) FROM CONGI

ISA– GIGABIT ETHERNET ACCESS
1AA 00014 0004 (9007) A4 – ALICE 04.10

Note: not used if the ”Gigabit Ethernet access” is used in conjunction with the ”Ethernet Port” (ETH–MB)

Figure 248. Gigabit Ethernet Access card –Block Diagram

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4.11 ISA –16 FEA–PR Fast Ethernet Access Card

The 16FEA–PR access card provides 16 * 10/100 Mbit/s interfaces for use with the ISA–PR port card.

The 16FEA–PR card occupies 2 Access slots within the chassis.

This section provides a generic description of the 16FEA–PR Access Card.

Functional Overview

The primary function of the 16FEA–PR access card is to physically terminate client 10/100 Fast Ethernet
interfaces. Traffic received from these interfaces is validated, processed and passed to the ISA–PR port
card for transmission over the network. Traffic received from the packet ring is processed in the access
card and delivered to the correct customer port in a valid packet format.

The card itself comprises two sub–cards:

• Base Card: provides control and packet processing functions
• ”Phy” (or Physical) card: which provides the physical interfaces and connectors

PHY CARD

BP connector 0 BP connector 0

Timing
BP Serdes Tx 1.25GBps x 3ch

Rx 1.25GBps x 3ch
FPGA nP
SE2PROM
HOST
Manag
CONT
DATA
CONT
RGGI

ADDRESS
RGGI
Packet Memory

ADDR Network Processor: Rx
Tx
DATA
Validation
DATA Search Memory
CONT
Frame classification, ADDRESS
editing and buffering CONT

Base Card
PHY
Manag
SMII
SMII

FE PHY FE PHY
POWER
0 1

8 x RJ45 8 x RJ45 PHY CARD
connectors connectors
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 249. 16FEA–PR Card Functional Block Diagram

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Data Path – Ingress
The 16 physical Ethernet interfaces are hosted by a network processor embedded on the access card.


• Correct Packet Format; Ethernet frame format as per IEEE 802.3 including:
• 802.3
• 802.1Q

• Packet Size

• Valid CRC

The network processor processes only valid frames and discards the invalid frames. The first stage of
processing is packet classification. Frame classification is used to identify:–

• The service to which this frame belongs. Frame destination or set of destinations depends on
the service type. This is defined in the provisioning process.
• Identify the frame priority. This will determine the precedence and delay with which it will be
forwarded to the ISA–PR port card. Frames will be classified into one of three available CoS
(Class of Service) queues defined as high, medium or low.

For further information with regard to service definitions and QoS mechanisms in the ISA–PR, please refer
to 3.7 on page 245 and 4.35 on page 508.

Following frame classification, the network processor performs frame editing. Frame editing refers to the
appending or swapping of a tag for identification purposes. The following functions are currently
supported.

• Append MPLS tag to identify the service and priority to which the frame belongs. This
information is used by other network elements in network – always
• Strip Martini header – optional
• Append, Swap or Strip VLAN – optional

The network processor forwards validated and edited frames to the port card (ISA–PR) for transmission
to the destination access cards. Payload information is passed between the access card and port card
via two 1Gbps backplane channels.

Data Path – Egress
The first part of the egress process takes part on the port card. For further details, please refer to 4.35
on page 508.

Frames that have been designated for deliveries to client ports are delivered from the port card to the
relevant access card over two 1Gbps backplane channels.

The network processor handles the buffering of frames until they can be forwarded over the appropriate
Ethernet interface. Delivery of frames is according to bandwidth availability and frame priority.

Prior to emitting a frame network processor applies frame editing as follows:
1AA 00014 0004 (9007) A4 – ALICE 04.10

• Strip MPLS tag, which has been used to identify the service and priority to which the frame
belongs at the ring – always
• Append Martini header – optional

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Performance Monitoring
The 16FEA–PR card maintains performance monitoring counters at both Port and Queue levels. At the
Port level these are standard Ethernet counters. At the Queue level these are discard counters.

Control

The 16FEA–PR card is managed via a controller hosted on the ISA–PR port card.
The control bus can be used to read inventory information such as serial number, construction information
date of manufacture.
On the front plate, two LEDs give alarm indication for the card as specified in the table below.

Table 50. 16FEA–PR card LEDs designation

LED name State Alarm / Status
ON = Minor
OK YELLOW
Blinking 50/50 = maintenance in progress (loopbacks...)
ON = Major/Critical
Blinking 50/50 = during the POST (Power On Self Test) failure. On
OK RED POST completion the LED will change its color according to the card
status afterwards
Blinking 20/80 = card mismatch
ON = OK Status
OK GREEN Blinking 50/50 = during init
Blinking 20/80 = card is unassigned, i.e. not yet approved by NMS
OK OFF the card is not powered
Active GREEN ON = the card is powered
Active OFF the card is not powered

Physical Interfaces
The 16FEA–PR access card front view is shown in Figure 74. on page 163.
Each of the interfaces is fully standards compliant to IEEE 802.3 offering 10/100 Base–TX physical
interconnection and a choice of the full range transmission modes (10/100 Mbit/s, Full/Half Duplex, Fixed
or Auto negotiation transmit mode)
A full listing of the interface characteristics can be found in section 5.5.2 on page 611.

Each Ethernet interface has LED indications specified in the table below.

Table 51. 16FEA–PR interface LED designation

LED State Designation

Link Green Link up

Link Off Link down

Activity Yellow RX/TX in process

Activity Off Link silent

Power
1AA 00014 0004 (9007) A4 – ALICE 04.10

The access module receives a 7v DC supply from the port card, which is used to power the components.
Other voltages required are generated on the card itself.
The power consumption of the 16FEA–PR Fast Ethernet Access card is 23 Watts.

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4.12 ISA – 2 GBA–PR Fast Ethernet Access Card

The 2GBA–PR access card provides 2 * Gbit/s interfaces for use with the ISA–PR port card.

The 2GBA–PR card occupies 2 Access slots within the chassis.

The card itself comprises two sub–cards:

• Base Card which provides control and packet processing functions
• ”Phy” (or Physical interface) card which provides the physical interfaces and connectors

This section provides a generic description of the 2GBA–PR Access Card.

Functional Overview

The primary function of the 2GBA–PR access card is to physically terminate client Ethernet interfaces.
Traffic received from these interfaces is validated, processed and passed to the ISA–PR port card for
transmission over the network. Traffic received from the packet ring is processed in the access card and
delivered to the correct customer port in a valid packet format.

PHY CARD

BP connector 0 BP connector 0

Base Card
Timing
BP Serdes Tx 1.25GBps x 3ch

Rx 1.25GBps x 3ch
FPGA nP
SE2PROM
HOST
Manag
CONT
DATA
CONT
RGGI

ADDRESS
RGGI

ADDR
Packet Memory

network Processor: Rx
Tx
DATA
Validation
DATA
CONT Frame classification, ADDRESS Search Memory
editing and buffering CONT
PHY
Manag
SMII
SMII

POWER
OPTIC

OPTIC

PHY CARD
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 250. 2GBA–PR Card Functional Block Diagram

The 2 GbE interfaces are hosted by a network processor embedded on the access card.

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Data Path – Ingress


•

Correct Packet Format; Ethernet frame format as per IEEE 802.3 including:

• 802.3
• 802.1Q

• Packet Size

• Valid CRC

The network processor processes only valid frames and discards the invalid frames. The first stage of
processing is packet classification. Frame classification is used to identify:–

• The service to which this frame belongs. Frame destination or set of destinations depends on
the service type. This is defined in the provisioning process.
• Identify the frame priority. This will determine the precedence and delay with which it will be
forwarded to the ISA–PR port card. Frames will be classified into one of three available CoS
(Class of Service) queues defined as high, medium or low.

For further information with regard to service definitions and QoS mechanisms in the ISA–PR, please refer
to 3.7 on page 245 and 4.35 on page 508.

Following frame classification, the network processor performs frame editing. Frame editing refers to the
appending or swapping of a tag for identification purposes. The following functions are currently
supported.

• Append MPLS tag to identify the service and priority to which the frame belongs. This
information is used by other network elements in network – always
• Strip Martini header – optional
• Append, Swap or Strip VLAN – optional

The network processor forwards validated and edited frames to the port card (ISA–PR) for transmission
to the destination access cards. Payload information is passed between the access card and port card
via two 1Gbps backplane channels.

Data Path – Egress
The first part of the egress process takes part on the port card. For further details, please refer to and
4.35 on page 508.

Frames that have been designated for delivery to client ports are delivered from the port card to the
relevant access card over two 1Gbps backplane channels.

The network processor handles the buffering of frames until they can be forwarded over the appropriate
Ethernet interface. Delivery of frames is according to bandwidth availability and frame priority.

Prior to emitting a frame network processor applies frame editing as follows:

• Strip MPLS tag, which has been used to identify the service and priority to which the frame
1AA 00014 0004 (9007) A4 – ALICE 04.10

belongs at the ring – always
• Append Martini header – optional

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Performance Monitoring
The 16FEA–PR card maintains performance monitoring counters at both Port and Queue levels. At the
Port level these are standard Ethernet counters. At the Queue level these are discard counters.

Control

The 2GBA–PR card is managed via a controller hosted on the ISA–PR port card.

On the front plate, two LEDs give an alarm indication for the card as specified in the table below.

Table 52. 2GBA–PR card LED designation

ON = Minor
OK YELLOW
ON = Major/Critical
Blinking 50/50 = during the POST (Power On Self Test) failure. On
OK RED POST completion the LED will change its color according to the card
status afterwards
ON = OK Status
OK GREEN Blinking 50/50 = during init
Blinking 20/80 = card is unassigned, i.e. not yet approved by NMS

Physical Interfaces
The 2GBA–PR access card front view is shown in Figure 73. on page 162

A full listing of the interface characteristics can be found in section 5.5.3 on page 611.
There are two Ethernet interfaces available which offer a standards compliant Optical Gigabit Ethernet.
Small form factor pluggable connectors enable the support of both 1000–Base–LX and 1000–Base–SX
standards.

Each Ethernet interface has LED indications specified in the table below

Table 53. 2GBA–PR interface LED designation

LED name State Designation

Link Green Link up

Link red Any port related alarm

Power

The access module receives a 7v DC supply from the port card, which is used to power the components.
1AA 00014 0004 (9007) A4 – ALICE 04.10

Other voltages required are generated on the card itself.
The power consumption of the 2GBA–PR Fast Ethernet Access card is 22 Watts.

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4.13 Optical booster (BST10, BST15, BST17)

The Booster unit is utilized when it is necessary to get longer span; it is intended for long haul applications,
increasing link budget.

Up to eight Booster units can be inserted in the Access Area of 1660SM equipment.

The Booster can differ by output optical power values: +10 dBm, +15 dBm and +17dBm (minimum).
The optical connectors FC/PC or SC/PC are accessible on the unit’s front coverplate.

The unit provide a non–regenerative direct optical amplification (i.e. without any intermediate
optical/electrical conversion) in the 1550 nm window.
The optical signal transmitted from the port to the Booster, is amplified and then transmitted towards the
external line.

The interconnection between Booster and port is realized on the unit front optical connectors by means
of supplied optical cable.

In addition to the main function the unit will provide the following features:

• Built in WDM coupler ;
• Operation monitoring and alarm generation;
• Analogue to digital converters for operating parameters measurement;
• Built in protection capabilities to address optical safety issues;
• Front panel led indicators for status and fault monitoring;
• Management of Automatic Laser Shutdown (ALS) according to ITU–T G.664 recommendation.

Three optical connectors on the front panel of the unit will be used for (see Figure 251. on page 414):

• Input of not amplified signal from optical port;
• Output of amplified signal + supervision signal (not amplified) to line.

booster from
module port
to + WDM
line coupler

BOOSTER

optical connector
FC/PC or SC/PC

Figure 251. BSTxx – optical block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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The unit has the following building blocks (see Figure 252. on page 417).
Power and reference circuitry

The unit has a direct power supply from battery voltage on backplane: nominal value in the range –48 V

to –60 V.

Devoted to:
• Input of main power supply with fault protecting circuitry
• DC/DC conversion from battery voltage to 5.2 V and 3.3 V main on board power supplies (with
fault protecting circuitry and synchronizing oscillator)
• DC/DC conversion from 5.2 V and 3.3 V main power supplies to –5.2 V, +2.5 V, –3.3 V auxiliary
power supplies (with overvoltage protecting circuitry)
• Voltage reference generation
• Power supplies alarm detection
Compact OFA module

Optical fibre amplifier module, an hybrid module of the Alcatel Optronics 1900 OFA family, acting as optical
gain device with built–in input and output power monitoring photodiodes.
Main components are:
• Photodiode for monitoring of input power (fed by a coupler extracting a small fraction of light
from the main optical path)
• Input optical isolator (preventing pump power and amplified spontaneous emission to exit from
input port)
• A length of Erbium doped active fibre
• Pump laser (operating at 980 nm) to generate optical pumping power
• A WDM coupler to insert pumping power into active fibre
• Output optical isolator to prevent external reflections (assuring stable operation of the OFA)
• Photodiode for monitoring of output power (fed by a coupler extracting a small fraction of light
from the main optical path)
Control block

Mixed analogue and digital circuitry (with a DSP microprocessor) devoted to control:
• Pump laser temperature
It should be stabilized in a small range around nominal value; the thermistor in OFA module is
used for temperature sensing of the laser, and a Thermo Electric Cooler/Heater (TECH) driven
by a current source/sink circuit is used for temperature control.
DSP processor can monitor TECH current via a sensing resistor, a differential amplifier and A/D
converter.
• Optical output power
It should be stabilized around target value +10 dBm; output photodiode in OFA module is used
for sensing of output power, and the current of pump laser is adjusted consequently. Moreover
input power to OFA module is monitored via input photodiode, a transimpedance amplifier and
A/D converter.
Main functions of the block are:
• Conditioning (i.e. level adjusting, buffering, and so on) of analogue signals from sensors internal
or external to OFA module
• Analogue to digital conversion of the conditioned signals
1AA 00014 0004 (9007) A4 – ALICE 04.10

• Digital implementation of control logic in DSP microprocessor, to generate control signals
• Digital to analogue conversion of control signals towards current sources
• Current source circuits toward OFA module (laser diode current and TECH current)

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Information processing

Information about state of the board is mainly processed by the DSP.
The main processes are:

•

Alarm detection

Alarms related to optical signal or OFA module are detected and processed by DSP; a few
alarms related to HW in the board are detected by dedicated circuitry. All alarms are made
available to external interface block.
• Measurement collection
Measures of optical and electrical parameters are collected by DSP and made available to
external interface block.
• Configuration and provisioning management
Configuration and provisioning information from shelf controller via external interfaces are
managed mainly by DSP.

External interfaces

The following interfaces will be implemented:
• Serial peripheral and inventory (SPI)
The SPI bus will be used by the main shelf controller to acquire remote inventory data; the same
bus is used by the main shelf controller to interface DSP processor. Data transfer over the SPI
bus is controlled by the main shelf controller; the other cards operate as slaves.
The SPI bus is duplicated on each shelf: each slave card is connected to both the main and the
spare SC processor through a dedicated bus.
The Optical Booster houses also the RIBUS I/F block the function of which is described on
paragraph 3.17 on page 370 and the Remote Inventory.
• Unit led interface
Two led are on the front panel of the unit:
– a bicolor red/green led acting as:
• red: internal failure indication;
• green: active unit indication;
– a yellow led acting as shutdown indication (i.e. no amplification of optical signal).

Optical safety and shutdown handler block

Since optical power levels emitted by the booster can damage the human eye, the unit will have to be
compatible with IEC standards 825–1 and 825–2, intended to protect users against optical radiation.
As protection mechanism, in the event of potential danger, an automatic shutdown will be supported.
Automatic shutdown will be implemented in the case of:

• Cover open (according enable from shelf controller)
• Loss of input signal

A single section automatic laser shutdown procedure will be implemented according G.664
recommendation; a shutdown command will be sent also to optical service unit as a consequence of
detection of loss of input signal in preamplifier and optical service unit. Restart pulses (time duration not
higher than 400 ms) will be implemented by the booster (both automatically and manually).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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OFA module

INPUT INPUT WDM ERBIUM OUTPUT OUTPUT
MONITOR ISOLATOR COUPLER DOPED ISOLATOR MONITOR
FIBER
FROM TO
PORT LINE

IP PUMP AUTOMATIC OP
TEMPERATURE PUMP POWER
CONTROL LASER CONTROL

TEMP. I PUMP

COVER LASER
REMOVAL SHUTDOWN
D/A conv. A/D conv.
COPEN LOS IN SD

IP
OP ALARMS DSP
GENERATION ALARMS
I PUMP
alarms control
TEMP.

control block

PW ALM

5V
–48/–60 POWER SUPPLY
BLOCK 3,3V
+2,5V
COPEN
FAIL

SD

REMOTE RIBUS
RIBUS
INVENTORY I/F
to/from
MATRIX

OPTICAL BOOSTER card
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 252. BSTxx – card block diagram

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4.14 Optical 2.5 Gbit/s Preamplifier (PR16)

General features

The unit will provide a non–regenerative direct optical amplification before the receive host system (i.e.
without any optical–to–electrical–conversion) in the 1550 nm window.

Target: output power level provisionable at –13.5 dBm.

It is intended for single channel applications, its output goes to a STM–16 port (RX) L16.2 JE3–CH34
interface, increasing link budget.
No WDM applications are provided.

In addition to the main function the unit will provide the following features:

• operation monitoring and alarm generation
• analogue to digital converters for operating parameters measurement
• built in protection capabilities to address optical safety issues
• front panel led indicators for status and fault monitoring
• management of Automatic Laser Shutdown (ALS) according to ITU–T G.664 Rec.
• on–line SW download (i.e. in–field download of new DSP SW releases without affecting the
optical signal)

Two optical connectors on the front panel of the unit will be used for:

• input of not amplified signal
• output of amplified signal

Two LED will show:

• a green/red LED: proper working in the system (or download in progress)
• a yellow LED: shutdown monitor to valuate laser current state

For the description of this unit refer to Figure 253. on page 423 and Figure 254. on page 424.

The unit has the following building blocks.

Power and reference circuitry

Devoted to:

• input of main power supply (DC battery voltage at 48/60 V nominal value), with fault protecting
circuitry;
• DC/DC conversion from battery voltage to 5.2 V and 3.8 V main on board power supplies (with
fault protecting circuitry and synchronising oscillator);
• DC/DC conversion from 5.2 V and 3.8 V main power supplies to –5.2 V, +15V, –15 V auxiliary
power supplies (with overvoltage protecting circuitry);
• voltage reference generation;
• power supplies alarm detection.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Compact OFA module (EDFA)

Optical fibre amplifier module, is an hybrid module of the Alcatel Optronics 1900 OFA family acting as
optical gain device with built–in output power monitoring photodiode.

Main components are:

• input optical splitter (90/100) to tap out of the module a fraction of the input power;
• photodiode for monitoring the output power (fed by a coupler extracting a small fraction of light
from the main optical path);
• input optical isolator (preventing pump power and amplified spontaneous emission to exit from
input port);
• a length of Erbium doped active fibre;
• pump laser (operating at 980 nm) to generate optical pumping power;
• a WDM coupler to insert pumping power into active fibre;
• output optical isolator to prevent external reflections (assuring stable operation of the OFA).

Optical Power Monitoring (OPM)

On a doughter board plugged in the OFA module are positioned the input power monitor photodiode and
a “tap–detector”, used to detect the output power level. The photodiode currents are locally transduced
in voltage signals by log amplifiers.

The output of the OFA goes directly to an optical passband filter, used to suppress the ASE noise outside
the transmitting band. The ouput of the filter goes to the output connector passing through a
coupler+photodiode for monitoring the power level.

Control block

Mixed analogue and digital circuitry (with a DSP microprocessor) devoted to control:

• Pump laser temperature.
Pump laser temperature should be stabilised in a small range around nominal value; the
thermistor in OFA module is used for temperature sensing of the laser, and a Thermo Electric
Cooler/Heater (TECH) driven by a current source/sink circuit is used for temperature control.
DSP processor can monitor TECH current via a sensing resistor, a differential amplifier and A/D
converter.

• Optical output power.
Output power is stabilised at –13.5 dBm; external tap photodiode is used for sensing of output
power, and the current of pump laser is adjusted consequently. Moreover input power to OFA
module is monitored via input photodiode, a log amplifier to give a wide dynamic range of 50
dB, and A/D converter.

Main functions of the block are:

• conditioning (i.e. level adjusting, buffering, and so on) of analogue signals from sensors internal
or external to OFA module;
• analogue to digital conversion of the conditioned signals;
• digital implementation of control logic in DSP microprocessor, to generate control signals;
• digital to analogue conversion of control signals towards current sources;
1AA 00014 0004 (9007) A4 – ALICE 04.10

• current source circuits toward OFA module (laser diode current and TECH current).

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Information processing

Information about state of the board is mainly processed by the DSP.

The main processes are:

• Alarm detection.
Alarms related to optical signal or OFA module are detected and processed by DSP; a few
alarms related to HW in the board are detected by dedicated circuitry. All alarms are made
available to external interface block.

• Measurement collection.
Measures of optical and electrical parameters are collected by DSP and made available to
external interface block.

• Configuration and provisioning management.
Configuration and provisioning information from shelf controller via external interfaces are
managed mainly by DSP.

External interfaces

The following interfaces will be implemented:

• Serial peripheral and Inventory Bus (SPI).
The SPI bus will be used by the main shelf controller to acquire remote inventory data; the same
bus is used by the main shelf controller to interface DSP processor. Data transfer over the SPI
bus is controlled by the main shelf controller; the other cards operate as slaves.
The SPI bus is duplicated on each shelf: each slave card is connected to both the main and the
spare SC processor through a dedicated bus.

• Unit LED interface.
Two LEDs are on the front panel of the unit:
– A bicolor red/green LED acting as:
• Red: internal failure indication
• Green: active unit indication
– A yellow LED acting as shutdown indication (i.e. no amplification of optical signal).

Optical safety and shutdown handler block

Since optical power levels emitted by the preamplifier can damage the human eye, the unit will have to
be compatible with IEC standards, intended to protect users against optical radiation.

As protection mechanism, in the event of potential danger, an automatic shutdown will be supported.
Automatic shutdown will be implemented in the case of:

• cover open (according enable from shelf controller)
• loss of input signal

A single section automatic laser shutdown procedure will be implemented according G.664 Rec.
Restart pulses (time duration not higher than 300 ms) will be implemented.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Optical interfaces parameters

Main items are:

•

FC/PC or SC/PC optical connectors

• Wavelength bandwidth (main signal): 1530 to 1565 nm
• Input power: –38 dBm to –18 dBm (@ BER ≤ 10E–10)
• Output power: –14 dBm (to be connected to a JE3–CH34 optical receiver)

Measures

A measure of the following analogue parameters will be available to operator (by craft terminal or operating
system) via shelf controller and equipment controller:

• Pin: optical power at the input connector
• Pout: optical power at the output connector
• Rel_Ip: relative I_pump; percentage ratio of actual I_Pump to I_Pump measured at begin of life

Alarms

The following alarm flags will be available to network operator (by craft terminal or operating system) via
shelf controller and equipment controller:

• ILoS: Input Loss of Signal: loss of power on input connector.
Activation threshold –44 dBm, deactivation threshold –42 dBm; threshold accuracy ±0.5 dBm
Activation/deactivation time: 10 ms max
Consequent actions: shutdown of pump laser and stop of the filter control
Classification: external urgent alarm

• Ideg: Input Degrade: low power on input connector.
Activation threshold –41 dBm, deactivation threshold –40.5 dBm; threshold accuracy ±0.5 dBm
Activation/deactivation time: 50 ms max
Consequent actions: none
Classification: external not urgent alarm
Masked by IloS.

• LaserDeg: Laser Degrade: logic “or” of relative and absolute degrade:
– relative degrade: actual pump current higher than 1.2 * pump current measured at begin
of life;
– absolute degrade: actual pump current higher than warning threshold level.
Activation/deactivation time: 10 sec max
Classification: internal not urgent alarm
Traffic not affected
Actions required to operator: unit replacing (preventive maintenance)
Masked by Input deg

• HW Fail: Logic “or” (at the shelf controller level) of the following alarms:
– Ex_Pout
– Ex_Ipump
– Ex_ITEC
1AA 00014 0004 (9007) A4 – ALICE 04.10

– Wr_Vref
Classification: internal urgent alarm

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Traffic will be affected
Actions required to operator: quick unit replacing

• PW Fail: Power supply/reference voltage circuits failures.

Consequent actions: shutdown of pump laser and TECH

Classification: internal urgent alarm
Traffic affected
Actions required to operator: unit replacing

• PuShd: Pump Shutdown: pump laser off (zero current)

• Cover_Op: Cover Open: access fibre protective cover removed
May force or not pump shutdown (according CoREn configuration control)

SPI Interface

The main interface between preamplifier unit and shelf controller is the standard SPI serial bus.

This interface is managed on the board by the Spider ASIC, acting as Slave Interface and signal buffer;
some pins of the Spider are used as I/O parallel ports.

On the internal SPI bus two other devices are connected:

• serial EEPROM for remote inventory informations
• DSP microprocessor

A direct connection between shelf controller and DSP microprocessor (or serial EEPROM) can be
established by Spider (acting as chip select decoder, electrical interface and protocol adapter).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
to

03
line

port
from

Ipump

Itech

Filter–CH34
Temp
EDFA gain block

Figure 253. PR16 optical path and control signal
OPM

PR16 main board

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OUTPUT
To STM–16 PORT)

DATA CONTROL
FLASH
General MEMORY

INPUT gain block type Purpose Shutdown
(From Line) I/O
cover open VREF

I_Pump
ok alim
VREF
D/A

DSP CONVERTER
P_out I_TEC
Thermistor
I_Pump A/D
I_TEC_N CONVERTER
I_TEC_P
P_in

Config.
Status Management
Bus
M–BUS
Driver
Shutdown

MAIN AND SPARE
Bus–OFF

MATRIXE
FROM/TO
Remote
SHUTDOWN Inventory

300 KHz
CMISS
OSC RIBUS
cover open
I/F
ok alim RIBUS
5V
ok alim
–5 V F + 3.3 Vdc
CONGI A B

3.3 V DC/DC
FROM

Unit ID
CONVERTERS
–3.3 V Failure
48/60 V
2.5 V

OPTICAL PREAMPLIFIER 2.5 GB/S (PR16)
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 254. PR16 card block diagram

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4.15 Electrical module (ICMI)


The electrical module can be housed in the Access card A2S1 and port cards P4E4N ,P4S1N, .

Up to two modules can be housed in each card.
The module contains :

– a CMI interface (CMI/NRZ decoder and NRZ/CMI encoder)

– a Remote Inventory block

CMI interface

INPUT side: the CMI electrical signal coming from the line is equalized and NRZ decoded (clock + data).
The LOS alarm is revealed.

OUTPUT side: the NRZ signal coming from the port (data + clock) is CMI coded to be sent to the line.

Loop functions

The module receive also the following commands:

– INT LOOP: Internal Loop ; when active, the signal coming from the port card (DT) is sent back, thus
realizing the loop.
– LINE LOOP: Line loop; when active the input signal coming from the line (DR) is sent back to the
output signal.

Remote inventory

The Remote inventory is implemented on an E2PROM . Inventory data as code, series number,
construction date are stored inside the E2PROM and can be read by the RIBUS I/F block (see para.3.17
on page 370) of the board in which the module is inserted.

Power Supply

The Electrical module receive the following voltage:

– +3.3 Vdc from the relevant board in which is inserted
– + 3.3 Vdc (Vs) from the relevant board in which is inserted and used to supply the Remote Inventory
block
1AA 00014 0004 (9007) A4 – ALICE 04.10

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LOS
Coax Input CMI
RETIMER DATA+CLOCK Rx
NRZ
DR
INT LOOP1
DT

Input side

DR
DT

Coax output CMI
Mask DATA+CLOCK Tx
Adapter NRZ
LINE LOOP1

Output side

CMISSn

Remote RI
to RIBUS I/F block
Inventory
+3.3 Vdc (Vs)

ELECTRICAL MODULE +3.3 Vdc

Figure 255. STM–1 Electrical module –block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.16 STM–1 optical modules


The STM–1 optical modules are the optical physical accesses for the STM–1 card. Different optical

modules are available according to the connector type used (FC/PC, SC/PC or LC), wave length ( IS–1.1,
L–1.1, L–1.2, L–1.2JE) and source type [Single–Mode and Multi–Mode (MM1)]. For details on Optical
Characteristics refer to Table 66. on page 628)
Input side : the optical signal is converted in an electrical signal and level adapted to be sent to the port
card (data + clock); on the receive side a LOS alarm can be detected.
Output side : the electrical signal coming from the port card (data + clock) is level adapted, converted
in an optical signal and sent to the line . The Tx optical module send and receive also the following signals:

– LASER FAIL
– LASER DEGRADE
– LASER SHUTDOWN
Remote inventory

The Remote inventory is implemented on an E2PROM . Inventory data as code, series number,
construction date are stored inside the E2PROM and can be read by the RIBUS I/F block (see para.3.17
on page 370) of the board in which the module is inserted.
Power Supply

The Electrical module receive the following voltage:

– +3.3 Vdc from the relevant board in which is inserted
– + 3.3 Vdc (Vs) from the relevant board in which is inserted and used to supply the Remote Inventory
block

EDR
OPTICAL LEVEL DATA+CLOCK RX
STM–1
INPUT INPUT ECKR ADAPTER
OPTICAL
MODULE
LOS

OPTICAL EDT
OUTPUT ECT LEVEL DATA +CLOCK TX
STM–1 ADAPTER
OUTPUT
OPTICAL LASER FAIL
MODULE
LASER DEGRADE
LASER SHUTDOWN

Laser Restart Remote RI to RIBUS I/F bus
Inventory
+3.3 Vdc (Vs)

+3.3 Vdc

STM–1 CMISSn
1AA 00014 0004 (9007) A4 – ALICE 04.10

OPTICAL MODULE

Figure 256. STM–1 Optical module – block diagram

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4.17 STM–4 optical modules

See Figure 257. on page 428.

The STM–4 optical modules are the optical physical accesses for the STM–4 card (only for 4 x STM–4

port, P4S4N).

Different optical modules are available according to the connector type used (FC/PC, SC/PC or LC) and
wavelength (IS–4.1, L–4.1, L–4.2).
For details on Optical Characteristics refer to Table 67. on page 630.

The optical module can be housed in the Access cards A2S4 and in the port card P4S4N.
Up to two modules can be housed in A2S4 and P4S4N.

Each module contains two optical components (Tx and Rx), two level adapter, the remote inventory and
the Laser reset button.

OPTICAL
INPUT
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌRX
EDR
DATA IN
Level
Optical Module
ÌÌÌÌÌÌÌ ECKR Adapter CLOCK IN
ÌÌÌÌÌÌÌ
LOS

ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
EDT
ECT Level
DATA OUT

OPTICAL Adapter CLOCK OUT
TX
OUTPUT
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌOptical Module

ÌÌÌÌÌÌÌ Laser Fail
Laser Restart Laser deg.

Shutdown

Remote to RIBUS I/F bus
Inventory

STM–4 Optical module
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 257. STM–4 optical module block diagram

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4.18 4 x ANY plug–in modules

The 4 x ANY plug–in optical modules are the optical physical accesses for the 4xANY HOST C card.
Different optical modules are available according to the wavelenght and signal type to be transported

(refer to Chapter 2.2.1 page 98)

For the block diagram description refer the 4xANY HOST–C card (paragraph 4.45 on page 549 ).
The relationship between client signal to be transported and plug–in module type is reported on Table 40.
page 293.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.19 SFP optical modules: 1000B and 100B


Two types of SFP optical modules are foreseen in current release

– the 1000B optical module, providing 1000Base–SX, 1000Base–LX and 1000Base–ZX interfaces
– the 100B optical module, providing the 10/100Base–FX interface.

The 1000B optical module, provides the optical physical access for the (see Figure 80. on page 169)
– GigaBit Ethernet port card, GETH–MB
– Gigabit Ethernet Access Card, GETH–AG, used in conjunction with the ETH–MB
– PR_EA MATRIX 1 x GIGABIT ETHERNET port card, PREA1GBE
– Ethernet Switch port card, ES4–8FE.

The 100B optical module, provides the optical physical access for the (see Figure 80. on page 169)
– Ethernet Switch port card (ES1–8FX).

These modules implement the PMD (Physical Medium Dependent) and the PMA (Physical Media
Attachment Sublayer) functions according to IEE 802.3.

Each module contains on transmitter side an automatic optical output power control circuit, a laser driver
and a laser diode module.
The transmitter is based on an uncooled DFB laser.
The laser safety class for the complete integrated module is CLASS 1 according to IEC 60825 2001 Edition.
It can manage command for TX disable and provides TX Fault alarm.
Depending on the SFP type, the optical access is compatible with
– a single mode fiber (9/125 µm) or
– multi mode fiber (50/125 µm or 62,5/125 µm)
with standard LC optical connector.
TX Fault indicates a laser fault of some kind. The Transmitter is not disabled when TX Fault signal is active.
Tx Disable is an input that is used to shut down the transmitter optical output.

On receiver side each module contains a PIN or APD photodetector (according to the module type) for
light to electrical current conversion and a limiting amplifier.
The photo detected current is amplified by a an electrical circuit which delivers two complementary data
signals.
The module provides LOS alarm (Loss of input Power Signal alarm). This output signal indicates the
received optical power is below the worst–case receiver sensitivity (as defined by the standard in use).
Depending on the SFP type, the optical access is compatible with
– a single mode fiber (9/125 µm) or
– multi mode fiber (50/125 µm or 62,5/125 µm)
with standard LC optical connector.
Remote inventory

The Transceiver has an EEPROM inside to provide Remote Inventory, containing information about
transceiver’s capabilities, standard interfaces, manufacturer, code, series number, construction date etc.
These information are read by the “Alarms and Remote Inventory Management” block (see para.3.17 on
page 370) of the board in which the module is inserted.

Digital diagnostic monitoring (DDM) is an SFP function supporting analog parameters measurements as
temperature, laser bias, laser power. It is an optional feature: the availability information is present in the
SFP remote inventory.
1AA 00014 0004 (9007) A4 – ALICE 04.10

Power Supply

The Electrical module receives the +3.3 Vdc from the relevant board in which is inserted.

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To board
processing TRANSMITTER
LC

PIN Laser

diode Optical output

DATA+
LASER
Electrical DATA DRIVER
DATA–

APC TX Fault

TX Disable

Remote Inventory / DDM
EEPROM

µP

RECEIVER

DATA+ LC
Main PRE PIN*
Electrical DATA Amplifier Optical input
DATA–

LOS

SFP Optical Module

* PIN or APD according to the SFP type

Figure 258. SFP optical modules general block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.20 63 x 2 Mbit/s port card (P63E1)


The P63E1 is a bidirectional unit which interfaces 63 plesiochronous 2048 kbit/s signals and the

STM4–BPF signal (BPF=backpanel format).
Due to the backpanel format (STM4–BPF or STM4*), the 63 plesiochronous 2 Mbit/s signals that can be
housed in an STM–1 frame, are dropped / inserted in the AU4#1 of the STM–4* frame.
The unit is composed by the following blocks:

– (G.A.)
G.A. is an ASIC (or Gate Array) that maps 63 2Mbit/s streams into an STM–1 frame as required by
ITU–T G.783 Rec.
As the backpanel format for data exchange between 63 x 2 Mbit/s and Matrix card is STM–4*, the
2 Mbit/s streams are inserted/extracted on the AU4 #1 of the STM–4* frame.

INPUT side

• PPI (E12_TT_Sk and E12/P12x_A_Sk): This block provides the electrical interface between
the physical transmission medium and the internal unit format. The received 2048 kb/s line
signal is HDB3 coded. A decoder on the physical interface decodes the signal to NRZ (non
return–to–zero) format.

• LPA (S12/P12x_A_So) : This block adapts user data for transport in the synchronous
domain. For asynchronous user data, lower order path adaptation involves bit justification. The
2.048 Mbit/s is inserted into a C–12 container (by means of asynchronous mapping), which is
synchronized (stuffing) with the correspondent TU–12.

• LPT (S12_TT_So) : The LPT function creates a VC–12 by generating and adding POH to a
C–12. The POH formats are defined in Recommendations G.708 and G.709.

• LTCT So : This block performs Tandem Connection Termination and Adaptation Source
functions, according to ITU and ETSI standards, on Low Path tributaries. It inserts into incoming
Low order VC the N2 byte, and performs BIP–2 parity compensation for that byte insertion. The
inserted N2 is composed by remote signalling, incoming error count, APId.

• STM4–BPF I/F () :
The STM–1 equivalent signal is multiplexed into the Back–Panel STM4* equivalent signal.
The signal is sent to the ”Main” and ”Spare” MATRIX cards .

OUTPUT side

• EPS :
This block select one of the two signal source provided by the MATRIX cards ”Main” and ”Spare”

• STM4–BPF I/F () :
1AA 00014 0004 (9007) A4 – ALICE 04.10

The STM–1 equivalent signal is demultiplexed from the Back–Panel STM4* equivalent signal.

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• LTCT Sk : This block performs Tandem Connection Monitoring / Termination and
Adaptation Sink functions, according to ITU and ETSI standards, on Low Path tributaries
(configuration choice between Monitoring and Termination is by preset). It extracts from
incoming Low order VC the BIP–2 parity and N2 byte, and then operates alignment, detection

and correlation of alarms, error check. When Termination function is configured, it also modifies

data flow by N2 byte overriding, AIS insertion, generation of remote signalling.

• LPT (S12_TT_Sk): The LPT function terminates and processes the POH to determine the
status of the defined path attributes.

• LPA (S12/P12x_A_Sk): It extracts the VC12–POH and processes the TU12 pointer.
detection

• PPI (E12/P12x_A_So and E12_TT_So):This block provides the interface between the
internal unit format and the physical transmission medium. It encodes into HDB3 code the signal
to be sent on line.

Other functions implemented are :

• Clock Reference Selection Block (on G.A): provides six 2 MHz clock links towards the
MATRIX cards for synchronization purposes. The selection among the 63 flows is made via
software.

• TIMING (on G.A): receives the reference clock (38.88 MHz) and synchronism pulse (500 Hz)
from the MATRIX cards and extracts the local clocks used by the G.A.
The Tx clock is locked, by means of a PLL to the system clock or, when in free running, to a local
oscillator with a +–50ppm drift: (51 MHz OSC) block.

• RIBUS I/F
This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the unit, to
release the Management–bus in case of power failure, and to use the remote inventory. It is
powered by the + 3.3 Vdc supply by CONGI boards.

• REMOTE INVENTORY
It is the memory containing the board information, for identification purposes (see para. 3.17
on page 370 for details).

• M–BUS Driver
It drives the input–output gates of the Management–bus. These drivers can be disabled (by
the Bus–OFF signal) in case of power failure.

• DC/DC CONVERTER
It converts the 48/60 V power supply to the 3.3 V used to supply all the components in the board.
The DC/DC converter is synchronized with a synchronization clock at 288 MHz (signal
Power–Sync, generated by G.A.) in order to avoid EMI problems.
1AA 00014 0004 (9007) A4 – ALICE 04.10

• STEP DOWN
It uses the 3.3 V power supply from DC/DC Converter block to obtain the 2.5 V used to power
the Gate Array (G.A.).

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2Mb/s
inputs ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
2Mb/s #1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input side

LTCT
#1
PPI
sink
LPA
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ source
.
LPT
source source

ckr1 .
.
. ckrx
.
Access Card

.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
. .
. STM4
. .

Main and Spare
BPF
.
from

.

MATRIXE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ I/F
.
.
.

to
Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
2Mb/s #63 ckr1 Clock
#63 Reference 6x
ckr63
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ckr63 ckrx Selection

2Mb/s
outputs
ÎÎÎÎÎ
2Mb/s #1
ÎÎÎÎÎÎÎÎÎÎ Output side

PPI LPA LPT LTCT
#1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
source
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ sink
ÎÎÎÎÎÎÎÎÎÎÎÎÎ sink sink
Access Card

cktx ckt1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ .
.
.
. .
to

. .
.
STM4
EPS
.
.
BPF
I/F

Main and Spare
MATRIXE
#63
ÎÎÎÎÎÎÎÎÎ
2Mb/s #63

from
cktxÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ckt63
ckt1 ckt63
Local Clocks
ck–system a
ckrx TIMING ck–system b
G.A. cktx

Config. Status
Power 2.5 V 51MHz
Sync
STEP OSC M–BUS
DOWN Driver
Management
48/60 V DC/DC Bus
CONGI A B

CONV.
3.3 V
from

Bus–OFF CMISS
MATRIXE
to/from

F + 3.3 Vdc

Remote
Inventory
RIBUS RIBUS
I/F

63 x 2 MBIT/S PORT CARD Unit ID
Failure

Figure 259. 63 x 2 Mbit/s card – Block Diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 434 / 706

706

4.21 63 x 2 Mbit/s / G703 / ISDN–PRA port card ( P63E1N–M4)


The 63 x 2 Mbit/s /G.703/ISDN–PRA port is similar to the basic 63 x 2 Mbit/s port, described in the previous

paragraph 4.20 on page 432, with the difference that the present board implements also the NT
functionality on ISDN Primary Rate Access (PRA) and the “Retiming function” on the 2 Mbit/s interfaces.

The Retiming function applies the Equipment Clock to the outgoing 2Mb/s signal that therefore becomes
synchronized with the SDH network synchronization reference .

The additional circuit that allows this implementation consists in an elastic buffer that is able to absorb the
jitter and wander that is transferred to the PDH signal when SDH pointer justification occurs.

This feature is programmable via SW, in order to include or exclude the Retiming for each single port. The
same P63E1N unit can mix ports that apply or not the retiming.

In this paragraph is reported the description of the NT ISDN–PRA function, all the other blocks
functionalities are described in the previous paragraph 4.20 on page 432.

The ISDN–PRA (Integrated Services Digital Network – Primary Rate Access) is a facility to carry a number
of synchronous digital communication channels to the user over a 2048 kbit/s structured signal; the
ISDN–PRA structure is defined in recommendation ETS 300 233. The sample frames are reported in
paragraph 3.18.1, page 380 up to para. 3.18.1.2, page 382.
The 2048 kbit/s signals can be structured or non–structured: in this latter case, the PRA functionality must
be disabled from Craft–Terminal. The selection among structured/non–structured and
basic–frame/multiframe options is achieved by means of Craft–Terminal, for individual signals.
It performs standard PRA functionality as well as some custom Leased Line functions (settable from C.T.).

Figure 261. on page 439 illustrates the NT ISDN–PRA block, that performs the following functions:

UPSTREAM DIRECTION
(from user to SDH network: incoming signal SY2Min, outgoing signal UP2Mout)

– Loopback2: by means of command LB2, sent by the controller, or detected in the Sa6 message
coming from the SDH network (UP2Min signal); this command sends back to the source the
upstream signal.

– AIS Detection: the AIS alarm (AIS2M) is detected after the reception of 512 bits containing less than
3 zeroes.

– Frame Alignment (FA): it performs basic–frame and multi–frame alignment according to ITU–T
G.706, presettable from the controller (commands BF and MF); the LOF2M alarm is declared in case
of non alignment .

– Failure Condition: the Failure Condition FC2M alarm is the “OR” of LOS2M, LOF2M , AIS2M alarms.

– REI alarm detection (E): the REI2M alarm is detected if E=0.

– RAI alarm detection (A): the RAI2M alarm is detected if active for 5 consecutive frames.

– Data Error detection (CRC–4): errors integrity check on the incoming data, according to CRC–4
procedure (Cyclic Redundancy Check), as defined in G.706. In case of errors, the alarm ERR2M is
arised.
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 435 / 706

706

– E bit insertion (E): the outgoing E bit is set to 0 when
• a failure condition (FCU) is detected on signal from SDH network (UP2Min);
• errors (ERRU) are detected on data from SDH network (UP2Min);
• the E insertion may be inhibited from controller, in this case E=1.

• E=1 in other cases.

– A bit insertion (A): the outgoing A bit is set to
• ’0’ when a failure condition (FC2M) is detected on signal from user (SY2Min);
• ’1’ when Loopback2 (LB2) is activated;
• passed transparently in other cases;
• the A bit may be forced from controller.
• set to ’1’ (*) when a failure condition (FCU) is detected on signal from SDH network (UP2Min);
N.B. (*): this option is enabled only in case of Leased Line applications;

– Sa5, Sa6 Messages:
• the outgoing Sa6 message is inserted in 4 Sa6 bits of 4 consecutive frames, with the following
significance (listed in order of their priority/severity):
– 1000 –– power fail
– 1111 –– SSF or AUXPU/AISU on signal from SDH network (UP2Min);
– 1110 –– LOFU on signal from SDH network (UP2Min);
– 1100 –– FC2M on signal from user (SY2Min);
– 0000 –– loopback2 (LB2) activated
– 0001 –– alarm REI2M from user
– 0010 –– CRC–4 errors (ERR2M) from user
– 0011 –– simultaneous occurrence of both previous (REI2M and ERR2M)
– 0011 –– only basic–frame alignment on SY2Min signal, when in automatic search
– 0000 –– normal operations.
• the outgoing Sa5 bit is set to:
– ’0’ –– when loopback2 (LB2) is activated
– ’1’ –– in other cases.

– CRC–4 bits insertion: the CRC–4 on data is performed and the result is inserted on bits C1 to C4,
according to G.706.

– Frame Word insertion (FW): the basic–frame and multi–frame alignment words are inserted on the
frame.

– Substituted Frames insertion: the substituted frames are inserted, in case of occurrence of a failure
condition (FC2M) on incoming signal from user.
N.B. Substituted frame is a frame with Sa4, Sa5, Sa7, Sa8 as well as all the bits in time slots
1 to 31 set to ’1’, and with A bit set to ’0’.

DOWNSTREAM DIRECTION
(from SDH network to user: incoming signal UP2Min, outgoing signal SY2Mout)

– Loopback–RX: by means of command LB–RX, sent by the controller; this command sends back to
the source the downstream signal.

– AIS Detection: the AIS alarm (AISU) is detected after the reception of 512 bits containing less than
3 zeroes.

– AUXP Detection: the AUXPU alarm is detected after the reception of 512 bits containing the pattern
...010101... with less than 3 deviation from the pattern itself. It can be enabled from the controller.
1AA 00014 0004 (9007) A4 – ALICE 04.10

– Frame Alignment (FA): it performs basic–frame and multi–frame alignment according to ITU–T
G.706, presettable from the controller (commands BF and MF); the LOFU alarm is declared in case
of non alignment.

ED 03

3AL 91669 AA AA 436 / 706

706

– Failure Condition: the Failure Condition FCU alarm is the “OR” of SSF, LOFU , AISU, AUXPU alarms.
N.B. SSF =Server Signal Fail, from upstream.

– REI alarm detection (E): the REIU alarm is detected if E=0.

– RAI alarm detection (A): the RAIU alarm is detected if active for 5 consecutive frames.

– Sa6: the Sa6 bit is read for every 4 consecutive frames, to check the presence of the loopback2
command, when 4XSa6=1010, for 8 consecutive times.

– Data Error detection (CRC–4): errors integrity check on the incoming data, according to CRC–4
procedure (Cyclic Redundancy Check), as defined in G.706. In case of errors, the alarm ERRU is
arised.

– A* insertion: the A bit is
• passed transparently in standard applications
• set to ’1’ (*) when a failure condition (FC2M) is detected on signal from user (SY2Min);
• set to ’1’ (*) when forced from the controller;
N.B. (*): this option is enabled only in case of Leased Line applications.

– E bit insertion (E): the outgoing E bit is set to 0 when
• a failure condition (FC2M) is detected on signal from user (SY2Min);
• errors (ERR2M) are detected on data from user (SY2Min);
• the E insertion may be inhibited from controller, in this case E=1.
• E=1 in other cases.
• set to ’0’ (*) when Power Fail alarm (PWF) is active;

– Sa4* insertion: the bits Sa4 to Sa8 are passed transparently in standard applications,
• Sa4 is set to ’0’ (*) when Power Fail alarm (PWF) is active, passed transparently otherwise.

– CRC–4 bits insertion: the CRC–4 on data is performed and the result is inserted on bits C1 to C4,
according to G.706.

– Frame Word insertion (FW): the basic–frame and multi–frame alignment words are inserted on the
frame.

– AIS insertion: a continuous bitstream of all ’ONES’ is inserted, in case of occurrence of
• force command from the controller;
• a failure condition (FCU) on signal from SDH network (UP2Min);
• (*) a failure condition (FC2M) on signal from user (SY2Min).

ALARMS, STATUS AND COMMANDS CONVEYED FROM/TO CONTROLLER
Every alarm, status and errors counting results are reported to the controller, for monitoring purposes:

– LOS, REI, RAI, FC, ERR(CRC–4), SSF detected either in upstream and in downstream signal
directions
N.B. LOS = Loss of user Signal; SSF= upstream Server Signal Fail.

The controller sends the following commands, in order to enable the relevant functions:
1AA 00014 0004 (9007) A4 – ALICE 04.10

– LB–2, LB–RX, BF, MF, ForceA, InhibitE, etc.
N.B. BF= Basic Frame; MF = Multi Frame.

ED 03

3AL 91669 AA AA 437 / 706

706

2Mb/s
2Mb/s #1
Input side

inputs ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
2 Mb/s
POM
NT
PPI ISDN LPA LPT LTCT
#1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
sinkÎ PRA
source
source source source .
.
. .
Access Card

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ckr1 . ckrx STM4
.

Main and Spare
.
. BPF
from

MATRIXE
. I/F
.
.

to
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
2Mb/s #63 ckr1 Clock
#63 Reference 6x
ckr63
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ckr63 ckrx Selection

ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
2Mb/s #1
Output side
2Mb/s
outputs
2 Mb/s
POM
NT
PPI ISDN LPA LPT LTCT
#1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
PRA sink sink sink
Access Card

source sink
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ .
to

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ .
. .
.
STM4
BPF EPS
cktx .
.
ckt1 I/F
.
.

Main and Spare
ÎÎÎÎÎÎÎÎÎÎ

MATRIXE
2Mb/s #63

from
#63
cktx
ÎÎÎÎÎÎÎÎÎÎ
ckt63
ckt1 ckt63
Local Clocks
ck–system a
TIMING
G.A. ckrx
cktx
ck–system b

Config. Status
Power 2.5 V 51MHz
Sync
STEP OSC M–BUS
DOWN Driver
Management
48/60 V DC/DC Bus
CONGI A B

CONV.
3.3 V
from

Bus–OFF CMISS
MATRIXE
to/from

F + 3.3 Vdc

Remote
Inventory
RIBUS RIBUS
I/F

63 x 2 MBIT/S PORT CARD Unit ID
Failure

Figure 260. 63 x 2 Mbit/s G.703/ISDN–PRA, Block Diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 438 / 706

706

1AA 00014 0004 (9007) A4 – ALICE 04.10

ED
To User (downstream)
To SDH Network (upstream)

03
BF MF
SY2Min
FA CRC–4 + + + + + UP2Mout

AIS E A ERR2M
LOF2M E A Sa5, Sa6 CRC–4 FW
Messages FC2M
AIS 2M (*)
LB 2 REI 2M RAI2M
FCU FCU SUBST
FRAMES
FC 2M ERR U FC2M
LOS2M

FC U
PWF

ERR2M
FCU (*) LOFu SSF
FC2M
PWF PWF FC 2M FC 2M LB2 RAIU REIU AUXPu
(*) (*) (*)
AISu
AIS FW CRC–4 Sa4* E A* Sa6 A E AUXP AIS
LBRX
ERR U
SY2Mout
+ + + + + CRC–4 FA UP2Min

BF MF

FC2M REI 2M RAI2M ERR
2M FC U REI U RAIU ERR U LB BF MF

ALARMS STATUS
CONVEYED FROM/TO CONTROLLER

706
3AL 91669 AA AA
FROM/TO

Figure 261. Functional Diagram of the NT ISDN–PRA block
CONTROLLER
EQUICO

439 / 706

4.22 3 x 34/45 Mbit/s port card (P3E3T3)


The P3E3T3 port card is a bidirectional interface from/to three PDH streams at 34 Mbit/s or at 45 Mbit/s

switchable and the STM4–BPF (BPF=backpanel format ).

Due to the back panel format, the 3 plesiochronous 34 or 45 Mbit/s signals that can be housed in an STM–1
frame, are dropped/inserted in the AU4#4 of the STM–4 frame.
It realizes the functions required by the ITU–T G.783 rec. i.e. :

• maps the payload into a C–3
• add/extracts the VC3 POH
• processes the TU3 pointer
• adapts the VC3 to the VC4
• assembles/disassembles the STM–1 format

The SDH functions are preformed by four Gate Array, one for each port and one that is common to the
three ports:

– 34/45 Mbit/s interface

The G.A. performs a fully bidirectional interface for a 34 Mbit/s PDH flow or for a 45 Mbit/s PDH flow in
compliance with the ITU–T G.783.
A G.A. can manage only one stream, therefore three G.A. are necessary to process the 3 streams on the
port card.
The PPI functions is performed by the access card ( two separated according to the bit rate) according
to the ITU–T G.703 Rec.

INPUT side

• LPA (S3/P3_A_So)
Asynchronous mapping of 3x34 /45 Mbit/s into the VC–3
C2 insertion

• LPT ( S3_TT_So)

J1 path trace insertion
G1 (path status) insertion : REI and RDI insertion
B3 calculation and insertion (VC3, BIP8)
F2 and F3 bytes insertion (coming from OH bus and DCC bus)

• LTCA (Low order tandem connection adaptation)

Frame start signal generation on VC_AIS detection

• LTCT (Low order tandem connection termination)

N1processing and insertion (TC–RDI, REI, ODI, OEI ..)
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 440 / 706

706

OUTPUT side
• LPA (S3/P3_A_Sk)
VC3 demapping and desynchronization

C2 monitoring

AIS generation

• LPT ( S3_TT_Sk)
LP–TIM detection (J1 monitoring)
LP–SLM and UNEQ detection (C2 monitoring)
RDI detection
REI recovery
B3 BIP–8 count and error detection
F2 and F3 bytes extraction and sending to AUX* bus and DCC* bus

• LTCA (Low order tandem connection adaptation)
Invalid frame start condition restoration

• LTCT (Low order tandem connection termination)
N1 monitoring and processing
B3 insertion (VC–3 BIP–8 compensation )

– STM–4 timing G.A.
The G.A. provides the following functions:
• to connect the three ”34/45 Mbit/s interface” to the backpanel . In fact the frame format leaving
the ”34/45 Mbit/s interface” is a 4 wire bus at 38.88 Mbit/s while the backpanel format is
STM–4*.
• Timing: it receives the 622 MHz System clock from the two MATRIX and generates the clock
at 38.88 MHz for the ”34/45 MBit/s interface”.


• RIBUS I/F
release the Management–bus in case of power failure, and to use the remote inventory. It is
powered by the + 3.3 Vdc supply by CONGI boards.
• M–BUS Driver
DC/DC CONVERTER
It converts the 48/60 V power supply to the 3.3 V used to supply all the components in the board.
• STEP DOWN
It uses the 3.3 V power supply from DC/DC Converter block to obtain the 2.5 V used to power
the Gate Array (G.A.).
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 441 / 706

706

AUX DCC DCC

Main and Spare
CK 38.88
AUX

MATRIXE
34/45 Mb/s #3

To/From

Data IN Input side
LPA LPT LTCA LTCT AU4
LOS ASSEMBLY STM4
Access Card

4 X 38.88 Mbit/s
From/To

BPF 622 Mbit/s
I/F

Output side
STM–4 TIMING

Main and Spare
Data OUT G.A.

MATRIXE
DISASS.

From
CK 38.88
TIMING CK syst.
AUX DCC
CK 38.88
34/45 Mb/s #2
Data IN Input side
Access Card

LOS ASSEMBLY Power
From/To

Sync

Output side
Data OUT 3.3 V DC/DC 48/60 V
DISASS. CONV.

CONGI A B
AUX DCC 2.5 V STEP

from
CK 38.88 DOWN
34/45 Mb/s #1

Data IN Input side
+ 3.3 Vdc F
Configuration and Status

LOS LPA LPT LTCA LTCT AU4
ASSEMBLY
Access Card
From/To

Output side
Data OUT
DISASS.

Management bus
M–BUS
Main and Spare

Driver
MATRIXE

Unit CMISS
To/From

Failure
Bus–off
RIBUS
REMOTE RIBUS
INVENTORY Id
3 x 34/45 MBIT/S PORT CARD I/F
+ 3.3 Vdc

Figure 262. 3x34/45 port card –Block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 442 / 706

706

4.23 4 x STM–1 electrical/optical port card (P4S1N)


The 4 x STM–1 port processes up to four STM–1 streams. A max. of two electrical or optical modules can

be housed on the card to give physical access to the STM–1 signal. The remaining two physical accesses
are on the relevant access card .

The SDH functions required to manage STM–1 signal are implemented by the G.A. mounted on the board.
It interfaces the two MATRIX card via backpanel.

Referring to the ITU–T G.783 Recommendation , the G.A. performs the following functions :

– TTF

– HOA

– LPOM /LSUT (the last is not available in this release)

– HPOM /HSUT (the last is not available in this release)

Cross connection functions (MSP, HPC and LPC) are performed by the two MATRIX boards (working in
1+1 configuration).

The TTF block is connected to the MATRIX boards (main and spare) through 1+1 bidirectional links at
622 Mbit/s , STM–4 equivalent capacity.

HOA block is connected both to the HPC matrices and to the LPC matrices on the two MATRIX boards
through a couple of 1+1 links at 622 MBit/s working in protection, STM–4 equivalent capacity.
Backpanel interface supply a system–clock to the G.A. internal circuits.

In the following block description, the new naming convention of the G.783 is reported. Refer to para. 3.3.4
on page 206 for details.

The G.A. send and receive four STM–1 signals (data + clock) at 155 Mbit/s to/from each SPI.
An external LOS is received from each input line interface.
Each optical transmitter provides its status by means of two input signals: Laser Degrade and Laser
Failure.

The ALS algorithm is hardware implemented : the G.A. provides the Laser shut Down command (LASER
OFF).

In the following will be described the signal processing of only one STM–1 interface; the other three
interfaces process the signal in the same way.

The PISO SIPO (Parallel–In Serial–Out; Serial–in Parallel–out) blocks allow the unit to interface with
the back panel at of 622 Mbit/s bit rate, mapping the STM–1 signals over a STM–4 internal equivalent
frame.

TTF BLOCK ( SPI, RST, MST, MSA)

This block performs the Transport Terminal Functions (sink on Input side, source on Output side) for
STM–1 signals.

TTF block provides the T1 timing references at 2 MHz , derived from the STM–1 input signals.
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 443 / 706

706

INPUT side : from line to MSP block on MATRIX

SPI (OSn/RSn_A_Sk) : it descramblers the incoming signal , counts the OOF and reveals the LOF
alarm.

RST (RSn_TT_Sk) : performs frame alignment detection (A1, A2) , regenerator section trace
recovery (J0) and mismatch detection, BIP–8 Errored Block count. J0 is not managed in this release.

MST (MSn_TT_Sk) : performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS
detection. TSD is applied in case of MS–DEG (signal degrade), TSF is applied if MS–AIS is detected.

MSA (MSn/Sn_A_Sk) : performs AU4 pointer interpretation, LOP and AIS detection, pointer
justification.

Moreover the following functions are performed on the Rx side :

SOH BYTE extraction (Rx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) are dropped and
serialized in a DCC frame. Two DCC frames are generated working in 1+1 protection.

OUTPUT side : from MATRIX to line

MSA (Ms/Sn_A_So) : it performs AUG assembly, AU–4 pointer generation, AU–AIS generation.

MST (MSn_TT_So) : it performs BIP–24 calculation and insertion, MS–REI MS–RDI and MS–AIS
insertion.

RST (RSn_TT_So) : it performs frame alignment insertion, regenerator section path trace insertion,
BIP–8 calculation and insertion.

SOH BYTE insertion (Tx side): DCC bytes (DCCR D1–D3 and DCCM D4–D12) coming from the
DCC frames are inserted into the SOH section.

SPI (OSn/RSn_A_So) :it scramblers the outgoing signals and insert AIS in alarm condition.

HOA BLOCK (HPT, HPA)

From HPC matrix to LPC matrix

HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI and
UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS
is detected.
TSD is applied if a condition of signal degrade is detected.

Moreover :

F2 F3 byte extraction (Rx side) : both F2 and F3 bytes are extracted from the received flow and
serialized on a DCC frame .

N1 byte extraction (Rx side) : for the network Tandem Connection Termination Monitoring
function (TCT/TCM).

HPA (Sn/Sm_A_Sk) : VC–4 disassembly, TU pointer interpretation, LOP and TU–AIS detection,
HP–SLM and LOM detection.
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 444 / 706

706

From LPC matrix to HPC matrix

HPA (Sn/Sm_A_So) : VC4 assembly, TU pointer generation, TU–AIS generation , signal label
insertion,

HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8

Moreover:

F2 and F3 byte insertion (Tx side) : F2/F3 bytes are inserted on the DCC frame

N1 byte insertion (Tx side) : for the network Tandem Connection Termination Monitoring function
(TCT/TCM).

The G.A. provides also the HSUT, HPOM, (alternative) and LSUT, LPOM functions (alternative) both in
Rx and Tx side.

The main task of HSUT are:

RX side (from MSA to HPC matrix):

• path trace information recovery
• REI recovery
• HP–RDI detection (path status monitoring
• UNEQ and VC–AIS detection (signal label monitoring)
• VC4 BIP–8 Errored Block count

Tx side: (from HPC matrix to MSA)

• generation of an unequipped container
• ”unequipped” insertion, trail trace identifier generation
• RDI and /or REI information generation
• VC–4 BIP–8 calculation and insertion

The main task of HPOM are:

RX and TX side:

• signal termination
• J1 path recovering
• REI information recovering
• TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated in case of SD

The main tasks of LSUT are :

RX side (from HPA to LPC matrix):

• recovering of VC–m unequipped signal label
• path trace recovering
• BIP–2 recovery
1AA 00014 0004 (9007) A4 – ALICE 04.10

• REI and RDI recovery

ED 03

3AL 91669 AA AA 445 / 706

706

Tx side (from LPC matrix to HPA ):

• insertion of VC–m unequipped signal label
• path trace insertion

• BIP–2 insertion

• REI and RDI insertion

LSUT is used to monitor unequipped path trails .

The main tasks of LPOM are :

• trace identifier monitoring
• RDI and REI recovering and deriving for performance primitives
• signal label monitoring
• VC–m BIP–2 errored block count

LPOM is used for performance monitoring purposes.


• RIBUS I/F
release the Management–bus in case of power failure, and to use the remote inventory. RIBUS
I/F is powered by the + 3.3 Vdc supply by CONGI boards.


• M–BUS Driver

DC/DC CONVERTERS

This block converts the 48/60 V power supply 3.3 V and 2.5 V used to supply all the components
in the board.
1AA 00014 0004 (9007) A4 – ALICE 04.10

ED 03

3AL 91669 AA AA 446 / 706

706

System–clock a

G.A. (1a)
System–clock b

PISO to/from HPC matrix
(1b) (X Link)

(1c) SIPO

MAIN AND SPARE
1st INTERFACE

HPT (1d)

MATRIXE
HOA
(2a)
HPA to/from LPC matrix
PISO (L link)
(2b)
LPOM (2c) SIPO
LSUT (2d)
(*)
F2, F3 T1

Optical or Electrical HPOM (3a) to/from
Optical TTF HPC matrix
Plug–in Module HSUT (3b) PISO
Input/ (*) (H Link)
Output (3c)
STM–1 SIPO
1 RST MST MSA (3d)
SPI LOS
LASER D. DCCR DCCM (4a)
RSOH MSOH PISO DCC
LASER F. (4b)
LASER OFF (4c) SIPO
(4d)

FROM/TO
SERVICE
(5a)
PISO AUX
F2, F3 (5b)
(5c) SIPO
Optical (5d)
Input/
Output (1b)
2 2nd INTERFACE (2b)
(3b)
(4b)
Optical (5b) T1
Input/
Output (1c)
3 (2c)

MAIN AND SPARE
3 rd INTERFACE
SPI (3c)
( )

MATRIXE
(4c)
Optical (5c) T1
Input/
Output (1d)
4 4 th INTERFACE (2d)
SPI (3d)
( ) (4d)
(5d) T1

Config.
Status Management

MAIN AND SPARE
622 MHz Bus
OSC M–BUS

MATRIXE
FROM/TO
Driver
CMISS
Bus–OFF
Remote RIBUS
Inventory

RIBUS ID
Power I/F
Sync
F +3.3 Vdc
CONGI A B

Unit
Failure
3.3 V
FROM

DC/DC 48/60 V
2.5 V CONVERTERS
ACCESS
CARD 4 x STM–1 ELECTRICAL/OPTICAL PORT
Notes:
(*) – HSUT and LSUT are not available in the current release
( )– THE ” SPI” ASSOCIATED TO THE 3rd AND 4th INTERFACES ARE PHISICALLY ON THE ACCESS CARD
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 263. 4 x STM–1 Electrical/Optical port block diagram

ED 03

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4.24 4 X 140/STM1 switchable O/E port card (P4E4N)


The 4 X 140/STM1 switchable O/E port card is a bidirectional unit which interfaces up to four

plesiochronous 140 Mbit/s (E4) or Synchronous 155 Mbit/s (STM–1) with STM4–BPF (BPF=backpanel
format ).
The choice among the two possible different interfaces is flexible and mixed configuration are allowed.
For each P4E4N port card there are four electrical (75 Ohm) or optical module( Short and Long Haul) ;two
of the four module are hosted directly on the port card , the other two are hosted in the relevant access
card (A2S1).

The description that follows explains the two operating mode of each interface (140 Mbit/s PDH or 155
Mbit/s SDH) on the port card.

155 Mbit/s STM–1

It interfaces the two MATRIX cards via backpanel.
The “Mapper/Demapper 140–PDH/155–STM–1” block is internally by–passed through the EN 140/155
signal when the interface is programmed as 155 Mbit/s.

– TTF
– HOA

Cross connection functions (MSP, HPC and LPC) are performed by the matrices present on the two
MATRIX boards (working in 1+1 configuration).




Failure.
OFF).
1AA 00014 0004 (9007) A4 – ALICE 04.10

frame.

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STM–1 signals.



alarm.



justification.





insertion.






is detected.

Moreover :


function (TCT/TCM).
1AA 00014 0004 (9007) A4 – ALICE 04.10


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insertion,


Moreover:


(TCT/TCM).

Rx and Tx side.



• REI recovery




RX and TX side:




1AA 00014 0004 (9007) A4 – ALICE 04.10


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140 Mbit/s PDH

The functions required to manage 140 Mbit/s PDH signal are implemented by the “Mapper/Demapper
140–PDH/155–STM–1” block and G.A. mounted on the board. The last interfaces the two matrix on the
MATRIX cards via backpanel.


The circuits concerned are:

PPI (E4_TT_Sk and E4/P4s_A_Sk) : it interfaces the line extracting the timing, decoding data and
AIS detecting. It is also performed the PDH LOS processing. The Data flow is than sent to the LPA
block after a serial to parallel conversion (SIPO).

LPA (S4/P4s_A_So)
The 140 Mbit/s plesiochronous stream is inserted in a C4 container to be adapted so as to be
transported into the synchronous network.

HPT (S4_TT_So)
The Virtual Container (VC4) is formatted.
The VC4 is structured so that its octets are distributed within a 125 msec. interval (i.e., one STM–1
period), and consists of the C4 container and POH. The latter containing nine octets equally
distributed within the frame. Figure 228. on page 375 depicts the structure of a VC4 and of the POH
bytes: J1, B3. C2, G1, F2, H4, Z3–Z5. Bytes F2, Z3–Z5 .

PG ( Pointer Generator)
A fixed pointer value is inserted in the AUOH to structure the AU4 signal.

MST and RST
This two functions are necessary to create a proprietary STM–1 signal in order to interface the
“Mapper/Demapper 140–PDH/155–STM–1” block with the G.A. Data are sent to the G.A. in a serial
way through the PISO block.
In the G.A. the complementary function are made (RST, MST, MSA).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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MSA (inside the G.A.): It performs AUG assembly, AU–4 pointer generation, AU–AIS generation

MST and RST (inside the G.A.):this two functions are necessary to create a STM–1 signal in order
to interface the G.A with the “Mapper/Demapper 140–PDH/155–STM–1” block .
Data are sent from G.A. to Mapper/Demapper 140–PDH/155–STM–1” block in serial way and than
converted in parallel through a SIPO.

ALIGNER: it searches the frame alignment word and checks the alignment conditions.

HPT ( S4_TT_Sk): Extracts the POH bytes from the VC4 structure and manages them accordingly
(see Figure 228. on page 375).

LPA (S4/P4s_ASk)
Restructures the 140 Mbit/s PDH signal by extracting it from Container C4 . The signal is than sent
in serial way (through PISO) to the PPI block.

PPI (E4/P4s_A_So and E4_TT_So ) : it convert the internal signal code to the line code.


• RIBUS I/F
This block is used to:

– read/write from/to the ”RIBUS” stream
– control the LED on the unit
– to release the Management–bus in case of power failure
– read remote inventory data
– enable 155Mbit/ or 140 Mbit/s operating mode ( EN 140/155) separately
– send Internal Loop and External Loop commands to each interface separately

RIBUS I/F is powered by the + 3.3 Vdc supply by CONGI boards.


• M–BUS Driver

DC/DC CONVERTERS

This block converts the 48/60 V power supply 5V, 3.3 V, 2.5 V and 1.8 V used to supply all the
components in the board.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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System–clock a
G.A. System–clock b
(1a) to/from HPC matrix
(1b)
PISO (X Link)
HOA

MAIN AND SPARE

(1c) SIPO
1st INTERFACE

HPT (1d)

MATRIXE
(2a) to/from LPC matrix
Int. HPA PISO (L link)
(2b)
Loop LPOM (*) (2c) SIPO
Line LSUT (2d)
Loop
EN 140/155 HPOM T1
F2, F3
HSUT(*)
O/E (3a) to/from
Input/ O/E LOS LOS TTF HPC matrix
(3b) PISO (H Link)
Output Module (3c)
1 MAPPER/DEMAPPER Data SIPO
Data 140–PDH/155–STM1
RST MST MSA (3d)
SPI
or
PPI DCCR DCCM (4a)
LASER D. RSOH MSOH (4b)
PISO
DCC
LASER F. (4c) SIPO

FROM/TO
SERVICE
(4d)
LASER OFF
(5a)
(5b)
PISO

AUX
O/E F2, F3 (5c) SIPO
Input/ (5d)
Output
2 (1b)
(2b)
2nd INTERFACE (3b)
O/E EN 140/155 (4b)
Input/ (5b) T1
Output
3 (1c)

MAIN AND SPARE
SPI (2c)
3 rd INTERFACE

MATRIXE
( ) (3c)
O/E (4c)
Input/ EN 140/155 (5c) T1
Output
4 (1d)
SPI 4 th INTERFACE (2d)
( ) (3d)
(4d)
EN 140/155 T1
(5d)

Config.
Status

MAIN AND SPARE
622 MHz Management
Bus
OSC M–BUS

MATRIXE
FROM/TO
Power Driver
Sync.
Remote CMISS
Inventory Bus–OFF

RIBUS
EN 140/155 1–4 RIBUS
I/F ID
Line Loop 1–4
FROM CONGI

1.8 V F +3.3 Vdc
Int. Loop 1–4
5V
DC/DC Unit failure 48/60 V
3.3 V
CONVERTERS
2.5 V
ACCESS
CARD 4 X 140/STM–1 ELECTRICAL/OPTICAL PORT
Notes:
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 264. 4 x 140/STM–1 Electrical / Optical port block diagram

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EN 140/155

MAPPER/DEMAPPER
140–PDH/155–STM1 EN 140/155

DATA
155 Mbit/s to G.A.
PISO
Data In LPA
SIPO Insert HPT Pointer MST RST
into C4 Generation

PDH AIS
Detector C3,B3
TO
G.A.
SDH LOS
LOS
PDH LOS
processing

EN 140/155
OH
MANAGEMENT

DATA
Data Out LPA from G.A.
HPT ALIGNER SIPO
140 Mbit/s POH EXTRACTION
PISO Reconstruction

155 Mbit/s

EN 140/155

Figure 265. Mapper /Demapper 140–PDH / 155–STM1 block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.25 4 x STM–1 port (P4ES1N)


The 4 x STM–1 port processes up to four STM–1 streams. The physical accesses to the four STM–1

signals are available on the relevant access card.

It interfaces the two MATRIX card via backpanel.


– TTF

– HOA



1+1 configuration).


HOA block is connected both to the HPC matrices and to the LPC matrices on the two MATRIX board



frame.


STM–1 signals.

1AA 00014 0004 (9007) A4 – ALICE 04.10

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alarm.



justification.





insertion.






is detected.

Moreover :


function (TCT/TCM).

1AA 00014 0004 (9007) A4 – ALICE 04.10


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insertion,


Moreover:


(TCT/TCM).

Rx and Tx side.



• REI recovery




RX and TX side:




1AA 00014 0004 (9007) A4 – ALICE 04.10


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• RIBUS I/F


• M–BUS Driver

DC/DC CONVERTERS

This block converts the 48/60 V power supply 3.3 V and 2.5 V used to supply all the components
in the board.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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System–clock a

G.A. (1a)
System–clock b

1st INTERFACE PISO to/from HPC matrix
(1b) (X Link)

(1c) SIPO

MAIN AND SPARE

HPT

(1d)

MATRIXE
HOA
HPA PISO (L Link)
(2b)
LPOM (2c) SIPO
LSUT (2d)
(*) T1
F2, F3
to/from
Optical TTF HPOM (3a) HPC matrix
HSUT (3b) PISO (H Link)
Input/ (*)
Output (3c)
STM–1 SIPO
1 RST MST MSA (3d)
SPI LOS
(4a)
DCCR DCCM PISO DCC
RSOH MSOH (4b)
(4c) SIPO

FROM/TO
SERVICE
(4d)
(5a)
PISO
(5b) AUX
F2, F3 (5c) SIPO
Optical (5d)
Input/
Output
2 2nd INTERFACE (1b)
SPI (2b)
(3b)
(4b)
Optical (5b) T1
Input/
Output (1c)
3 (2c)
3 rd INTERFACE

MAIN AND SPARE
SPI (3c)

MATRIXE
(4c)
Optical (5c) T1
Input/
Output (1d)
4 4 th INTERFACE (2d)
(3d)
SPI (4d)
(5d) T1

Config.
Status Management
622 MHz Bus
OSC M–BUS

MAIN AND SPARE
Driver

MATRIXE
CMISS
FROM/TO
Bus–OFF
Remote
Inventory ID
RIBUS RIBUS
Power I/F
Sync + 3.3 Vdc
F
CONGI A B

Unit
Failure
FROM

3.3 V 48/60 V
DC/DC
2.5 V CONVERTERS

ACCESS
CARD 4 x STM–1 ELECTRICAL PORT
Notes:
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 266. 4 x STM–1 Electrical port block diagram

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4.26 Port 16xSTM1 – 4xSTM4 (P16S1–4E)


General

The board P16S1–4E provides either 4 STM–4 optical interfaces or 16 STM–1 Optical/Electrical interfaces
(along with the Optical/Electrical Access Board) (refer to Figure 91. on page 189).

The P16S1–4E board along with A12OS1E Optical Access board allows the transport of 16 optical STM1
streams by means of 16 SFP optical transceivers.

On the P16S1–4E there are four of 16 SFP transceivers, while in the A12OS1E card there are the other
12 transceivers.

On the P16S1–4E board the SFP transceivers can work at both the bit rate of 155 and 622 Mb/s for both
Short Haul and Long Haul applications.

The P16S1–4E board along with the A16ES1E Electrical Access card allows the transport of 16 electrical
STM–1 streams. All the 16 electrical line interface devices are present in the A16ES1E board.

Description

The main features of P16S1–4E board are:

[1] Provides four SFP transceivers for optical interface as per ITU–T G.957.

The Small Form–factor Pluggable (SFP) fiber optic Transceiver is used to interface the P16S1–4E
board to single mode fiber optic cables.
The SFP is hot pluggable and compliant with Multi–Source Agreement (MSA). The cage and the
connector will be mounted on the board, and the optical module will be plugged into it. There are four
SFP modules present on the P16S1–4E board, which provide optical interface to either four STM–1
or four STM–4 tributaries.
The SFPs take in optical data and give electrical signals to the “DATA CLOCK RECOVERY” block.
The SFP module is interfaced with the “MAPPER/DEMAPPER STM–1/STM–4”; The interface
consists of control and alarm signals namely LASER FAULT, LASER OFF, LOS.

[2] Provides four devices for Clock and Data recovery. Data and clock are then sent to
“MAPPER/DEMAPPER STM–1/STM–4” block.

[3] Provides a “MAPPER/DEMAPPER STM–1/STM–4” which interfaces the on–board clock and data
streams and those obtained from the Access cards at 1.6 Gb/s via “SERDES” block to the overhead
termination ”TTF+HOA” and vice versa.

[4] Provides four ”TTF+HOA” blocks, which perform trail termination sourcing/sinking functions, and
adaptation functions for sixteen STM–1/ four STM–4 streams. ”TTF+HOA” blocks also inserts and
extracts the DCC and AUX channels from the payload. These are given to/from the backplane
through the “DCC MANAGEMENT” block.
For details information about TTF and HOA block refer to the PAES1N board description on
paragraph 4.25 page 455.

[5] Provides three blocks so as to:

• Process data from/to the on board ”TTF+HOA” blocks to/from NGI interface at the back plane
1AA 00014 0004 (9007) A4 – ALICE 04.10

towards Matrix A and B at 2.5Gbps rate (DATA BACK PLANE INTERFACE ).

• Process data from /to the Access Cards at 1.6Gbps rate (SERDES).

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[6] Provides RIBUS device for power up status/configuration. Also, generation and monitoring of various
status and control signals are done through the ports of RIBUS.

[7] Provides device to control and configure the two “DATA BACK PLANE INTERFACE” blocks through

the SPI bus and process DCC and AUX channels at the backplane.

[8] Provide EEPROM for storing the configuration data.

[9] Generates all the required voltages of 3.3V, 2.5V, 1.8V, 1.5V and 1.2V and provides circuitry for
monitoring these voltages.

[10] Provides timing circuitry, which includes 622 MHz VCXO and associated circuits for external clock
generation and PLL function.

[11] Provides one bicolour LED and a laser restart switch (the last drives both the optical interfaces on
board and on access card)


• RIBUS I/F

1AA 00014 0004 (9007) A4 – ALICE 04.10

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8x414 Mb/s Data and alarms
SERDES 2x1.66 Gb/s

ACCESS CARDS
from/to
Laser Restart

(*)
CK19 MHz

TIMING System–clock a
622.08 MHz
System–clock b
Optical STM–1 CLK 38.88 MHz CIRCUITRY

MAIN AND SPARE
Input/ #1

MATRIXE
Output laser fault (LF) MFSYNC
1 1
2 laser off (LOFF)
SFP 3 LOS DATA
MODULE TTF
DATA CK BACK–PLANE
RECOVERY HOA INTERFACE
Optical
x4
Input/ LF
Output LOFF
MAPPER/DEMAPPER

2 LOS (*)
TTF
STM–1/STM–4

DATA CK

FROM/TO
SFP

SERVICE
MODULE RECOVERY DCC/AUX
HOA MANAGEMENT
x4

(*)
Optical LF
Input/ TTF
LOFF
Output

MAIN AND SPARE
LOS
3 HOA DATA

MATRIXE
SFP DATA CK
MODULE RECOVERY x4 BACK–PLANE
INTERFACE
Optical TTF
LF
Input/ LOFF
Output LOS HOA (*)
4 STM–1
SFP DATA CK x4
MODULE RECOVERY #16

(*)

1.8V
DC/DC
1.5V
Configuration CONVERTER
1.2V

CONGI A B

Status FROM
3.3 V DC/DC
CONVERTER 48/60 V
2.5 V
PROTECTION
M–BUS
Driver
MAIN AND SPARE

Management
MATRIXE

Bus
Bus–OFF CMISS
Remote
Inventory ID
RIBUS RIBUS
I/F

Unit
CONGI A B

F + 3.3 Vdc
Failure
FROM

16xSTM–1 – 4XSTM–4 PORT
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 267. 16x STM–1 – 4x STM–4 port block diagram

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4.27 4 x OC3 AU3/TU3 CONVERSION port (P4OC3)


This board can manage up to 4 x OC–3 (SONET) streams.

The board hosts up to 2 interfaces into the front panel, which can be equipped with Electrical (ICMI) or
Optical plug–in modules (IS–1.1, IL–1.1, IL–1.2, MM1). The other two interfaces can be hosted in the
Access area using the A2S1 access card.
Each combination of electrical/optical modules can be equipped in the same board.

On OC–3 interface the Sonet mapping is manage so the RS and MS sections are terminated, the 3 AU3
are processed to extract or insert the 3 VC3.

This unit performs the AU3/TU3 conversion , which allows the transport in SDH network of Sonet VC3
traffic.

The conversion is performed on OC–3 interface: the 3 VC3 are extracted then re–mapping in SDH VC4
container and this container is passed to the matrix where it is managed as a structured VC4.

Figure 223. on page 371 depicts the AU3/TU3 conversion mechanism achieved by 4xOC3 board.

The Sonet interface (OC3) have not to be configured as Synchronization source. The OH byte of RS and
MS section are managed according SDH ITU standard. The configuration is done by Craft Terminal or
Network Management.

No EPS is supported by this board.
The description of the board has been divided in two parts; the first is the “AU3/TU3 conversion block”
thath implement the SONET functionality, the second is the “G.A.” that implement the SDH functionality.

AU3/TU3 conversion block

The functions required to manage OC3 signal are implemented by the “AU3/TU3 conversion block that
interface the G.A. mounted on the board. The last interfaces the two matrix on the MATRIX cards via
backpanel.

INPUT side : from plug–in module to G.A.


SIPO :this block performs the Serial to Parallel conversion (SIPO) of the SONET STS3/OC3 (155
Mb/s) serial stream coming from the line.

ALIGNER (SDH/SONET standard Frame Aligner)
The Frame Aligner Word (FAW) estracted by the incoming frame is inserted by the MST/RST* source
function into the outgoing frame: in this way G.A. is able to detect a possible OOF (Out Of Frame)
condition as well.

RST/MST Sk
This block performs:

• Standard SDH/SONET Descrambler
1AA 00014 0004 (9007) A4 – ALICE 04.10

• extraction of all SOH bytes of the SONET stream that are inserted in RST/MST* source
functions to be processed by G.A.
• B1 and B2 calculation and checking in order to send error information downstream

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AU3–TU3 Rx

The AU3 to TU3 conversion block contains:

•

time–division Pointer Interpreter of the 3 AU3s

• Pointer buffer
• Pointer Generator of the 3 TU3 multiplexed inside the AU4
• Pointer Generator of the AU4

HPT* So

• calculation and insertion of B3 byte in AU4 POH
• insertion of C2 byte in AU4 POH

MST/RST* So

• insertion of extracted and stored SOH bytes
• compensation of B1 and B2 bytes by usage of error information collected by RST/MST sink
function

PISO: this block performs the Parallel to Serial conversion (PISO) of the SDH STM–1 stream
towards G.A.

On the Input side the LOS alarm is buffered and sent to the G.A.

OUTPUT side : from G.A. to Plug–in module

SIPO :this block performs the Serial to Parallel conversion (SIPO) of the SDH STM–1 stream coming
from G.A.

ALIGNER*
Alignement to SDH STM–1 stream coming from G.A. is performed

RST/MST* Sk
• extraction of all SOH bytes of the SDH stream that are inserted in RST/MST source functions
• B1 calculation and checking for internal use.

HPT* Sk
It implements the “Path Label Mismatch“ algorithm;
the C2 byte from the incoming AU4 frame is extracted and its content is written into a register. If the
value is different than expected, a “Path Label Mismatch” alarm is raised

AU3–TU3 Tx:

• Pointer Interpreter of the AU4
• time–division Pointer Interpreter of the 3 TU3s
• Pointer buffer
• Pointer Generator of the 3 AU3 multiplexed inside the OC3
• pointer justifications and buffer overflow alarms are reported Equipment Controller (EC)
1AA 00014 0004 (9007) A4 – ALICE 04.10

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MST/RST So

• insertion of extracted and stored SOH bytes

• calculation and insertion of B1 and B2 bytes

• standard SONET scrambler

PISO: this block performs the Parallel to Serial conversion (PISO) of the SONET STS3/OC3 stream
towards the line.

G.A. (Gate Array)

The SDH functions are implemented by the G.A. mounted on the board. It interfaces the two MATRIX
cards via backpanel.

– TTF
– HOA

MATRIX boards (working in 1+1 configuration).




The G.A. send and receive four signals (data + clock) to/from the four “AU3/TU3 CONVERSION block”
Failure.
OFF).
In the following will be described the signal processing of only one signal from/to “AU3/TU3 CONVERSION
block”; the other three interfaces process the signal in the same way.
the back panel at of 622 Mbit/s bit rate, mapping the signals over a STM–4 internal equivalent frame.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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TTF BLOCK ( SPI*, RST, MST, MSA)

This block performs the Transport Terminal Functions (sink on Input side, source on Output side) for the
155 Mbit/s signals.


SPI* (OSn/RSn_A_Sk) : it descramblers the incoming signal , counts the OOF and reveals the LOF
alarm.



justification.





insertion.



SPI* (OSn/RSn_A_So) :it scramblers the outgoing signals and insert AIS in alarm condition.



is detected.

Moreover :


function (TCT/TCM).

1AA 00014 0004 (9007) A4 – ALICE 04.10


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insertion,


Moreover:


(TCT/TCM).

Rx and Tx side.



• REI recovery




RX and TX side:




1AA 00014 0004 (9007) A4 – ALICE 04.10


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• RIBUS I/F

– to release the Management–bus in case of power failure
– read remote inventory data
– send Internal Loop and External Loop commands to each interface separately



• M–BUS Driver

DC/DC CONVERTERS

This block converts the 48/60 V power supply 5V, 3.3 V, 2.5 V and 1.8 V used to supply all the
1AA 00014 0004 (9007) A4 – ALICE 04.10

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System–clock a
G.A. System–clock b
(1a) to/from HPC matrix
(1b)
PISO (X Link)
HOA

MAIN AND SPARE

(1c) SIPO
1st INTERFACE

HPT (1d)

MATRIX
Int. HPA PISO (L link)
(2b)
Loop LPOM (*) (2c) SIPO
Line LSUT (2d)
Loop
F2, F3 HPOM
HSUT(*)
O/E (3a) to/from
Input/ O/E LOS LOS TTF HPC matrix
(3b) PISO (H Link)
Output Module AUE/TU3 (3c)
1 Data SIPO
Data CONVERSION SPI* RST MST MSA (3d)
SPI block
DCCR DCCM (4a)
LASER D. RSOH MSOH (4b)
PISO
DCC
LASER F. (4c) SIPO

FROM/TO
SERVICE
(4d)
LASER OFF
(5a)
(5b)
PISO

AUX
O/E F2, F3 (5c) SIPO
Input/ (5d)
Output
2 (1b)
(2b)
2nd INTERFACE (3b)
O/E (4b)
Input/ (5b)
Output
3 (1c)
SPI (2c)
( ) 3 rd INTERFACE (3c)
O/E (4c)
Input/ (5c)
Output
4 (1d)
SPI 4 th INTERFACE (2d)
( ) (3d)
(4d)
(5d)

Config.
Status

MAIN AND SPARE
622 MHz Management
Bus
OSC M–BUS

FROM/TO
MATRIX
Power Driver
Sync.
Remote CMISS
Inventory Bus–OFF

RIBUS
RIBUS
I/F ID
Line Loop 1–4
FROM CONGI

1.8 V F +3.3 Vdc
Int. Loop 1–4
5V
DC/DC Unit failure 48/60 V
3.3 V
CONVERTERS
2.5 V
ACCESS
CARD 4xOC3 AU3/TU3 CONVERSION PORT
Notes:
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 268. 4 x OC3 AU3/TU3 conversion port(P40C3)

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AU3/TU3 CONVERSION block

RSOH bytes

MSOH bytes SOH
BYPASS

B1 error for compensation

Data B2 error for compensation
from OOF
plug–in
AU3–TU3 Rx DATA
module
SIPO Aligner PI PB PG PG to G.A.
RST MST HPT* MST* RST* PISO
sk sk AU3 TU3 AU4* So So So

B3, C2

LOS LOS
LOS
BUFFERING

RSOH bytes
SOH MSOH bytes
BYPASS

Data
to DATA
plug–in TU3–AU3 Tx from
module G.A.
RST MST PG PI PI MST* RST* Aligner SIPO
PISO PB TU3 AU4
So So AU3 sk sk *

C2 check
HPT*
Sk
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 269. AU3/TU3 conversion block

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4.28 STM–4 optical ports

(See Figure 270. on page475)

The STM–4 port processes an optical STM–4 stream.

Different STM–4 optical port are available according to the connector type (FC/PC or SC/PC) and wave
length (S–4.1, L–4.1, L–4.1JE, L–4.2 and L–4.2JE); in the following a generic description is given.

It interfaces the two MATRIX boards via backpanel.

Referring to the ITU–T G.783 recommendation, the G.A. performs the following functions :

– TTF

– HOA



1+1 configuration).

The TTF block is connected to the two MATRIX boards through 1+1 bidirectional links at 622 Mbit/s ,
STM–4 equivalent capacity.



The G.A. send and receive one STM–4 signal (data + clock) at 622 Mbit/s to/from the SPI
The SPI can detect an external LOS from the input line .
The optical transmitter provides to the G.A. its status by means of two input signals: Laser Degrade and
Laser Failure.

The ALS algorithm is hardware implemented and the G.A. provides the Laser shut Down command.

On the front panel of the unit a push–button is available for manual laser restart.

TTF BLOCK (SPI, RST, MST, MSA)

STM–4 signal.

TTF block provides the T1 timing references at 2 MHz , derived from the STM–4 input signals

INPUT side : from line to MSP MATRIX

alarm.
1AA 00014 0004 (9007) A4 – ALICE 04.10

recovery (J0) and mismatch detection, BIP–8 Errored Block count.

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MSA (MSn/Sn_A_Sk) : performs AU4’s pointer interpretation, LOP and AIS detection, pointer

justification.



TP byte insertion (Rx side) : since the cross connection functions are centralized , for protection
purpose TSD (Trail Signal Degrade) and TSF (Trail Signal Failure) are transmitted towards the two
MATRIX board.

K BYTES insertion and extraction (Rx side) : this block provides the in–band transmission of
K1,K2, bytes towards the MATRIX board. For each of the 4 STM–1 streams, the bytes are extracted
form the line when a TSF is received and transmitted towards the two MATRIX board.


The four AUG structure are byte interleaved in the STM–4 structure with fixed phase relationship vs.
the same multiple signal.

insertion.



K BYTES insertion and extraction (Tx side) : K1, K2 bytes are extracted from the frame coming
from backpanel and re–inserted on the same output line frame .



is detected.

Moreover :


function (TCT/TCM).
1AA 00014 0004 (9007) A4 – ALICE 04.10


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insertion,


Moreover:


(TCT/TCM).

Rx and Tx side.



• REI recovery




RX and TX side:




1AA 00014 0004 (9007) A4 – ALICE 04.10


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• RIBUS I/F


• M–BUS Driver

DC/DC CONVERTERS
This block converts the 48/60 V power supply to the following voltages:

• 3.3 V and 2.5 V used to supply all the components in the board.

• –5.2 V to supply the optical module
1AA 00014 0004 (9007) A4 – ALICE 04.10

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System–clock a
System–clock b

G.A.

to/from HPC matrix
(X Link)
HPT
HOA to/from LPC matrix

MAIN AND SPARE
HPA (L Link)

MATRIXE
FROM/TO
F2, F3 LPOM
LSUT
(*)
HPOM
HSUT
OPTICAL (*)
OPTICAL TTF to/from
INTERFACE
INPUT/ HPC matrix
OUPUT STM–4 K1,K2 (H Link)
Tx side RST MST K1,K2,TP
MSA
SPI LOS Insertion Rx side
LASER D. Insertion
LASER F. DCCR DCCM
RSOH MSOH T1
LASER OFF

DCC

FROM/TO
SERVICE
AUX
F2, F3
Config. Status
Management
M–BUS Bus
622 MHz
Laser Restart Driver
OSC

MAIN AND SPARE
CMISS

MATRIXE
FROM/TO
Bus–OFF

Remote
Inventory RIBUS
RIBUS
I/F

Unit ID
Power Failure
CONGI A B
Sync +3.3 Vdc FROM

–5.2 V
3.3 V DC/DC 48/60 V
2.5 V CONVERTERS

STM–4 OPTICAL PORT

Notes:

Figure 270. STM–4 –block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.29 4 x STM–4 optical port (P4S4N)

Note: this board does not support Low Order traffic termination

The 4 x STM–4 port can processes up to four STM–4 streams but only two can be terminated so only two

can be used.

A maximum of two optical modules can be housed on the card to give physical access to the STM–4 signal.

The SDH functions required to manage STM–4 signal are implemented by the GAs mounted on the board.
It interfaces the two MATRIXE cards via backpanel.

For simplicity the following description is related only to one of the four STM–4 interfaces that can be
process by the card .

Referring to the ITU–T G.783 Rec., the GA performs the following functions: TTF and HPOM / HSUT .

Cross connection functions (MSP, HPC) are performed by the two MATRIXE boards (working in 1+1
configuration).

The TTF block is connected to the two MATRIXE boards through 1+1 bidirectional links at 622 Mbit/s,
STM–4 equivalent capacity.

In the following block description, the new naming convention of the G.783 is reported.

The G.A. send and receive STM–4 signals (data + clock) at 622 Mbit/s to/from the SPI.
The SPI can detect an external LOS from the input line.
Laser Failure.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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This block performs the Transport Terminal Functions (sink on Rx side, source on Tx side) for the STM–4
signal.

TTF block provides the T1 timing references at 2 MHz, derived from the STM–4 input signals.


SPI (OSn/RSn_A_Sk) : it descramblers the incoming signal, counts the OOF and reveals the LOF
alarm.

RST (RSn_TT_Sk) : performs frame alignment detection (A1, A2), regenerator section trace


justification.

Moreover the following functions are performed on the Rx side:

SOH BYTE extraction (Rx side) : DCC bytes (DCCR D1 B D3 and DCCM D4 B D12) are dropped
and serialized in a DCC frame. Two DCC frames are generated working in 1+1 protection.

TP byte insertion (Rx side) : since the cross connection functions are centralized, for protection
HCMATRIX boards.

K BYTES insertion and extraction (Rx side) : this block provides the in–band transmission of K1,
K2, bytes towards the MATRIXE board. For each of the 4 STM–1 streams, the bytes are extracted
form the line when a TSF is received and they are overwritten into the SOH section.


The four AUG structure are byte interleaved in the STM–4 structure with fixed phase relationship vs.
the same multiple signal.

insertion.


SOH BYTE insertion (Tx side) : DCC bytes (DCCR D1 B D3 and DCCM D4 B D12) coming
from the DCC frames are inserted into the SOH section.

from backpanel and re–inserted on the same output line frame.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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HPOM, HSUT block

The GA provides also the HSUT, HPOM (alternative) both in RX and TX side.



• REI recovery

TX side (from HPC matrix to MSA):



RX and TX side:

• TSF is generated in case of SSF, UNEQ, TIM, AIS. TSD is generated in case of SD.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Other functions

Other functions implemented are:

•

RIBUS I/F

release the Management–bus in case of power failure, and to use the remote inventory.


• M–BUS Driver
It drives the input–output gates of the Management–bus. These drivers can be disabled (by the
Bus–OFF signal) in case of power failure.

• DC/DC CONVERTERS
This block converts the –48/–60 V power supply to the following voltages:

• 3.3V and 2.5V used to supply all the components in the board

• –5.2Vto supply the optical module

Power–Sync, generated by GA) in order to avoid EMI problems.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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System–clock a
System–clock b

MAIN AND SPARE
G.A. HPOM

MATRIX
HSUT

from/to
OPTICAL OPTICAL TTF #1
INPUT/ INTERFACE
to/from
OUPUT
.
STM–4 K1,K2 HPC matrix
#1 Tx side RST MST MSA K1,K2,TP
SPI LOS Insertion Rx side
LASER D. Insertion
LASER F. DCCR DCCM
OPTICAL RSOH MSOH
INPUT/
OUPUT
#2

TTF #2

TTF #3 (not used)
TTF #4 (not used)
DCC

SERVICE
from/to
Config. Status
Management
M–BUS Bus
622 MHz
Laser Restart Driver
OSC

MAIN AND SPARE
MATRIX
from/to
Bus–OFF

Remote
Inventory RIBUS
RIBUS
I/F

Unit ID
Power Failure
Sync
CONGI A B

–5.2 V
3.3 V 48/60 V
from

DC/DC
2.5 V CONVERTERS

4xSTM–4 OPTICAL PORT

Figure 271. 4xSTM–4 optical port block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.30 ISA – ATM MATRIX 4X4 (ATM4X4)


This unit realize an ATM switching matrix with a total bandwidth of 622Mbit/s.

The board is able to manage up to 16 LT where LT is a physical or logical channel where is mapped an
ATM flow (E1, E3, VC12, VC3, VC4).
On the board a local STM–1 access carrying an unstructured VC4 is managed.

The card perform the following functions:

[1] SDH signal processing

[2] ATM signal processing

[3] MATRIX

[4] MICROPROCESSOR

[5] Common part


One STM–1 interface is available on the card. The stream can be optical or electrical according to the
modules available (electrical–STM1 or optical–STM1) inserted into the front cover cavity of the ATM
MATRIX 4X4.
The proprietary function of ”Bidirectional working on single fiber” is provided, by presetting. This function
uses the BMD (bad media dependent) byte. The BMD alarm is considered as an external LOS.
The ALS algorithm is provided by hardware implementation (Laser–Shut–Down command).
The line–interface (SPI) is performed by the pluggable module (line–module).
LOS, Laser–Degrade, Laser–fail alarms and Laser–Shut–Down commands are comprised in the
AlarmsCommands group in the figure.
The SDH functions required to manage STM–1 signals are:

– SPI, RST, MST, MSA
– HPT, LPT and LPA.
– SOH bytes

MATRIXE board (working in 1+1 configuration).

The MSA block is connected to the MATRIXE boards (main and spare) through 1+1 bidirectional links
at 622 Mbit/s , STM–4 equivalent capacity.

SPI, RST, MST, MSA BLOCK

These blocks performs the Transport Terminal Functions (sink on Rx side, source on Tx side) for STM–1
signals.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Rx side : from line to MSP matrix on the MATRIXE board

alarm.



justification.



Tx side : from matrix on the MATRIXE to line


insertion.




HPT, LPT and LPA blocks

Two data stream at frequency of 622 MHz are connected to the block called SWITCH in Figure 272.
on page 487, one coming from HPC matrix ( L link) and one from LPC matrix (X link).

Rx side: from matrix on MATRIXE to LPA or HPT

The task of the SWITCH block is to select one of the two busses coming from the matrices according to
the type of signal to be connected ( L if is structured or X if unstructured).

If the signal is structured the incoming signal (L Link) is sent through the SWITCH to the LPT and LPA
block.

1AA 00014 0004 (9007) A4 – ALICE 04.10


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detection

If the signal is unstructured the incoming signal (L Link) is sent through the SWITCH to the HPT block.

HPT (Sn_TT_Sk) : path trace information is recovered, REI information is recovered, HP–RDI
and UNEQ are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM
or AIS is detected.
N1 byte extraction (Rx side): for the network Tandem Connection Termination Monitoring
function (TCT/TCM).

Tx side: from LPA or HPT to matrix on MATRIXE

The task of the SWITCH block is to sent the signal coming from HPT or LPT block towards the matrices
on the MATRIXE. The selection is made according to the type of signal to be connected ( L if is structured
or X if unstructured).

If the signal is structured the datas coming from ATM MAPPING block are sent through the LPT and LPA
blocks towards the SWITCH block.



If the signal is unstructured the datas coming from ATM MAPPING block are sent through the HPT block
to the SWITCH block.

HPT (Sn_TT_So) : path trace identification insertion, RDI and REI indications insertion, VC–4
BIP–8 calculation and insertion, signal label insertion.
N1 byte insertion (Tx side): for the network Tandem Connection Termination Monitoring
function (TCT/TCM).

HPOM, HSUT BLOCK (HSUT is not operative in this release)

HPOM performs the monitoring of an equipped path while HSUT performs the termination of an
unequipped path.
From HPOM and HSUT are recovered :
1AA 00014 0004 (9007) A4 – ALICE 04.10

• the primitives used for Performance Monitoring (Errored block count, Defect seconds)
• switching criteria for SNCP/N protection
The two functions are alternative.

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HPOM (Higher order path overhead monitoring)

Snm_TT_Sk : signal termination , J1 path recovering , REI information recovering, HP–RDI
detection (path status monitoring) , UNEQ and VC–AIS detection (signal label monitoring), VC4

BIP–8 Errored Block count. TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated

in case of SD.

HSUT (Higher order Supervisory Unequipped termination)

Sns_TT_Sk : path trace information recovery, REI recovery, HP–RDI detection (path status
monitoring), UNEQ and VC–AIS detection (signal label monitoring), VC4 BIP–8 Errored Block count.

Sns_TT_So : generation of an unequipped container , ”unequipped” insertion, trail trace identifier
generation, RDI and /or REI information generation, VC–4 BIP–8 calculation and insertion.


RX side from SDH to MATRIX:

– ATM DEMAPPING: this block extract the ATM cells from the transmission path payload E1, E3, VC3,
VC4, VC4c; ATM DEMAPPING BLOCK receive the E1 and E3 frames contained in VC3 and VC4
payload for the processing performed in the equipment boards.

– CELL DELINEATION : cell delineation is the process which allow the identification of the cell
boundaries. It is performed on the cell stream extracted from the PDH/SDH frames

– DESCRAMBLER:for SDH and PDH the information field of each cell is descrambled with a self
synchronizing scrambler polynomial; descrambler is enable for a number of bit s equal to the length
of the information field, and again disabled for the following assumed header.

– HEC VERIFICATION AND CORRECTION: in this block HEC field in the cell header is checked; HEC
is used to achieved cell delineation.
The algorithm used can recover a single–bit error or detect headers with single and multi–bit errors.

– CELLs DECOUPLING: idle cells are extracted from the cell stream. Idle cells has been inserted in
the far end adaptation source function to reach the synchronous container capacity.

– HEADER VERIFICATION: this function verifies that the first four octets of the ATM cell header are
recognizable as being a valid header pattern. Cells with unrecognized header patterns are discarded.
An indication of invalid header cell discard event is provided to the microprocessor interface where
are counted.

– UPC/NPC:this function (policing) checks that the incoming traffic from a VPC is not violating the
agreed traffic contract.
UPC (User Parameter Control) and NPC (Network Parameter Control) perform the same function
but in different parts of the network (respectively at User Network Interface and Network Node
Interface )

– OAM: operations and maintenance function is done by using dedicated cells. Typically function are
cells monitoring, cells reporting, faults localization etc.

– HEADER TRANSLATION: this block performs on each virtual connection an header translation
1AA 00014 0004 (9007) A4 – ALICE 04.10

which consist in a conversion of the external identification number (LTI/VPI/VCI) into an an internal
identification number for the user to network direction

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– CONGESTION MANAGEMENT is the block that in the event of congestion is responsible to assure
that cell with loss priority will be discarded before than cell with high priority.

– TRAFFIC SHAPING:this function enhances the utilization of the buffer and matrix providing better

switch performance, especially for burst data.

TX side from MATRIX to SDH:

– RATE REDUCTION: The purpose of this block is to smooth the average 622 Mbits/s traffic entering
with bursts up to 1,2 Gb/s. This function uses four waiting queues, called Rate Reduction FIFOs, used
to manage four priority levels fixed on a per connection basis. They are written at 1,2 Gbits/s and read
at 622 Mbits/s.

– MULTICAST: it is a replication function of the incoming cell towards n outgoing directions; a new
connection identifier is used for each replication.

– ROUTING:The purpose of this function is to guide the cells towards their target LT

– CONGESTION MANAGEMENT: is the block that in the event of congestion is responsible to assure

– TRAFFIC SHAPING: the traffic shaping function modifies the characteristics of cells stream in a VCP
in order to improve network efficiency. It allows for meeting traffic contract at the egress of the
equipment. The shaping function can correct the Cell Delay Variation generated by the buffer and
the matrix.

– HEADER TRANSLATION:this block performs on each virtual connection an header translation which
consist in a conversion of the internal identification number into the external identification number
(LTI/VPI/VCI)for the network to user direction.

– OAM:operations and maintenance function is done by using dedicated cells.

– CELLs RATE DECOUPLING: idle cells are inserted into cell stream to match the rate of the container.

– HEC PROCESSING: the Header Error Control value is calculated on the entire ATM cell header and
inserted in the appropriate field.

– SCRAMBLER: information field of each cell is scrambled in order to improve security and robustness
of the HEC cell delineation mechanism. In addition it helps randomizing the data in the information
field for possible improvement of the transmission performance.

– ATM MAPPING: the cell stream is inserted into transmission path payload E1, E3, VC3, VC4, VC4c;
the E1 and E3 frames are sent to the output of the board mapped in VC12 and VC3 payload because
of the processing that will be done in the equipment boards.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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[3] MATRIX

The matrix is in charged of cross connect the incoming and outgoing cells according to the information
received by the microprocessor. In case of Soft Permanent Virtual Connection ( Soft–PVC) the P–NNI

signalling is supported.

[4] MICROPROCESSOR

The microprocessor present on the board performs the following functionality:

– configuration, alarm and status gathering of the ATM devices present on the board

– handling of the signalling packet receive from the matrix in case of Soft–PVC

– communication with the EC on the EQUICO (SNMP Link); using this channel performance and
management date are encapsulated and sent to the EC and from there to the Craft Terminal or O.S.

All the LEDS (except that for Unit–Failure) are driven by the microprocessor.

The maeaning of the LEDs and Push–Button is reported in Figure 272. on page 487.

[5] Common part

• RIBUS I/F


• M–BUS Driver

DC/DC CONVERTERS
Starting from the 48/60 V power supply the following voltages are generated:

– + 5 Vdc used by the optical module
– +1.5 Vdc, –3.3 Vdc, –3.3 Vdc, –3.3 Vdc, +2.5 Vdc used to supply all the components
in the board.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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AUX from/to

L
ÉÉÉÉ
ÉÉÉÉ LASER D.
LASER F.
RSOH, MSOH, F2, F3 SOH
bytes
System clock a
SERVICE
I E/O LASER OFF
System clock b
N
ÉÉÉÉ HPOM

E HSUT(*)

I/O ÉÉÉÉ
ÉÉÉÉ
MODULE STM–1 (D+CK)

LOS
RST MST MSA
H

MATRIX MAIN AND SPARE
HPT
ÉÉÉÉ 622 MHz
OSC
DCCR DCCM
RSOH MSOH
LPT

from/to
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ Struct/unstruct LPA L

CELLs RATE ATM Struct/unstruct
HEC SCRAMBLER S
DECOUPLING PROCESSING MAPPING W
I
HEC T
HEADER CELLs CELL ATM C X
VERIFICATION DESCRAMBLER
VERIFICATION DECOUPLING DELINEATION DEMAPPING H
CORRECTION

UPC/NPC HEADER CONGESTION TRAFFIC
OAM
TRANSLATION MANAGEMENT SHAPING SPATIAL
MATRIX

HEADER TRAFFIC CONGESTION
OAM ROUTING
TRANSLATION SHAPING MANAGEMENT

MULTICAST RATE
REDUCTION
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ ÉÉ É
É
É
ÉÉ SDRAM

FLASH
LEDS(X5) EPROM

LED TEST PNNI Signalling
MICROPROCESSOR

EQUICO
SNMP
from/to
RESET

Configuration Status (ATM)
ÉÉ É
ÉÉ
É
ÉÉ
É Management
Bus

M–BUS
Configuration Status (SDH)
Driver
from/to

CMISS
Bus–OFF
Remote RIBUS
Inventory
5V
RIBUS ID
1.5 V
I/F
FROM CONGI

F +3.3 Vdc
Unit
– 3.3V DC/DC Failure
ATM MATRIX 4X4 CONVERTERS
3.3 V 48/60 V
2.5 V
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 272. ATM 4X4 card – Block diagram

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4.31 ISA – ATM MATRIX 4X4 ENHANCED (ATM4X4D3)

The functional description of the board is similar to ISA ATM4X4V2 (refer to paragraph 4.32); the only
differences between the two boards is the number of TPs managed.

As a matter of fact ATM4X4D3 board can manage up to 16 TPs among E1, E3, VC12, VC3, VC4, T3,
E1 IMA group.

4.32 ISA – ATM MATRIX 4X4 ENHANCED (ATM4X4V2)

(See Figure 273. on page and 493 )

This unit realize an ATM switching matrix with a total bandwidth of 622Mbit/s.
ATM flow (E1, E3, VC12, VC3, VC4, T3, E1 IMA group)
On the board a local STM–1 access carrying an unstructured VC4 is managed.

The card perform the following functions:



[3] MATRIX

[4] MICROPROCESSOR

[5] Common part

The SDH functions required are:

HPT, LPT and LPA.
– SOH bytes

MATRIXN board (working in 1+1 configuration).

The MSA block is connected to the MATRIXN boards (main and spare) through 1+1 bidirectional links
at 622 Mbit/s , STM–4 equivalent capacity.


Two data stream at frequency of 622 MHz are connected to the block called SWITCH in Figure 272.
on page 487, one coming from HPC matrix ( H link) and one from LPC matrix (L link).

Rx side: from matrix on MATRIXN to LPA or HPT

the type of signal to be connected ( L if is structured or H if unstructured).

1AA 00014 0004 (9007) A4 – ALICE 04.10

block.

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detection

If the signal is unstructured the incoming signal (H Link) is sent through the SWITCH to the HPT block.

or AIS is detected.
function (TCT/TCM).

Tx side: from LPA or HPT to matrix on MATRIXN

on the MATRIXN. The selection is made according to the type of signal to be connected ( L if is structured
or H if unstructured).





function (TCT/TCM).
1AA 00014 0004 (9007) A4 – ALICE 04.10

HPOM, HSUT BLOCK (HSUT is not operative in this release)

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HPOM performs the monitoring of an equipped path while HSUT performs the termination of an
unequipped path.
From HPOM and HSUT are recovered :

• the primitives used for Performance Monitoring (Errored block count, Defect seconds)

• switching criteria for SNCP/N protection
The two functions are alternative.

HPOM (Higher order path overhead monitoring)

Snm_TT_Sk : signal termination , J1 path recovering , REI information recovering, HP–RDI
detection (path status monitoring) , UNEQ and VC–AIS detection (signal label monitoring), VC4
BIP–8 Errored Block count. TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated
in case of SD.

HSUT (Higher order Supervisory Unequipped termination)

Sns_TT_Sk : path trace information recovery, REI recovery, HP–RDI detection (path status
monitoring), UNEQ and VC–AIS detection (signal label monitoring), VC4 BIP–8 Errored Block count.

Sns_TT_So : generation of an unequipped container , ”unequipped” insertion, trail trace identifier
generation, RDI and /or REI information generation, VC–4 BIP–8 calculation and insertion.








– IMA (Inverse Multiplexing over ATM) RX: NxE1 stream are bundled in a single high speed cell stream;
E1 stream are collected in a cyclical fashion among physical links preserving sequence( for details
on IMA refer to AF–PHY–0086.001).

1AA 00014 0004 (9007) A4 – ALICE 04.10

are counted.

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Interface )






at 622 Mbits/s.

connection identifier is used for each replication (not operative in current release).



the matrix.




– IMA (Inverse Multiplexing over ATM) TX: high speed stream of ATM cells is broken up in the multiple
E1 links( for details on IMA refer to AF–PHY–0086.001)

1AA 00014 0004 (9007) A4 – ALICE 04.10


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[3] MATRIX


[4] MICROPROCESSOR




– communication with the EC on the EQUICO (SNMP Link); using this channel performance and



[5] Common part

• RIBUS I/F


• M–BUS Driver

DC/DC CONVERTERS

– +1.5 Vdc, +3.3 Vdc, , +2.5 Vdc used to supply all the components in the board.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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IMA TX

FILLING CELL IMA FRAME ICP CELL CELL STREAM
INSERTION GENERATION INSERTION SPLITTING HPT

622 MHz

OSC

LPT
É
É
ÉÉ
IMA TX
É
L

Struct/unstruct LPA

HEC SCRAMBLER S

from/to
I
HEC T
HEADER CELLs CELL ATM C H
CORRECTION

IMA RX

HEADER CONGESTION TRAFFIC SPATIAL
UPC/NPC OAM MATRIX
TRANSLATION MANAGEMENT SHAPING

OAM ROUTING

MULTICAST RATE
REDUCTION

IMA RX
FILLING CELL INVALID CELL ICP CELL IMA CELL STREAM
DISCARD DISCARD REMOVE SYNC RECONSTUCTION

SDRAM

FLASH
LEDS(X5) EPROM

LED TEST MICROPROCESSOR PNNI Signalling

EQUICO
SNMP
from/to
RESET

ÉÉ É
ÉÉ
É
ÉÉ
É Management
Bus

M–BUS
Driver
from/to

CMISS
Bus–OFF
Remote RIBUS
Inventory
5V
RIBUS ID
1.5 V
I/F
FROM CONGI

F +3.3 Vdc
Unit
ATM MATRIX 4X4 CONVERTERS
3.3 V 48/60 V
2.5 V
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 273. ATM4X4V2 card – Block diagram

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4.33 ISA – ATM MATRIX 8X8 (ATM8X8)


This unit realize an ATM switching matrix with a total bandwidth of 1.2 Gbit/s. As a matter of fact the unit

is two slot wide and it is connected with the SDH Matrix (MATRIXE) through two link at 622 Mbit/s.

The block diagram of the board has been been divided in two part depicted in Figure 274. on page 499
and Figure 275. on page 500; the part A describe the common part (microprocessor, led, DC/DC
converter) and the signal processing (ATM and SDH) of the first 622Mbit/s link, the part B describe the
signal processing (ATM and SDH) of the second 622Mbit/s link.

ATM flow (E1, E3, VC12, VC3, VC4 and VC4–4c).

The card perform the following function:



[3] MATRIX

[4] MICROPROCESSOR

[5] Common part

The SDH functions are:

– HPT

– LPT and LPA.

MATRIXE board (working in 1+1 configuration).


Two data stream at frequency of 622 MHz are connected to the block called SWITCH in Figure 274. on
page 499 , one coming from HPC matrix ( L link) and one from LPC matrix (X link); the same description
can be applied to Figure 275. on page 500 that depict the part B of the board.

Rx side: from matrix on MATRIXE to LPA or HPT

the type of signal to be connected ( L if is structured or X if unstructured).

block.

1AA 00014 0004 (9007) A4 – ALICE 04.10


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detection

If the signal is unstructured the incoming signal (L Link) is sent through the SWITCH to the HPT block.

or AIS is detected.
function (TCT/TCM).

Tx side: from LPA or HPT to matrix on MATRIXE

on the MATRIXE. The selection is made according to the type of signal to be connected ( L if is structured
or X if unstructured).





function (TCT/TCM).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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N.B. The description that follows can be applied to both Figure 274. on page 499 and Figure 275.
on page 500







are counted.

Interface )




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at 622 Mbits/s.

connection identifier is used for each replication.



the matrix.






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[3] MATRIX



[4] MICROPROCESSOR




– communication with the EC on the PQ2/EQC (SNMP Link); using this channel performance and



[5] Common part

• RIBUS I/F


• M–BUS Driver

DC/DC CONVERTERS

– + 5 Vdc used by the optical module
– +1.5 Vdc, –3.3 Vdc, –3.3 Vdc, –3.3 Vdc, +2.5 Vdc used to supply all the components
in the board.
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System clock a
System clock b

HPT

622 MHz
OSC
LPT

from/to
ÉÉ
ÉÉ
ÉÉ
ÉÉ L
Struct/unstruct LPA

HEC SCRAMBLER S
I
HEC T
CORRECTION

UPC/NPC OAM
HEADER CONGESTION TRAFFIC
ÏÏ
ÏÏ
TRANSLATION MANAGEMENT SHAPING SPATIAL
MATRIX
ÏÏ
ÏÏ
OAM ROUTING
TRANSLATION SHAPING MANAGEMENT ÏÏ
ÉÉ MULTICAST RATE
ÏÏ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
É É
ÉÉÉ É
É É
REDUCTION ÏÏ
ÏÏ
SDRAM ÏÏ
PNNI Signalling
ÏÏ
FLASH
ÉÉEPROM Ï Ï ÏÏÏÏÏ
ÏÏÏÏÏÏÏSee Figure 275.
LED TEST
LEDS(X5) ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏon page 500
MICROPROCESSOR
RESET
ÏÏ
ÉÉ É É
ÉÉÉ
ÉÉ
PQ2/EQC
SNMP

from/to
ÉÉ É
É
ÉÉ
ÏÉÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏ See Figure 275. on page 500
Management
Bus

M–BUS
Driver
from/to

CMISS
Bus–OFF
Remote RIBUS
Inventory
5V
RIBUS ID
1.5 V
I/F
FROM CONGI

F +3.3 Vdc
Unit
ATM MATRIX 8x8 CONVERTERS
3.3 V 48/60 V
(part A) 2.5 V
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 274. ATM 8X8 card – Block diagram part A

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System clock a
System clock b

HPT

622 MHz
OSC
LPT

from/to
ÉÉ
ÉÉ
ÉÉ
ÉÉ L
Struct/unstruct LPA

HEC SCRAMBLER S
I
HEC T
CORRECTION

UPC/NPC HEADER CONGESTION TRAFFIC
OAM
TRANSLATION MANAGEMENT SHAPING

OAM ROUTING

MULTICAST RATE
ÉÉ REDUCTION

ÉÉ
É
ÉÉ
ÉÉ ÉÉ É
ÉÉ
É
É
ÉÉ
É
ÏÏÏÏÏÏÏÏÏÏÏ
Configuration Status (ATM) to /from
ÏÏÏÏÏÏÏÏÏÏÏ É É
ÉÉ
ÏÏÏÏÏÏÏÏÏÏÏ SPATIAL
MATRIX

ÏÏÏÏÏÏÏÏÏÏÏ See Figure 274.
on page 499
ATM MATRIX 8x8
(part B)
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 275. ATM 8X8 card – Block diagram part B

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4.34 ISA–Packet Ring Edge Aggregator Unit (PREA1GBE, PREA4ETH)

(See Figure 277. on page 507.)

There are two types of PR_EA:

a) in the first version (PREA4ETH), it hosts a 4 x 10/100 BaseT Fast Ethernet module and the total
traffic throughput is 1 Gb/s, in which 622Mb/s are contributed by the SDH matrix, and 400 Mb/s
contributed by the 4 Fast Ethernet local ports.

b) in the second version (PREA1GBE), it hosts a 1 x 1Gigabit Ethernet module and the total traffic
throughput is 1.8 Gb/s, in which 622Mb/s are contributed by the SDH matrix, and 1.25 Gb/s
contributed by the GbEthernet local port.

The unit allows the management of packets data services over Ethernet and their transportation over the
SDH network. The ethernet packets are labelled and then mapped onto SDH frames via PPP/HDLC
framing. The ethernet access is possible either local and remote, this latter via GFP/SDH framing; ethernet
links can be type E, FE, GE (10Mb/s, 100Mb/s, 1Gb/s).

The SDH containers used for data transportation are VC–12, VC–3, VC–4.

The MPLS traffic can be connected to 63 logical ports.

The functions implemented on the board are the following:

4 x Ethernet Module (case of MPLS+4FE board):

– It implements four Ethernet transceiver interfaces, compliant to IEEE 802.3 standard, Carrier Sense
Multiple Access with Collision Detection (CSMA/CD), that can be connected to Local Area Networks
(LAN) conveying data packets over Ethernet.
The interface type is 10/100Base–T, operating at rates 10 or 100Mb/s, using baseband
communication on a twisted pair cable, connected by means of RJ45 connector.
Its main functions are:
• line isolation
• operations auto–negotiation, about the following options: 10Mbps or 100Mbps, full–duplex
• receive data and clock recovery, transmit pulse shaping
• carrier sensing for collision detection
• transmission conflicts management.

1 x GigaEthernet Module (case of MPLS+1GE board):

– It is a pluggable, small–form factor pluggable module (SFP), implementing the optical to electric
conversion, and viceversa, to accomplish a full–duplex Gigabit Ethernet interface at 1.25 Gb/s, as
specified in IEEE802.3. For its description refer to para. 4.19, page 430 (”Gbit Eth. i/f Module”).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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SDH termination:

– SWITCH: The task of the SWITCH block is to send the signals coming from HPT or LPT block
towards the matrices on the MATRIX unit. The selection is made according to the type of signal to

be connected (L if it is structured, X if unstructured). The “L” signals are sent to LPT – LPA blocks,

the “X” to the HPT.

– HPT: this block adds/removes the high order POH bytes to the C–4 unstructured payloads (bulks).

– LPT: The LPT function terminates a VC–12 or a VC–3 by adding or removing the relevant POH bytes
to a C–12 or a C–3.

– LPA: This block adapts the low order payloads C12 or C3 to the higher order containers used for
transportation in the SDH (TU–12 or TU–3). The adaptation includes timing synchronization and
frame offset with pointers movements.

– Struct/Unstr: this selector sends the bulk signals (unstructured) to HPT, while the structured signals
are sent to LPA–LPT.

Framing:

– PREAMBLE: it provides to remove (toward MPLS direction) the “preamble” and
“start–of–frame–delimiter” fields from the ethernet MAC 802.3 header (Medium Access Control), and
to reinsert them toward ethernet direction; then it recalculates the FCS value. ( Moreover it decodes
the “Tag” fields of the MAC client header (if present): 802.1p and 802.1q, to read the user priority and
the VLAN identifier. The in/out ethernet data are 2–bit paralleled at 50Mb/s in case of E or FE; 8–bit
at 125 Mb/s in case of GE.

– BUF: it is a buffer in which the ethernet data are written by means of a smooth ethernet clock, as they
are ready, and are then read by the MPLS mapper (PUSH). In case that the buffer is near to full the
mechanism of flow–control is started, in order to slow down the ethernet data source.

– PUSH: it provides to “push in” the first label to the ethernet packet (the second label is pushed by the
MPLS router), after having inspected the ethernet header, identified the destination and the class of
service. It classifies the packets according to the 802.1p/q “VLAN–Tag” and “User Priority” fields, if
configured. Depending on the type of decoded ethernet SLA (Service Level Agreement) the stream
can be associated with one of three types of QoS (Quality of Service): Best Effort bandwidth
(BE–BW), or Min–BW with regulated bursts, or Guaranted constant BW.

– POP: It provides to “pop out” the label from the packet, returning the bare ethernet frame.

– GFP: it provides to deassemble (toward MPLS direction) the GFP frames (Generic Framing
Procedure), removing the GFP header, and to assemble them toward SDH direction. It supports
un–concatenated ethernet frames over unstructured VC4 payloads.

– HDLC: it provides (refer to rec. RFC 1662 and RFC 2615):
• to deassemble (MPLS direction) the HDLC frames (High–Level Data Link Control), removing
the HDLC header, and to assemble them in SDH direction;
• FCS calculation (Frame Check Sequence);
• byte stuffing/destuffing: flag sequence or other header octets are encoded by a 2–octet
sequence, in the data field, in order to avoid erroneous simulations of the header;
• inter–frame filling, by means of the “flag–sequence” (hex 0x7e) repetition;
• X^43 +1 data scrambling/descrambling.
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– PPP: it provides to deassemble (in MPLS direction) the PPP frames (Point–to–Point Protocol),
removing the PPP header, and to assemble them in SDH direction. It carries out, optionally, the
“Martini encapsulation”, removing the FCS field from the ethernet frame and inserting a checksum
value for the MPLS packet.

– A: this block provides to adapt the serial bus from the back–panel bus format to the intra–board bus
format, for SNMP messaging between the microprocessor and the EC (equipment controller), for
MPLS network configuration.

– SMAP: it provides, toward MPLS direction, to “unload” the data packets from the SDH frames, and
to “load” them in SDH direction; the packets are then switched toward GFP or HDLC processing,
according to the logical ports configurations.

MPLS Router:

It performs the routing functions by looking the top MPLS label, it can forward the packets streams
to up to 63 SDH or ethernet ports.
In the MPLS network, it provides to inspect the top label of the MPLS packet in order to identify the
incoming FEC and LSP; if possible, it aggregates the packet to other packets streams on a common
path, then it selects the forwarding to a next hop by swapping the top label.
At the edge of the MPLS network (originating node), on receiving packets from the local or remote
ethernet interfaces, it provides to push the top label reporting information for the routing procedure
(LSP and FEC).
At the edge of the MPLS network (destination node), on receiving packets from the network, it
provides to pop out the top label and drops them to the destination end port.
At the beginning of a packets stream introduction, the microcontroller starts the RSVP–TE signalling
(Resource Reservation Protocol – Traffic Engineered Tunnel) in order to search and establish a path
with a certain band capacity and a given priority, between the destination and the source node; this
path can be treated as a tunnel and is called LSP (Label Switched Path); once the LSP has been
established, the RSVP signalling finishes and starts the Label Distribution Protocol (LDP) signalling,
that informs all the nodes of the network to maintain the label bindings for the relevant established
LSP. The RSVP and LDP signalling are in–band communications between the local and remote
microcontrollers.
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Queuing management:

– It provides to monitor the load of traffic in the local router, and to take measures for preventing the
congestions, supported by the intra–board microcontroller, such as: management of many different

queues and relative priorities, packets queuing, packets discarding, packets lifetime management,

etc. It implements, mainly, for this function, the following mechanisms:
• 256 queues for each “logical” port (the logical ports number is 63)
• scheduling, by means of HOL or WC–WFQ or WNC–WFQ methods
• congestion avoidance via W–RED method (Weighed–Random Early Discarding): in
occurrence of congestion conditions signals, a random packets discarding is started, in order
to prevent the traffic worsening.
• The priority management is based on the ethernet SLA (Service Level Agreement), by means
of CIR and PIR values of the traffic contract.
• Three types of QoS (Quality of Service) are available: Best Effort bandwidth (BE–BW), Min–BW
with regulated bursts, Guaranted constant BW.
• A “Dual–Rate Leaky–Bucket” police mechanism is used (it can be seen as two cascaded leaky
buckets, the first based on PIR value, the second on CIR).
• In case of congestion, only the low priority traffic will be cut–off, while the high priority traffic
maintains the guaranted BW.
• The Best–Effort traffic deployed in ring topology can be associated to a “Fixed Share” of the total
available band, or to a “VariableProportional Share”. In case of congestion the BE excess
traffic will be cut–off via W–RED.
• Packets shorter than the minimum ethernet frame are silently discarded. Packets longer than
the maximum frame are silently discarded. The discarded packets are counted by the PM
function.
• Note: the priority and the BW parameters are marked on the first label, at the “PUSH1” function
of the ingress node.

Microprocessor:

– It is a local microcontroller managing and supporting the MPLS functionalities, such as:
The RSVP–TE and LDP communications between the destination and the origination nodes,
in order to establish the routing and the LSP tunnelling.
Management of communications with the EC and the network Operations System (OS), by
means of SNMP (Simple Network Management Protocol) messaging, for MPLS network
configuration.
Configuration of the MPLS functions implemented by the devices on the board, by means of
ICMP (Internet Control Message Protocol) messaging.
Collection of alarms and status of the MPLS functions.
Management of the Performance Monitoring (PM) function for MPLS.
Management of Multicast traffic.
Management of OSPF (Open Shortest Path First) routing (not operative).
Furthermore it aids the congestion control function, supporting the “Queuing Manager”
Communications with the EC, by means of the ISSB–EC bus, for software data transfer.
It is provided with relevant SDRAM and Flash EPROM devices, for data and software storage.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Other functions implemented on the board are:

• RIBUS I/F
This block is used to read/write from/to the ”RIBUS” serial stream, to control the LED on the unit,

to release the Management–bus in case of power failure, and to use the remote inventory.

RIBUS I/F is powered by the + 3.3 VS supplied by the rear access panel.

on page 370 for details about Remote Inventory information).

• M–BUS Driver
It drives the input–output gates of the parallel Management–bus. These drivers can be disabled
(by the Bus–OFF signal) in case of power failure.

DC/DC CONVERTERS

This block converts the 48/60 V power supply, to obtain the voltages used to supply all the
Power–Sync, generated by the SDH asic) in order to avoid EMI problems.

• LEDS and Push–buttons
The board presents, on its front panel, some LEDS and push–buttons; the meaning of these
LEDs and Push–Buttons is reported in Figure 52. page 141. and Figure 53. page 142.

• Buses
The main buses on the board are:
SNMP: serial bus to carry SNMP (Simple Network Management Protocol) messages between
the EC and the intra board controller, for information about MPLS network configuration. This
link is implemented by means of the DCC–EC bus from EC on EQUICO unit.
ISSB–EC: Intra–Shelf–Serial–Bus from the EC, to communicate software data (download,
etc.).
ISSB–SPARE: serial bus to the spare MPLS unit (if any) to communicate EPS information (.
SDH–CS: from the EC, after derivation from the parallel “Management–bus” (M–bus), for
configuration and status information of SDH components.
MPLS–CS: from microprocessor, for configuration and status information of MPLS
components, it conveys ICMP packets.
RIBUS: serial bus from the SC (shelf controller on MATRIX unit), to communicate inventory and
peripheral data.
M–BUS: called also ISPB (Intra Shelf Parallel Bus), from the SC (shelf controller on MATRIX
unit), to communicate data about asics configuration, SDH alarms collection, etc.
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RSOH, MSOH, F2, F3 SOH AUX from/to
bytes SERVICE
HPOM
HSUT System clock (T0)

RST MST MSA

HPT H
622 MHz
DCCR DCCM
OSC

MATRIXE main and spare
RSOH MSOH
10/100 Mb/s FAST ETHERNET

LPT

from/to
SDH–CS
4 x FE
2@50Mb/s
SDH–CS

PREAMBLE LPA X
GFP

SMAP
BUF S
PPP HDLC W
I
Struct/unstruct T
GFP C L
SMAP
H
HDLC

PPP A
POP POP
PUSH PUSH

PQ2/EQC
from/to
QUEUING MPLS SNMP SNMP
MPLS–CS
MANAGEMENT ROUTER

SDRAM
MPLS–CS MPLS–CS

SPARE MPLS UNIT
FLASH
EPROM
(EPS)
Configuration Status
ÀÀÀÀÀÀÀÀÀÀ
from/to
ISSB–SPARE
for MPLS (MPLS–CS)
ÀÀÀÀÀÀÀÀÀÀ
MICROPROCESSOR

RESTART ISSB–EC MATRIXE MAIN AND SPARE
ÀÀÀÀÀÀÀÀÀÀÀ
ÀÀÀÀÀÀÀÀÀÀÀ Management
from/to

Bus (ISPB)
Configuration Status M–BUS
for SDH (SDH–CS) Driver
CMISS
Bus–OFF
Remote RIBUS
Inventory
5V
1.8 V RIBUS ID
I/F F +3.3 Vdc
DC/DC Unit
CONGI

3.3 V
FROM

CONVERTERS Failure
2.5 V 48/60 V

MPLS + 4 x FAST ETHERNET
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 276. MPLS+4FE Unit (PREA4ETH) – Block diagram

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SOH AUX from/to
RSOH, MSOH, F2, F3
bytes SERVICE
HPOM
HSUT System clock (T0)

RST MST MSA

HPT H
622 MHz
DCCR DCCM
OSC
RSOH MSOH

MATRIXE mainand spare
1 GIGABIT ETHERNET I/O

LPT

from/to
SDH–CS
1 x GBE
8@125Mb/s SDH–CS

PREAMBLE LPA X
GFP

SMAP
BUF S
PPP HDLC W
I
Struct/unstruct T
GFP C L

SMAP
H
HDLC

PPP A
POP POP
PUSH PUSH

PQ2/EQC
from/to
QUEUING MPLS SNMP
MPLS–CS
MANAGEMENT ROUTER SNMP

SDRAM
MPLS–CS MPLS–CS

FLASH

SPARE MPLS UNIT
EPROM
(EPS)
Configuration Status
ISSB–SPARE

from/to
for MPLS (MPLS–CS)
MICROPROCESSOR

RESTART ISSB–EC
ÀÀÀÀÀÀÀÀÀÀÀ Management
Bus (ISPB)
from/to

CMISS
Bus–OFF
Remote RIBUS
Inventory
5V
1.8 V RIBUS ID
I/F F +3.3 Vdc
DC/DC Unit
3.3 V Failure
CONGI

CONVERTERS
FROM

2.5 V 48/60 V

MPLS + 1 x GIGABIT ETHERNET
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 277. MPLS+1GbE Unit (PREA1GBE) – Block diagram

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4.35 ISA – Packet Ring unit (ISA–PR)

The role of the ISA–PR functionality inside 1660SM is to provide a shared carrier–class Ethernet Packet
Ring embedded either physically or logically into the SDH infrastructure, in a flexible manner over SDH

Virtual Containers.

The ISA–PR Packet Ring transports and aggregates Metro Ethernet traffic within a metro access or metro
core SDH access ring/rings, all packet traffic is statistically multiplexed, with multiple Classes of Services
and guaranteed QoS support (according to the defined SLA).

The ISA–PR port card is used in conjunction with the 16FEA–PR and 2GBA–PR Access cards.

These Access cards are described in para. 4.11 at page 408 and 4.12 at page 4.12 respectively.

Functional Overview

The diagram below shows the main functional blocks of the ISA–PR port card and interconnections to the
access cards
I2C bus

RI GigaBit
RI GMII GMII Ethernet
RI MII1 MII16 FE
Access
RI Access
Card Card
NP NP

RGGI RGGI
RGGI RGGI

AC (Access chip)
AC
1G(Ser)
1GHost
1GHOST

Craft Terminal NMS
1GData
1GData

1G(Ser) 1G(Ser)
1G(Ser) 1G(Ser) 1G(Ser)

Octal SerDes GMII
Host Host Octal SerDes
GMII
1G 1G 1G 1G
1G

1G

RI Port
Unit
Led
BT–Stratix2 Card
BU
param 6G(in) HSI 4G(eg)
SRAM
CI Map Mac
Bu Policer/
SRAM I/F
Stratix1
Channel Policer
Scheduler
BM–Stratix1
Channel
Table Scheduler
ATI 32 (2.4G)
ADM – OC12/OC48
PM
param Stratix2
Utopia 32bits
2Phy(4)
EDC Daughter Framer
Board TADM
Power – Batt / Ground
from Congi
Optical transceiver Modules
1AA 00014 0004 (9007) A4 – ALICE 04.10

STM4 line signals

Figure 278. PR unit functional block diagram

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The main functional blocks of the ISA–PR port card are as follows:

• Optical transceivers – Physical ring interfaces: STM–4.

•

Framer ADM – Provides the SDH framing.

• ADM (Add Drop Multiplexer) – Extracts traffic to be dropped in this port card, and merges
traffic received from the access cards with through traffic on the ring.

• Bandwidth Management – This block incorporates SLA control policing and buffer
management. It is this block that determines the precedence and delay with which packets are
forwarded to/from the ring.

• Host – System controller responsible for the local management of the ISA–PR port card and
access cards. The host communicates with the different elements of the ISA–PR series via
dedicated control paths. Loss of a host card through a fault does not affect the delivery of
customer traffic. The host card can communicate via one of two interfaces:

– External Ethernet interface presented on the faceplate of the ISA–PR port card.

– Internal Ethernet interface transported in the payload of the packet ring; used for in band
communication between network elements and between network elements and the NMS.

• EDC (Extended Differential Delay) – The EDC block is implemented on a daughter board. The
block is essential to meet various SDH underlay Route Diversity scenarios (Route Diversity
refers to SDH signal delivery across more than one fiber in parallel).

Data Path Access to Port
The port card receives classified and edited frames from the Network Processor block on the access card.
These incoming frames are presented to the bandwidth management block for processing.

The bandwidth management block performs:

Frame Policing and Marking (crucial component in providing MEF compliant services).
Frame marking refers to the method whereby some frames may be marked for possible discard.
Under congestion conditions only these frames will be considered for discard.

Buffer Management, i.e. frame storage in memory in the proper order till it is forwarded.

Scheduled frame forwarding to the various destinations subject to bandwidth availability, priorities,
Load Balancing considerations etc. Note that all destinations are possible, i.e. Ring interfaces at the
Trunk card, Ethernet interfaces at a Line card, any combination thereof.

Buffer Management may discard frames in course of Policing.

The next stage is the ADM block where through traffic from the ring is merged with traffic generated within
this system. Frames are forwarded according to priority criteria to the Framer.
The Framer maintains the Ring interfaces and maps the frames onto them.
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Data Path Port to Access
The ISA–PR port card receives ring traffic over the SDH optical interfaces. The framer, which hosts the
Ring interfaces, recovers and validates the frames and forwards them to ADM

The ADM looks up the network tag (MPLS) makes a decision according to the following criteria:–

• Drop
• Drop forward
• Forward
• Discard decision.

All frames that are due to be forwarded on the ring are merged with locally generated frames.

All frames that are dropped from the ring are forwarded to the bandwidth management block.

The bandwidth management block buffers the frames till they can be forwarded to the Access cards,
subject to bandwidth availability, congestion conditions and frame priorities.

Control

The ISA–PR port card is managed via the host controller housed on the port card itself.


LEDs on the ISA–PR faceplate provide indications as specified in the table below.

Table 54. PR unit LED designation


ON = Minor
OK YELLOW

ON = Major/Critical alarms on ISA–PR or Slot alarms in Access
Card or Major transmission alarms on Access Card. Access card
slot alarms stand for: Card Mismatch, Card Unassigned Card
failure on POST (Power On Self Test)
OK RED
Blinking 50/50 = during the POST (Power On Self Test) failure.
On POST completion the LED will change its color according to
the card status afterwards

ON = OK Status
OK GREEN Blinking 50/50 = ISA–PR in initialization process (following
power–on or reset)



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Physical Interfaces

The faceplate for the ISA–PR port module (shown in Figure 54. on page 143) presents the following
connectors:

SFP optical connections for SDH ring interfaces. The interfaces are designated W1 and W2 for West
ring interface and E1 and E2 for East ring interface

RS232 – RJ45 connector, allows for connection of a local console interface for use by a qualified
engineer for debug purposes

Eth (Ethernet Management interface) – RJ45 connector, enables local connection to the web based
craft interface. This interface can also be used to connect to the NMS (Network Management
System) via a data communications network (DCN).

Power

The ISA–PR port module receives 48v DC from the backplane and converts to lower voltages for local use.
The power consumption of the ISA–PR port module is 50 Watts.
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4.36 STM–16 optical port (two slots wide)


The description is applicable to all the STM–16 optical ports of this release; up to four STM–16 optical port

can be inserted in 1660SM.

The units can be distinguished by letters L, S and I defining their dependance on optical components used
for Long distance, Short distance or Intra Office.
The Input/output unit optical connectors can be accessed from the unit’s front coverplate. The units which
operate in the second window are indicated with 16.1, those operating in the third window with 16.2.

The units are identified by the type of connector used SFF, FC/PC or SC/PC or SC/SPC connectors.

The units identified by JE (Joint engineering) have better optical characteristics, typically for the dispersion
values and sensitivity (see Table 68. on page 631).
The STM–16 with ”192.3 to 195.7” indication (also defined ”colored”), are used when interfaced with WDM
equipment. That number indicates the central frequency (in Thz) of the carrier optical signal, related to the
wavelength.
These sixteen units are independently characterized by different wavelength.
The WDM equipment must receive up to sixteen different wavelength signals from sixteen different
STM–16 optical port.

The SDH functions required to manage STM–16 signal are implemented by four G.A. ( G.A#1 to G.A.#4
in Figure 279. on page 517) mounted on the board. They interface the two MATRIX boards via backpanel.

Another G.A. (G.A.#5 in Figure 279. on page 517) is present with MUX/DEMUX and loop functions. This
G.A. interface the line side with one stream at 2488 Mbit/s an the equipment side with four stream at 622
Mbit/s.
Two types of loops are possible inside G.A.#5:

• Line loop
• Internal loop

Referring to the ITU–T G.783 recommendation, the four G.A. performs the following functions :

– TTF (only the G.A. #1 )

– HOA (all G.A. from 1 to 4)

– LPOM /LSUT (all G.A. from 1 to 4). The last is not available in this release

– HPOM /HSUT ( only the G.A.#1). The last is not available in this release

1+1 configuration).

The TTF block is connected to the two MATRIX boards through four bidirectional links at 622 Mbit/s in
1+1 configuration (H link).

through two bidirectional link at 622 MBit/s each in 1+1 configuration (”X link” and “L link” respectively)
.
Backpanel interface supply a system–clock (SYST CK) to the G.A. internal circuits
1AA 00014 0004 (9007) A4 – ALICE 04.10

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The G.A.#1 send and receive four 622 Mbit/s signal (data + clock) to/from the G.A.#5

Laser Failure.

The ALS algorithm is hardware implemented and the G.A. provides the Laser shut Down command
(LASER OFF).



STM–16 signal.



alarm.



justification. Sixteen MSA blocks are present.

Moreover the following functions are performed on the Input side :


MATRIX board.

K1,K2, bytes towards the MATRIX board. The bytes are extracted from the line when a TSF is
received and they are transmitted towards the two MATRIX board.
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The sixteen AU4 structure are byte interleaved in the STM–16 structure with fixed phase relationship

vs. the same multiple signal.

insertion.






is detected.

Moreover :


function (TCT/TCM).



insertion,


Moreover:


(TCT/TCM).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Rx and Tx side.



• REI recovery




RX and TX side:









1AA 00014 0004 (9007) A4 – ALICE 04.10



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• RIBUS I/F

– release the Management–bus in case of power failure
– read remote inventory data.

• TONE MODULATOR MANAGEMENT

This block is used by the STM–16 optical port with ”192.3 to 195.7” indication. In this block
is present a”WDM tone generator”, which starting from the data written in the remote inventory,
fix the appropriate wavelength transmitted to the WDM equipment.

on page 370 for details) and additional data for operation of the board in WDM application.

• M–BUS Driver



– + 2.5 V
– + 3.3 V
– –5V
– +5V

The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power
Sync) , generated by G.A.#1) in order to avoid EMI problems.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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622 MHz SYST CK A/B
OSC G.A.#1 T1
to/from
Laser Restart HPC matrix ( X link)
HPT

CK Power Sync HOA to/from

LPC matrix (L link)
HPA

main and spare
2488 Mbit/s 4 x 622 Mbit/s
LPOM (*)
OPTICAL
G.A.#5 TTF
LSUT
INPUT/ F2, F3 HPOM (*)

from/to
OUPUT
MUX HSUT to/from
O/E SPI / K1,K2 HPC matrix

MATRIXE
DEMUX (H link)
Tx side RST MST MSA K1,K2,TP
Insertion
Rx side to/from
Insertion HPC matrix
DCCR DCCM (H link)
RSOH MSOH MSA
Line loop to/from
HPC matrix (H link)
Internal loop MSA
LOS to/from
HPC matrix (H link)
LASER D. MSA
LASER F. DCC
LASER OFF from/to
AUX PQ2/EQC
F2, F3 from/to
Tone SERVICE
SYST CK A/B

from/to MATRIXE
main and spare
G.A.#2 to/from
HPC matrix ( X link)
HPT
HOA to/from
LPC matrix (L link)
CK HPA

LPOM (*)
LSUT from/to
F2, F3 AUX SERVICE
F2, F3

from/to MATRIXE
SYST CK A/B

main and spare
G.A.#3 to/from
CK HPT
HOA to/from
Notes: (*) – HSUT and LSUT are not operative in current release

LPC matrix (L link)
HPA

Tone LPOM (*)
LSUT from/to
F2, F3 SERVICE
F2, F3 AUX

from/to MATRIXE
SYST CK A/B
Tone
main and spare
modulator G.A.#4 to/from
management HPC matrix ( X link)
CK HPT
HOA to/from
M–BUS LPC matrix (L link)
HPA
Driver
Remote LPOM (*)
Inventory LSUT from/to
Bus–OFF SERVICE
F2, F3 AUX
F2, F3
ID Management Bus
Line loop RIBUS
Internal loop I/F RIBUS
2.5 V Power Sync
+3.3 Vdc
3.3 V DC/DC 48/60 V
Unit 5V CONVERTERS
Failure from
STM–16 OPTICAL PORT –5 V +3.3 Vdc CONGI
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 279. STM–16 optical port block diagram

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4.37 STM–16 optical slim port (one slot wide)


The description is applicable to all the STM–16 optical “slim” ports of this release; up to sixteen STM–16

optical port can be inserted in 1660SM.

The units can be distinguished by letters S (S–16.1) and I (the last is not available in current release)
defining their dependance on optical components used for Short distance or Intra Office; the units operate
in the second window
The Input/output optical connectors can be accessed from the unit’s front coverplate.; as a matter of fact
the unit must be equipped with a SFP plug–in optical module where the fiber cable is connected.
The WDM equipment must receive up to sixteen different wavelength signals from sixteen different
STM–16 optical port.

The SDH functions required to manage STM–16 signal are implemented by four G.A. ( G.A#1 to G.A.#4
in Figure 279. on page 517) mounted on the board. They interface the two MATRIX boards (via
backpanel) through a SERDES device (serializer/deserializer) the task of wich is to serialize the 622Mbit/s
signals (coming from the four G.A). into few 2.5 Gbit/s signals (one for each link H, L, X).

Another G.A. (G.A.#5 in Figure 279. on page 517) is present with MUX/DEMUX and loop functions. This
G.A. interface the line side with one stream at 2488 Mbit/s an the equipment side with four stream at 622
Mbit/s.
Two types of loops are possible inside G.A.#5:

• Line loop
• Internal loop

Referring to the ITU–T G.783 recommendation, the four G.A. performs the following functions :

– TTF (only the G.A. #1 )

– HOA (all G.A. from 1 to 4)

– LPOM /LSUT (all G.A. from 1 to 4). The last is not available in this release

– HPOM /HSUT ( only the G.A.#1). The last is not available in this release

1+1 configuration).

The TTF block is connected to the two MATRIX boards through four bidirectional links at 622 Mbit/s in
1+1 configuration (H link).

HOA block is connected both to the HPC and LPC matrices on the two MATRIX boards via SERDES
device through bidirectional link at 2.5 Gbit/s 1+1 configuration (”X link” and “L link” respectively) .
Backpanel interface supply a system–clock (SYST CK) to the G.A. internal circuits
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The G.A.#1 send and receive four 622 Mbit/s signal (data + clock) to/from the G.A.#5

The optical transmitter provides to the G.A. its status by Laser Failure signal.

The ALS algorithm is hardware implemented and the G.A. provides the Laser shut Down command
(LASER OFF).



STM–16 signal.



alarm.



justification. Sixteen MSA blocks are present.

Moreover the following functions are performed on the Input side :


MATRIX board.

K1,K2, bytes towards the MATRIX board. The bytes are extracted from the line when a TSF is
received and they are transmitted towards the two MATRIX board.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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The sixteen AU4 structure are byte interleaved in the STM–16 structure with fixed phase relationship

vs. the same multiple signal.

insertion.






is detected.

Moreover :


function (TCT/TCM).



insertion,


Moreover:


(TCT/TCM).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Rx and Tx side.



• REI recovery




RX and TX side:









1AA 00014 0004 (9007) A4 – ALICE 04.10



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• RIBUS I/F

– control the SERDES SETTINGS device (sending configuration etc.)

on page 370 for details)

• M–BUS Driver



– + 2.5 V
– + 3.3 V
– 1.8 V
– 1.2 V

The DC/DC converter is synchronized with a synchronization clock at 300 MHz (signal Power
Sync) , generated by G.A.#1) in order to avoid EMI problems.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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T1
622 MHz
SYST CK A/B
OSC G.A.#1
to/from
Laser Restart HPC matrix( X link)
HPT

CKPower Sync to/from

main and spare
HOA

LPC matrix (L link)
HPA
2488 Mbit/s 4 x 622 Mbit/s
LPOM(*)
OPTICAL
G.A.#5 TTF
LSUT
(H link)
INPUT/ F2, F3
OUPUT HPOM(*)
MUX HSUT to/from S

from/to MATRIXE
O/E SPI / K1,K2 HPC matrix E (L link)
DEMUX (H link) R
Tx side RST MST D
MSA K1,K2,TP E ( X link)
Insertion
Rx side to/from S
Insertion HPC matrix
DCCR DCCM (H link)
RSOH MSOH MSA
Line loop to/from
HPC matrix (H link)
Internal loop MSA
LOS to/from
HPC matrix (H link)
MSA
LASER F.
LASER OFF DCC from/to
PQ2/EQC
F2, F3 AUX

SYST CK A/B
G.A.#2 to/from
HPT
HOA to/from
LPC matrix (L link)
CK HPA

LPOM (*)
LSUT
F2, F3
F2, F3 AUX

SYST CK A/B
G.A.#3 to/from
HPC matrix( X link)

SERVICE
HPT

from/to
CK to/from
HOA
Notes: (*) – HSUT and LSUT are not operative in current release

LPC matrix(L link)
HPA

LPOM(*)
LSUT
F2, F3
F2, F3 AUX
SERDES SYST CK A/B
SETTINGS to/from
G.A.#4 HPC matrix( X link)
CK HPT
HOA to/from
M–BUS LPC matrix(L link)
HPA
Driver
Remote LPOM (*)
Inventory LSUT
Bus–OFF
F2, F3
F2, F3 AUX
ID Management Bus
Line loop RIBUS
Internal loop I/F RIBUS from/to
MATRIXE
2.5 V Power Sync main
+3.3 Vdc
and spare
3.3 V DC/DC 48/60 V
Unit 1.8 V CONVERTERS from
Failure STM–16 OPTICAL SLIM PORT +3.3 Vdc
1.2 V CONGI
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 280. STM–16 slim port block diagram

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4.38 STM–64 optical port


Function of this unit is to be the STM–64 Port (9.95328 Gbit/s bit rate) of 1660SM system. It connects, via

optical fibers, the system to the Transmission Network.

The units can be distinguished by letters I, S and L defining their dependance on optical components used
for Intra Office distance (links up to 2 Km), Short distance (links up to 40 Km) or Long distance .
The Input/output unit optical connectors can be accessed from the unit’s front coverplate. The unit
operating in the third window is indicated with 64.2.

The units are identified by the type of connector used, FC/PC connectors.


The dimensions of this unit is two slots wide.

The Physical layer, the Regeneration section and multiplex section layer are terminated/ generated in this
board, and also the Multiplex section adaptation is processed.

The interface can support 64 x VC4 containers or 16 x VC4–4c containers or 4 x VC4– 16c containers or
1 x VC4–64c container. High Order and Low Order VC processing is carried out by the board.

The whole line capacity (up to 64 AU4s) are managed by matrix at HO level; half capacity (up to 32 AU4s)
of the whole line capacity is managed by matrix at LO level.

The SDH functions required to manage STM–64 signal are implemented by nine G.A. ( G.A#1 for TTF
function and from G.A.#2 to G.A.#9 for LVC function ) mounted on the board. The board interfaces the
two MATRIX boards via backpanel with links at 2.5 Gbit/s.

RX side functions

• Optical to electrical conversion at 9.95328 Gbit/s bit rate; at the input side are also detected the
following alarms:

– LOS (Loss Of Signal)
– LASER DERADE
– LASER FAIL

• Demultiplexing from 9.95328 Gbit/s to 16 x 622 Mbit/s by means of a 1:16 DEMUX device;

• Demultiplexing from 16 x 622 Mbit/s to 32 x 311 Mbit/s by means of a 1:2 DEMUX device in order
to interface the G.A.#1.

• TTF function (RST Sink, MST Sink, 64 x SA,). These functions are performed by GA #1

• Serializer: SERDES block serialize the signal coming from G.A.#1 to G.A.#9 and interface the
two MATRIXE boards with links at 2.5 Gibit/s (H, L, X links).

• LVC (lower order path ) function: us above mentioned 8 G.A. ( G.A.#2 to G.A.#9 ) are present
in order to process the SDH signal at low order level.
1AA 00014 0004 (9007) A4 – ALICE 04.10

Up to 32 VC–4 max. can be structured at low order by means of Craft Terminal or O.S settings
LVC are connected to the two MATRIX via SERDES device.

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TX side functions

• Serializer: SERDES block de–serialize the signal coming from the two MATRIXE (H, L, X links
at 2.5 Gibit/s ) into 16x622 Mb/s signals forwarded to G.A.#1 – G.A.#9.

• TTF function (64 x SA, MST Source, RST Source ). These functions are performed by GA #1

• LVC (lower order path ) function: us above mentioned 8 G.A. ( G.A.#2 to G.A.#9 ) are present
in order to process the SDH signal at low order level.

• Multiplexing from 32 x 311 Mbit/s to 16 x 622 Mbit/s by means of a 2:1 MUX device

• Multiplexing from 16 x 622 Mbit/s to 9.95328 Gbit/s by means of a 16:1 MUX device;

• Electrical to Optical conversion at 9.95328 Gbit/s bit rate; at the output side the command
LASER OFF , switch off the LASER


• RIBUS I/F

– control the SERDES SETTINGS device (sending configuration etc.)

on page 370 for details)

• M–BUS Driver


– + 3.3 V
– 1.8 V
– 1.7 V
1AA 00014 0004 (9007) A4 – ALICE 04.10

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G.A.#9
16x

622Mb/s

G.A.#2
LVC
PROCESSING
#4
LVC #3
LVC #2
LVC
#1
LVC
Laser Restart (H link)
LOS
LASER D.
LASER F.

MATRIXE main and spare
CKR
(L link)
16x 32x G.A.#1 SERDES

from/to
INPUT 622Mb/s DEMUX 311 Mb/s
O/E CKR 1:16
DEMUX 1:2 TTF

( X link)
16x 32x
16:1 622Mb/s MUX 311 Mb/s
O/E TTF
MUX 2:1
OUPUT

LASER OFF CK

622 MHz
LP Filter
OSC

SERDES
M–BUS SETTINGS
Driver
Remote
Inventory
Bus–OFF

ID Management Bus
RIBUS
I/F RIBUS

Unit
Failure

3.3 V
DC/DC 48/60 V
1.8 V CONVERTERS from
+3.3 Vdc CONGI
1.7 V

STM–64 Optical Port
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 281. STM–64 optical port block diagram

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4.39 ISA – Ethernet/Fast Ethernet port (ETH–MB)


The ETHERNET–PORT is a new unit able to process twenty–five (10/100 Mbit/s) Ethernet and fast

Ethernet streams and to map them towards the SDH world.

The Ethernet frames are inserted into a GFP (Generic Framing Procedure) packet which is a universal
container for data traffic.

The unit is able to execute a RATE ADAPTING action, hence it is able to cross–connect a 10/100Mbit/s
ETHERNET stream towards an SDH virtual container of any dimension (VC12, VC3, VC4).

The Ethernet unit is able to memorize all the frames composing the incoming 10Mbit/s signal in a pseudo
hard disk made up of eight RAM (1Mx18bit) memories to be forwarded to the selected VCx.

Should the memories be filled up without emptying them in the Vcx, a flow control intervenes. The latter
is able to communicate to the Ethernet transmitter to reduce or interrupt the frame transmission up to
recovering the stable condition of the archived frames versus the ones sent over the SDH VC.

All the write and read operations occur at the 125 Mhz frequency in order to reduce the risk of memory
stuffing.

The same operation will also be executed on the Tx side, i.e. the frames contained in the SDH virtual
containers will pass in the RAMs before to be forwarded to the outgoing Ethernet stream.

The ETH–ATX access port can be utilized in order to supply the highest number of Ethernet ports; it is
provided only with a physical Ethernet interface facing with the ETHERNET–PORT (ETH–MB) via
backpanel as regards the management and cross–connection functions towards the SDH world.

In this manner 11 interfaces are made available on the ETHERNET–PORT and 14 interfaces are made
available on the ETHERNET ACCESS for a total amount of 25 10/100Mbit/s streams.

The ETH–MB can also be used in conjunction with the Gigabit Access card GETH–AG in order to process
two 1.25 Gbit/s Ethernet stream and eleven 10/100 Mbit/s Ethernet stream (not in current release)).

In the following is described the signal processing in the Ethernet line ––– SDH matrix (placed on the
MATRIX unit) direction. On the opposite side are performed the complementary functions.
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The functions implemented on the board are the following:

– Ethernet frames processing:

•

SELF RATE ADAPTING and interfacing with the line:

The Ethernet streams come into the unit via eleven connectors RJ45 on the front–cover, just
after there are the transformers to realize the crossover function.

The inner part of the line interface comprises the “Self Rate Adapting” block, which is able to
perform the physical processing of the 10/100 Mbit/s signals.
At the start–up, this block is automatically able to select the max. rate accepted by the remote
station; it is however possible to force all the configurations (full–duplex, half–duplex, 10Mbit/s
100Mbit/s) by means of the check signal “Rate Adapting forced settings” coming from the
Microcontroller on the board.

The “Self Rate Adapting” block requires a 125 MHz reference clock (supplied by a VCXO) in
order to be able to process the input and output signals.

The signals are sent to the “Retiming” block after having been processed.

• RETIMING:

The eleven Tx and Rx serial streams together with the clock and synchronism are retimed with
the system clock to absorb phase differences (if any) with the clock recovered from the data.

• GFP:

The function of this block is to prepare the Ethernet frames to be mapped towards the SDH world
by means of GFP encapsulation (see para. 3.8 on page 263 for details) thus guaranteeing the
possibility to utilize any type of VCx virtual container.

The “GFP” block” is connected to 8 SSRAM memory pads to create the pseudo hard disk
functionality and to 3 external memories (Management memories) where are stored all the
information required to perform the connections towards the VCx.

• MICROCONTROLLER:

The Microcontroller can set all the operation settings of the “Self Rate Adapting” block present
on the ETH–MB board and the one on the ETH–ATX access unit. Moreover the Microcontroller
can configure the “GFP” block cross–connections.

The program executed by the microcontroller to perform the various processes resides in two
SRAM memories and in one FLASH memory on the board.

• SIPO PISO:

These blocks are used to parallel the 1.25Gbit/s streams received from the access port and then
processed like the signals recovered from the 11 line interfaces on the same board. In fact, the
14 streams have been serialized by obtaining two 1.25Gbit/s links in order to connect 14
Ethernet streams on the access board via the backpanel.
The 1.25Gbit/s streams are also utilized to connect the Ethernet port (ETH–MB) with the Gigabit
Access card (GETH–AG).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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• VCXO:

On the unit is present a VCXO supplying a 125MHz clock to all the logics processing the
Ethernet signal.

– SDH termination:

• SWITCH: The task of the SWITCH block is to send the signals coming from HPT or LPT block
towards the matrix on the MATRIX board. The selection is made according to the type of signal
to be connected (L if it is structured, X if unstructured). The “L” signals are sent to LPT – LPA
blocks, the “X” to the HPT.

• HPT: this block adds/removes the high order POH bytes to the C–4 unstructured payloads
(bulks).

• LPT: The LPT function terminates a VC–12 or a VC–3 by adding or removing the relevant POH
bytes to a C–12 or a C–3.

• LPA: This block adapts the low order payloads C12 or C3 to the higher order containers used
for transportation in the SDH (TU–12 or TU–3). The adaptation includes timing synchronization
and frame offset with pointers movements.

• Struct/Unstr: this selector sends the bulk signals (unstructured) to HPT, while the structured
signals are sent to LPA–LPT.

– Other functions implemented on the board are:

• RIBUS I/F
This block is used to read/write from/to the ”RIBUS” serial stream, to control the LED on the unit,
to release the Management–bus in case of power failure, and to use the remote inventory.
RIBUS I/F is powered by the + 3.3 VS supplied by the CONGI

on page 370 for details about Remote Inventory information).

• M–BUS Driver
It drives the input–output gates of the serial Management–bus. These drivers can be disabled
(by the Bus–OFF signal) in case of power failure.


• LEDS
The board presents on its front panel one LED the meaning of which is reported in Figure 46.
on page 135.

• Buses
ISSB–EC: serial bus from the EC, to communicate software data (download, etc.).
SDH–CS: from the EC, after derivation from the serial “Management–bus”, for configuration
and status information of SDH components.
1AA 00014 0004 (9007) A4 – ALICE 04.10

RIBUS: serial bus from the SC (shelf controller on MATRIX unit), to communicate inventory and
peripheral data.

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622 MHz System clock a
System clock b
OSC

SDH–CS HPT

LPT

from/to
SDH–CS

Power Sync. LPA X
VCX0
S
W
125MHz I
Struct/unstruct T
C L
H
1
ÎÎÎ
ÎÎÎ
ÎÎÎ
ETHERNET INTERFACE 10 BASE T

2
SELF RATE System clock Management
Configuration
ÎÎÎ
ÎÎÎ ADAPTING
Memory É
É
É
É
Full–duplex GFP
Data+Ck Generic
Half–duplex
Framing
11 ÎÎÎ
ÎÎÎ
10 Mbit/s
100 Mbit/s RETIMING
Procedure

8
ÎÎÎ
(not used)
1
12 ÎÎÎ RAM

ACCESS CARD
ÎÎÎ SIPO
1,2 Gb/s DATA

from/to
ÎÎÎ Rate adapting

PISO
forced settings

SDRAM
É Configuration
ISSB–EC PQ2/EQC
from/to
MICROPROCESSOR ÀÀÀÀÀÀÀÀÀÀÀÉÀÀ
ÉÀÀ
ÀÉÉ
ÀÀÀÀÀÀÀÀÀÀÀÀ
FLASH
EPROM Management

Bus (ISPB)
M–BUS
Configuration Status Driver
for SDH (SDH–CS) CMISS
from/to

Power Sync.
Bus–OFF
Remote
Inventory
RIBUS
ID
1.8V RIBUS
FROM CONGI

I/F F +3.3 Vdc
3.3 V DC/DC Unit
CONVERTERS Failure
2.5 V
48/60 V
ETHERNET PORT

Figure 282. ETHERNET port (ETH–MB) – Block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.40 ISA –Giga Ethernet Main Board (GETH–MB)


This unit allows the management of Giga–bit Ethernet data and their transportation over the SDH network.

The connections to the Ethernet network are accomplished by means of 8 full–duplex ethernet optical
interfaces, type 1000Base–LX , 1000Base–SX, 1000Base–ZX , of which four are located on the front of
the board, and four are on the GigaEthernet Access Unit; the giga–ethernet links operate at rates up to
1.25Gb/s, with data–rate auto–negotiation option, connected by means of LC–Duplex fiber connectors.

The SDH container used for Ethernet data transportation is VC–4.
The eight Ethernet channels can be connected to 8 SDH logical ports at VC4 rate.

The main functions implemented on the board are the following:
GbEth i/f
SIPOPISOa
SIPOPISOb
ETH–GFP
TABLES MEM
GFP–SDH
ALIGNMENT BUFFER
SDH–BP
Microprocessor
RIBUS i/f Remote Inventory
DC/DC Converters.

GbEth I/F:
four of these blocks are located on the unit; it is a small–form factor pluggable (SFP) module,
implementing the optical to electric conversion, and viceversa, to accomplish a full–duplex Gigabit
Ethernet interface at 1.25 Gb/s, as specified in IEEE802.3. For its description refer to para. 4.19,
page 430 (”Gbit Eth. i/f Module” 1000B–LX, 1000B–SX, 1000B–ZX).

SIPOPISO:
two of these blocks are located on the unit: SIPOPISOa serves the four Gigabit data afferent the
optical interfaces on the present board, while SIPOPISOb serves the four Gigabit data afferent the
access board. The SIPOPISO block receives four ethernet differential signals at a rate of 1.25Gb/s
and parallels each of them on ten wires at 125Mb/s rate; viceversa, in the opposite direction, it
receives each gigabit signal on a parallel flow on 10–bits basis and serializes it. It accomplishes the
PCS and PMA functions specified by the IEEE802.3:
• receive clock recovery
• data serialization/deserialization
• encoding/decoding of octets data to/from ten–bits code–groups (8b/10b)
• managing of the auto–negotiation process.

ETH–GFP:
this is an integrated circuit that accomplishes the data passage from ethernet frames to GFP (Generic
Framing Procedure) frames and viceversa. Every function contained in it is repeated 8 times, in order
to process the 8 ethernet signals. The ethernet MAC frame structure is illustrated in Figure 120. page
238 and is detailed in rec. IEEE 802.3. The GFP frame structure is illustrated in para. 3.8, page 263,
and is detailed in rec.ITU–T G.7041.
NOTE: the functions are here described only in the direction from Ethernet to GFP, in the opposite
1AA 00014 0004 (9007) A4 – ALICE 04.10

direction they are opposite and specular.
• ETH: it provides to acknowledge the boundaries of the ethernet frames as specified in rec. IEEE
802.3. The octets relevant to ethernet Preamble and Start–Of–Frame Delimiter are discarded.

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• SIL: it provides to acknowledge the ethernet inter–frames silences and to discard them. In this
way the useful data only are transferred to the subsequent data buffer.
• BUFF: it is a buffer in which the ethernet data are written by means of a smooth ethernet clock,
as they are ready, and then are read by the GFP mapper. In case that the buffer is near to full

the mechanism of flow–control is started, in order to slow down the remote ethernet data source.

• GFP: it is the GFP mapper. The data are drawn from the buffer at 155Mb/s rate; possible gaps
between ethernet encapsulated frames are filled with Inter–Packet Gaps (IPG).

TABLES MEM:
this is a memory storing some tables of data relevant to: routing, delays of the queues and delays
of the links, destinations of the ethernet signals, etc.

GFP–SDH:
this is an integrated circuit that accomplishes the data passage from GFP frames to SDH frames and
viceversa. Every function contained in it is repeated 8 times, in order to process the 8 afferent signals.
NOTE: the functions are here described only in the direction from GFP to SDH, in the opposite
• LPA: it provides to map, directly, the GFP data into an SDH higher order unstructured C4
container.
• HPT: this block adds the higher order POH bytes to the C–4 payload (bulk); it accomplishes only
a reduced HPT, since the complete function is implemented on the SDH–BP macro–block.
• XCVC: it implements the Cross–Connection (routing) and the Virtual Concatenation of the
encapsulated ethernet signals. The Virtual Concatenation consists in the distribution of the
bytes flow of a single ethernet signal, by bytes de–interleaving, over several, concatenated VC4
signals; the virtual concatenation can be done over 2 or 4 or 7 VC4’s.
• MSA, MST, RST: they accomplish only reduced SDH functions for the STM1 signal, since they
are used here only for intra–board framing purposes;

ALIGNMENT BUFFER:
this is a buffer storing the data, needed in the case of virtual concatenation: since different VC4’s can
have different delays, they must be memorized to be aligned; the maximum tolerable delay difference
is 250msec.

SDH–BP:
this is an integrated circuit that accomplishes the data passage from STM1 frames to VC4 frames
for the BackPanel format and viceversa. Two of these macro–blocks are located on the board, in
order to process the 8 afferent signals, since each of them can process 4 stm1 signals. Every function
contained in it is repeated 4 times.
NOTE: the functions are here described only in the direction toward the back panel, in the opposite
• RST, MST, MSA: these are standard SDH functions for the STM1 signal, their function is
reduced since they are used here only for intra–board framing purposes;
• HPT: this block adds the higher order POH bytes to the C–4 payload (bulk);
• 4:11:4 : this is a parallel–to–serial converter, in direction towards the backpanel, and a
serial–to–parallel converter, in direction from the backpanel; the backpanel signal format is
STM4–like, at 622 Mb/s rate. The backpanel signal is split in two: the first (D1a and D2a) going
to the main MATRIX Unit and the second (D1b and D2b) to the spare MATRIX Unit
1AA 00014 0004 (9007) A4 – ALICE 04.10

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VCXO25MHz:
It generates a 25 Mhz frequency and, by means of a x5 multiplier, the 125 MHz ethernet transmitter
reference clock.

622MHz PLL:

It is a phase locked loop generating the 622 Mhz reference clock for timing the downstream data
toward the ethernet interfaces.

Microprocessor:
It is a microcontroller (NIOS type) controlling and supporting the Ethernet functionalities, such as:
configuration, alarms and states collections, performances monitoring, communications with the
Shelf Controller (SC, on MATRIX unit) and with the OS, etc. It communicates with the SC by means
of the configuration bus for SDH functions (SDH–CS), coming from the Management bus ISPB (intra
shelf parallel bus). It is provided with relevant devices SDRAM (for data memory) and Flash EPROM
(for program memory).

The other functions implemented on the board are:

• RIBUS I/F
This block is used to read/write from/to the ”RIBUS” serial stream (SPI: serial peripheral
inventory), to control the LED on the unit, to release the Management–bus in case of power
failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the
rear access panel.


• M–BUS Driver
It drives the input–output gates of the Management–bus (ISPB: intra–shelf parallel bus). These
drivers can be disabled (by the Bus–OFF signal) in case of power failure.

DC/DC CONVERTERS

The board presents, on its front panel, one LED, the use and meaning of the LED and of the
frontal connectors is reported in Figure 47. on page 136.

• Buses
SDH–CS: from the SC (shelf controller), after derivation from the “Management–bus” (M–bus),
for configuration and status information of SDH components.
ETH–CS: from microprocessor, for configuration and status information of the Ethernet
functions.
RIBUS: also called SPI (serial peripheral bus), from the SC (shelf controller on MATRIX unit),
to communicate inventory and peripheral data.
1AA 00014 0004 (9007) A4 – ALICE 04.10

unit), to communicate data about SDH asics and traffic configuration, SDH alarms collection,
performance monitoring, etc.

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155MHz
:4 622 MHz System clock (T0a, T0b)
PLL
622MHz 2

SDH–CS 2 D1a
SDH–CS

4:1 2 D1b

from/to
155MHz RST MST MSA HPT
2x4
1:4

LPA 2 D2a
HPT MSA MST RST SDH–BP 1
2x8
2x8 2 D2b

XC VC 2x4
@155Mb/s SDH–BP 2
GFP–SDH @622Mb/s
125MHz
ALIGNMENT PowerSync.
BUFFER

@1.25Gb/s ETH–GFP 125MHz 155MHz
SIPO 2x40@125Mb/s
GbEth I/F 2x4
2x4
PISO a ETH SIL
1 2x40@125Mb/s BUFF GFP
2x8@155Mb/s
2
3 125MHz
4

ETH–CS TABLES
125MHz 125MHz MEM

x5

GbEth Access Module
125MHz
VCX0
25MHz

from/to
SIPO 2x4 @1.25Gb/s

PISO b

Configuration for Eth.
ETH–CS

SDRAM MICROPROCESSOR
(NIOS)
FLASH
EPROM Management

Bus (ISPB)
CMISS
from/to

Bus–OFF
PowerSync. Remote
Inventory
internal voltages

1.5V RIBUS (SPI)
ID
1.8V RIBUS
I/F F +3.3 Vdc
DC/DC Unit
3.3 V
CONGI

CONVERTERS Failure
from

2.5 V 48/60 V

Gigabit Ethernet Unit

Figure 283. Gigabit Ethernet Unit – Block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.41 ISA– Ethernet switch (ES1–8FE)

The board ISA–ES1–8FE mainly works as a LAN switching, and in particular it provides the service of
connecting two LANs as a point to point connection between two routers or switches through an SDH

network.

The connections to the Ethernet network are accomplished by means of eight local 10/100 Base T
ethernet interfaces located on the front of the board, and eight ethernet over SDH interfaces through
back–panel.

The SDH container used for Ethernet data transportation are VC–4, VC–3, VC–12, VC3XV and VC12XV.


[1] Ethernet Physical interface

[2] Ethernet Switch module

[3] Ethernet Mapper (GFP/LAPS)

[4] Bus converter

[5] SDH interfacing to Back Panel (TTF and LVC)

[6] Microprocessor

[7] RIBUS interface

[8] Power supply


This block supports the eight 10/100 Mbit/s ports. The 10/100 Mbit/s Ethernet MAC block is IEEE 802.3,
802.3x and 802.3ac compliant and supports Full Duplex/Half Duplex for 10/100 Mbit/s Ethernet MAC
(MAC implements the IEEE 802.3 MAC Control layer and PAUSE operation for flow control) mode of
operation.

In addition, 3 LED interface are provided for each port to reflect current status.


In ISA ES1–8FE board, 16FE ports are used, in which 8 of them for 100BASE–T line side interface, while
other 8 for SDH mapper.

The basic functions supported are following listed:

• MAC based forwarding and autolearning
• VLAN based forwarding
• 802.1Q VLAN add/remove/swap
• Stacked VLAN (802.1Q format) add/remove/swap
• Multicast/Broadcast
• 802.3x flow control
• 802.1Q Priority bits management for queuing, WFQ scheduling
•
1AA 00014 0004 (9007) A4 – ALICE 04.10

Policing and bandwidth allocation

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[3] Ethernet Mapping over SDH (GFP/LAPS)

Ethernet packets are encapsulated and mapped into SDH frames for transmission. Ethernet mapper
supports 8 independent channels for EOS encapsulation.

Each channel can be mapped with multi SDH containers with appropriate bandwidth, such as
VC12s/VT1.5, VC3s/STS–1s, or VC4s/STS–3c.

Both high order and low order concatenation are supported, moreover, virtual concatenation with LCAS
(Link Capacity Adjustment Scheme) providesr customer with powerful dynamic bandwidth adjustment
scheme to fit various needs.

Basic feature list as follows:

• Multi encapsulation mode supported:

– GFP Generic Framing Procedure (ITU–T G.7041)

– LAPS Link Access Procedure SDH (ITU–T X.86/X.85)

– BCP PPP Bridge Control Protocol (RFC 1662/2878)

• Low order/High order Contiguous and Virtual Concatenation supported

• Container supported:

– VC12–xv (x = 1 to 63)

– VC3–xv (x = 1 to 3)

• Differential delay compensation = 48 ms

[4] Bus converter

The task of the Bus converter is to translate 19 Mb/s A/D bus to 155 Mb/s data stream.

[5] SDH interfacing with Back Panel (TTF and LVC)

The TTF block is connected to the two central boards (MATRIXN) through 1 +1 links @622 Mbit/s in LVDS.

TTF (Transport Terminal Function) block provides SDH termination for Regenerator Section and Multiplex
Section.

The LVC block is connected both to the HPC matrices and to the LPC matrices on the MATRIXN card
through couple of 1+1 links @ 622 MBit/s working in protection, LVDS format, STM–4 equivalent capacity.

LVC circuits perform the HOA function (Higher Order Assembler) and the Lower Order functions LTCM
or LTCT sink, LPOM or LSUT sink, LSUT source and LTC source up to 4 STM1 equivalent.

[6] Microprocessor

It is a microcontroller controlling and supporting the Ethernet functionalities, such as: configuration,
alarms and states collections, performances monitoring, communications with the Shelf Controller
(SC, on MATRIX unit) and with the OS, etc. It communicates with the SC by means of the
configuration bus for SDH functions (SDH–CS), coming from the Management bus ISPB (intra shelf
1AA 00014 0004 (9007) A4 – ALICE 04.10

parallel bus). It is provided with relevant devices SDRAM (for data memory) and Flash EPROM (for
program memory).

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[7] RIBUS interface

This block is used to read/write from/to the ”RIBUS” serial stream (SPI: serial peripheral inventory), to
control the LED on the unit, to release the Management–bus in case of power failure, and to use the remote

inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the rear access panel.

The following information/alarms coming from the boards are collected and sent to EQUICO:

– Card type and slot identification

– Alim alarm : it arises in case of card power failure

– ISPB control: it disables the card access to the ISPB bus in case of board power failure or incase of
generic board failure.

– LED control: it commands the on/off status of the green/red INT LED present on each card.

Moreover the component permits to read/write the remote inventory.

[8] Power supply

This block converts the 48/60 V power supply, to obtain the voltages used to supply all the components
in the board.

Ethernet card internally uses five different power voltages.

The following voltages are needed: +3.3V , +2.5V, +1.8V, +1.5V, +3.3VS.



• M–BUS Driver

DC/DC CONVERTERS

The board presents, on its front panel, nine LEDs, the use and meaning of the LED and of the
1AA 00014 0004 (9007) A4 – ALICE 04.10

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System clock a

System clock b

Link H 1+1
TTF

from/to
BUS Link X 1+1
CONVERTER
LVC Link L 1+1

1 8

1
ÎÎ
ÎÎ
From/to SDRAM

Ethernet Ethernet Switch
Ethernet
Physical
Mapper
Interface Module
(GFP, LAPS)

8
ÎÎ
ÎÎ Configuration Status

EQUICO
from/to
RESTART SNMP

MICROPROCESSOR
SDRAM
FLASH
EPROM Management
Bus (ISPB)
M–BUS
Driver
CMISS
from/to

Bus–OFF
PowerSync. Remote
Inventory
internal voltages

1.5V RIBUS (SPI)
ID
1.8V RIBUS
I/F F +3.3 Vdc
DC/DC Unit
3.3 V
CONGI

CONVERTERS Failure
from

2.5 V 48/60 V

ISA ES1–8FE unit
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 284. ISA ES1–8FE block diagram

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4.42 ISA– Ethernet switch (ES1–8FX)

The description of the board is similar to the ISA ES1–8FE (refer to paragraph 4.41 on page 535) taking
into account that ISA ES1–8FX has eight 100 Base FX Optical SFP module instead of 10/100 Base T.

4.43 ISA– Ethernet switch (ES4–8FE)

The board ISA–ES4–8FE mainly works as a LAN switching and as gateway from the Ethernet traffic
towards the SDH network.
In particular it provides the service of connecting two LANs and can be applied mainly in three scenario:

[1] Point to point application where a point to point connection is set–up between two routers or switches
through an SDH network.

[2] Ring application where local interfaces add/drop Ethernet traffic on a ring of virtual concatenated
paths in the SDH network.

[3] HUB application where several switches or routers convey traffic towards a single machine (for
example POP router)

The connections to the Ethernet network are accomplished by means of 8 local 10/100 Base T ethernet
interfaces located on the front of the board, and 16 ethernet over SDH interfaces through back–panel
which has a 622 Mbit/s equivalent throughput.
The front panel hosts also one Small Form factor Pluggable module supporting a Gigabit Ethernet
interface, the ninth local interface.

The SDH container used for Ethernet data transportation are VC–4, VC4XV (only when Gbit Ethernet
interface will be managed) VC–3, VC–12, VC3XV and VC12XV.




[3] Ethernet Mapper (GFP/LAPS)

[4] SDH interfacing to Back Panel (TTF and LVC)

[5] Local Microprocessor

[6] RIBUS interface

[7] Power supply


This block supports the eight 10/100 Mbit/s ports. The 10/100 Mbit/s Ethernet MAC block is IEEE 802.3,
802.3x and 802.3ac compliant and supports Full Duplex only for 10/100 Mbit/s Ethernet MAC (MAC
implements the IEEE 802.3 MAC Control layer and PAUSE operation for flow control) mode of operation;
autonegotiation is also supported.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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In ISA ES4–8FE board, 25 ports are used, in which 8 of them for 100BASE–T line side interface, one for
1000Base SX, LX, ZX while other 16 for SDH mapper.

The basic functions supported are following listed:

• MAC based forwarding and autolearning
• VLAN based forwarding
• 802.1Q VLAN add/remove/swap
• Stacked VLAN (802.1Q format) add/remove/swap
• Multicast/Broadcast
• 802.3x flow control
• 802.1Q Priority bits management for queuing, WFQ scheduling
• Policing and bandwidth allocation

[3] Ethernet Mapping over SDH (GFP/LAPS)

Ethernet packets are encapsulated and mapped into SDH frames for transmission. Ethernet mapper
supports 16 independent channels for EOS (Ethernet Over SDH) encapsulation.

Each channel can be mapped with multi SDH containers with appropriate bandwidth, such as VC12,
VC12XV, VC3, VC3XV, VC4 or VC4XV (with local Gb Ethernet interface)

Both high order and low order concatenation are supported, moreover, virtual concatenation with LCAS
(Link Capacity Adjustment Scheme) provides customer with powerful dynamic bandwidth adjustment
scheme to fit various needs.

Basic feature list as follows:

• Multi encapsulation mode supported:

– GFP Generic Framing Procedure (ITU–T G.7041)

– LAPS Link Access Procedure SDH (ITU–T X.86/X.85)

– BCP PPP Bridge Control Protocol (RFC 1662/2878)

• Low order/High order Contiguous and Virtual Concatenation supported

• XV Container supported:
According to the port configuration two different operation mode are available for ISA
ES–4–8FE as explained in the table below:

XV type XV container supported

SMII operating mode GMII operating mode

VC12–xv (x = 1 to 50) (x = 1 to 63)

VC3–xv (x = 1 to 2) (x = 1 to 12)

VC4–xv (x = 1 ) (x = 1 to 4 )
1AA 00014 0004 (9007) A4 – ALICE 04.10

The choice between SMII or GMII operation is made via Craft Terminal.

• Differential delay compensation = 48 ms

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[5] SDH interfacing with Back Panel (TTF and LVC)

The TTF block is connected to the two central boards (MATRIXN) through 1 +1 links @622 Mbit/s in LVDS.

TTF (Transport Terminal Function) block provides SDH termination for Regenerator Section and Multiplex

Section.

The LVC block is connected both to the HPC matrices and to the LPC matrices on the MATRIXN card
through couple of 1+1 links @ 622 MBit/s working in protection, LVDS format, STM–4 equivalent capacity.

LVC circuits perform the HOA function (Higher Order Assembler) and the Lower Order functions LTCM
or LTCT sink, LPOM or LSUT sink, LSUT source and LTC source up to 4 STM1 equivalent.

[6] Local Microprocessor

It controls and supports the Ethernet functionalities (Ethernet Physical Interface, Ethernet Switch Module
and Ethernet Mapper): configuration, alarms and states collections, performances monitoring,
communications with the OS (SNMP).
The microprocessor is provided with relevant devices SDRAM (for data memory), Flash EPROM (for
program memory) and Compact Flash.
External Shelf Controller (SC) controls SDH related circuits by ISPB bus.

[7] RIBUS interface


The following information/alarms coming from the boards are collected and sent to EQUICO:






[8] Power supply

This block converts the 48/60 V power supply, to obtain the voltages used to supply all the components
in the board.

Ethernet card internally uses five different power voltages.

The following voltages are needed: +3.3V , +2.5V, +1.8V, +1.5V, +3.3VS.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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• M–BUS Driver

DC/DC CONVERTERS

The board presents, on its front panel, one LED, the meaning of which is reported in Figure 48.
on page 137.
A push–button for the microprocessor restart is present on the front of the unit.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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System clock a


System clock b

Link H 1+1
TTF

from/to
Link X 1+1

LVC Link L 1+1
ETHERNET INTERFACE 10 /100 BASE T

4XSTM–1

From/to SDRAM
1
ÎÎÎ
ÎÎÎ 1XSMII 2xSMII
(8 Fast Ethernet) (16 FE)
Ethernet Ethernet
Ethernet
Physical Mapper
Switch
(GFP, LAPS)
Interface 2xGMII
Module
8 2XGMII (2 GB E)
ÎÎÎ
ÎÎÎ (1 Gbit Ethernet)

not used
GIGABIT ETH
Interface

1 ÎÎÎ SFP
IBM

ISPB
module
ÎÎÎ
PCI

EQUICO
from/to
SNMP
RESTART

SDRAM
MICROPROCESSOR CONTROL
BUS
BRIDGE
FLASH

EPROM

Management
CPLD Bus (ISPB)
M–BUS
COMPACT Driver
CMISS
from/to

FLASH
Bus–OFF
Remote
internal voltages

Inventory
1.5V RIBUS (SPI)
ID
1.8V RIBUS
I/F F +3.3 Vdc
DC/DC Unit
3.3 V
CONGI

CONVERTERS Failure
from

2.5 V 48/60 V

ISA ES4–8FE

Figure 285. ISA ES4–8FE block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.44 ISA ES–16


ISA ES16 unit has a throughput towards the SDH network of 2.5 Gbit/s and it hasn’t any local Ethernet

interfaces on the front pane (stand–alone operation)l. The board is able to manage local Ethernet
interfaces, but it has to be equipped together with the access card, which has to be plugged into the Access
Area.

The Access Card, which can be used in conjunction with ISA ES–16 are:

– 14x Fast Ethernet access card for providing 14 FE local interface;

– Gigabit Ethernet Access Card for providing up to four Gigabit Ethernet Local interfaces with SFP
optical plugs, which can be 1000B– SX/LX/ZX.

Note: independently of the configured Ethernet local interfaces, the maximum number of ports towards
SDH network (managed by Q3) is 64, while the number of ports of the switch can be increased up to 78
if the Fast Ethernet Access Card is applied or up to 68 if the Gigabit/s Access Card is applied.
The management and control of those local interfaces is in charge of SNMP.

The board mainly works as a LAN switching and as a gateway from the Ethernet traffic towards the SDH
network.

In particular the board can be used mainly for providing three services:

– Virtual Private Line: point to point application where a point to point is set–up between two routers
or switches through a SDH network: the ISA ES–16 can be directly connected to the customer using
the local interface of the Access Cards, or the connection to the customers can be remotized using
for istance the Fast Ethernet Boards.

– Virtual Private LAN service: multipoint to multipoint application, where each port of the customer can
be connected to every other ports of its virtual private LAN. The forwarding of the Ethernet flows is
based on proper classification process taking into account the SLA and the load of the network local
interfaces. The topology exploiting this application could be for example a ring topology where the
customer local or remote interface add/drop Ethernet traffic on a ring of (virtual) paths in the SDH
network. In this way ISA ES–16 work as switch distributed in the network.

– Broadband access service (hub application scenario) where several switches or routers convey
traffic towards a single machine (for example a POP router).

The Ethernet traffic, opportunely mapped in the SDH transport structures, is then sent towards the SDH
Matrix through the back–plane which has STM–16 equivalent throughput. This represents the maximum
throughput of the board which depends also by the subrack slot.

The Ethernet frames can be mapped in different types of SDH Virtual Containers (according the chooses
of the operator) using the Frame based GFP (Generic Frame Procedure) protocol, LAPS (Link Access
Procedure– SDH) protocol or PPP (Point to Point protocol) protocol over HDLS (High level Data Link
Control).

The board is able to forward frames on port numbering, VLAN tag, priority coding, MAC Destination
address, but also on MPLS (Multi Protocol Label Switching) label; It supports the Martini encapsulation
for transporting the VLAN tagged Ethernet frames into MPLS network.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Main functionalities:

– 4.5 Gbit/s layer 2 switching

– SDH capabilities:

• STM16 Ho/STM4 LO

• virtual concatenation: up to 64 VCG groups

• hitless LCAS (Link Capacity Adjustment Scheme)

– Protocol support:

• POS (Packet Over SDH)

• GFP

• IEEE 802.3 Ethernet (10/100 or GBE)

– Switching based on:

• Stacked VLAN

• MPLS

• MAC learning

– HW support for EPS:

– Ethernet access through FE access module or GBE acc module

ISA ES 16 is a single height module that fits in any port slot 1660SM equipment. The equivalent backplane
capacity is 1xSTM4 in normal slot or 2xSTM4 in enhanced slots

Local data access are available through access slot equipped with 14xFE access card or 4xGBE access
card.

When attached to 4xGBE access card the input traffic must be reduced in order not to overflow the fabric:
in such a case backplane traffic is not affected, while GBE traffic can be reduced by means of 802.3 flow
control protocol (pause frames).

ISA ES–16 board supports the EPS protection scheme 1+1 where the main and spare position are
assigned by management system in a flexible way (refer to paragraph 3.13.1 on page 322 for details).

Data enter ES16 embedded in SDH streams by the matrixes and as Ethernet frames from Access Cards.

Data connection with Matrixes is realized with MUX/DEMUX and G.A. block.

MUX/DEMUX is connected to main and enhanced NGI ports supporting data up to 4 equivalent STM1
in normal slot and 8xSTM1 in enhanced slot.
1AA 00014 0004 (9007) A4 – ALICE 04.10

MUX/DEMUX is configured to talk to G.A block in 16xSTM1 mode; G.A. block generates a STM16 stream
to “VCG management block” that handles up to 64 VCGs (Virtual Concatenation Group) with LCAS
protocol; also terminates layer 2.5 on each group (GFP, LAPS and POS)..

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Although “VCG management block” can transport several type of layer 2 or 3 formats, foreseeable
applications of ISA ES16 only calls for transport of Ethernet and MPLS frames.

Extracted frames are sent for further processing to “ETHERNET Mapper” block the function of which are:

– Serial link alignment

– frame delineation

– storing of frames entering from SPI3 and access card and forwarding to AD FPGA

– reassembling of ethernet frames received from AD FPGA and forwarding to Access card

– format adaptation of segments coming from AD directed to Calla48

ISA ES16 UNIT is connected to FE or GE “access card” directly by “ETHERNET Mapper” block.

“Ethernet Mapper” block interfaces to “Layer 2 processing” block through 2 monodirectional 13 LVDS links
bus at 450 Mbps.

In Rx direction full packet are transferred across the interface. Each packet is prepended with a control
word carrying indications of input port, length and other service information.

In Tx direction, segments of up to 128 bytes are transferred across the interface: “Ethernet Mapper” block
dispatches data to Ethernet reassembling circuitry or to “VCG management” block.

Ethernet packets are processed by “Layer 2 processing” block to:

– decode protocol header, up to eight nested protocols or MPLS labels can be extracted

– search flow and session to which the packet belong

– policing the streams according to session parameters

– monitor the traffic with inflow and outflow counters

– schedule forwarding of packets

– encapsulation of outgoing packets

Output port, encapsulation and assigned quality of service of outgoing packets depend on a subset of
input port, VLAN tags, MAC address and MPLS labels. “Layer 2 processing” block and the local
microprocessor cooperates in dynamically learning and obsoleting MAC addresses.

Local Microprocessor

It controls and supports the Ethernet functionalities (Ethernet Physical Interface, Ethernet Switch Module
and Ethernet Mapper): configuration, alarms and states collections, performances monitoring,
communications with the OS (SNMP).
The microprocessor is provided with relevant devices SDRAM (for data memory), Flash EPROM (for
program memory) and Compact Flash.
External Shelf Controller (SC) controls SDH related circuits by ISPB bus.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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RIBUS interface



The following information/alarms coming from the boards are collected and sent to PQ2/EQC:








• M–BUS Driver

DC/DC CONVERTERS

Starting from the 48 dc supplyed by CONGI unit with the aids of internal DC/DC converter, are
generated the following voltage:

– 3.3 Vdc
– 2.5 Vdc
– 1.8 Vdc
– 1.5 Vdc
– 1.2 Vdc

The board presents, on its front panel, one LED, the meaning of which is reported in Figure 48.
on page 137.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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ACCESS CARD
1,2 Gb/s DATA
SIPO

from/to

PISO

System clock a
G.A. System clock b
Link L 1+1
LVC

Link H 1+1
Ethernet VCG MUX/
LAYER 2

from/to
Processing Mapper TTF DEMUX Link X 1+1
management

EPS–ISSB
RESTART

EQUICO
from/to
SNMP

SDRAM
MICROPROCESSOR
Bus (ISPB)
PCI

FLASH
EPROM

COMPACT
FLASH CONTROL
BUS
BRIDGE MATRIX MAIN AND SPARE
Management
Bus (ISPB)
M–BUS
Driver
PowerSync. CMISS
from/to

Bus–OFF
1.2V
internal voltages

Remote
Inventory
1.5V RIBUS (SPI)
ID
DC/DC RIBUS
1.8V
CONVERTERS I/F F +3.3 Vdc
Unit
3.3 V
CONGI

Failure
from

2.5 V 48/60 V

ISA ES16
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 286. ISA ES16 unit block diagram

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4.45 4 X ANY HOST C card


This port realizes the mapping of up to 4 “client” signals, into an equivalent bandwidth up to 16 AU4’s; the

client allocation depends on the operative bitrate of client signal to be mapped, so as the availability of
16 AU4’s (rather than 8 AU4’s) is related to the type of slot used for the board equipment (refer to paragraph
3.10 on page 293 for details).

AU4’s carrying ’client’ signals mapped can be, then, cross–connected at HO level by MATRIX card.

’Client’ interfacing is performed through specific ’pluggable’ modules.

Serial data provided by client modules is then processed by the “primary and secondary 2xANY“ blocks
in order to realize a ’bit–per–bit’ mapping of client signals supported, that result, after each block
processing, ’virtually concatenated’ into an 8xSTM1 bandwidth.

A specific FPGA interfaces the two “primary and secondary 2xANY“ blocks performing ’client mapping’
and then provides the whole SDH chain of functions from HPT to RST; this device allows also the
optimization of client allocation into the available 8xSTM1’s, when equipped in ’H.S.’ slots (refer to
paragraph 3.10 on page 293 for details).

The data signal is, then, exchanged to MATRIX card, through the G.A. block operating as electrical
interface: equivalent STM16 is received (transmitted) from FPGA block and provided (received) to
MATRIX card with NGI framed format (X, L, H links in Figure 287. )

Note – TTF blocks supported by FPGA and G.A block are used only for interface purpose. An internal
oscillator (VCXO 622.08 Mb/s) is hosted in order to handle CRU EPS events (phisically on MATRIX unit)
with no impact on ’client’ traffic transmitted to line.

TX SIDE

– 4 X ANY module blocks: the client receiver interface regenerates the incoming client signal and
recovers the relative timing; the interface characteristics are related to client type (refer to paragraph
5.7 on page 619). Line loopback commands for each interface are received by “Alarms and Control”
block.

– Primary and Secondary 2xANY blocks: inside theese blocks the HPA function is performed; more
in details:

• client clock adaptation
• virtual concatenation
• C2 insertion

– HPT block:

HPT source is performed for all VC–4 in FPGA block; the following function are performed:

• B3: Bit interleaved parity (BIP–8) is computed over all bits of the previous VC–4 and placed in
B3 byte position.
• G1[1–4]: The number of errors indicated in RI_REI (remote error indication extracted in HPT
sk) is encoded in the REI (bits 1 to 4 of the G1 byte)
1AA 00014 0004 (9007) A4 – ALICE 04.10

• G1[5]: When there is an active RI_RDI (remote defect indication extracted in HPT sk), the RDI
indication will be sent in bit 5 of G1 byte. Upon termination of the above conditions, the RDI
indication will be removed.

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– MSA block: it performs 16 POINTER GENERATOR functions in parallel, according to ITU and ETSI,
on an AU–4 mapping basis.

– MST block: it is located in FPGA and performs Multiplex Section Termination Source:

• K2 byte is also processed for RDI insertion. RDI is inserted according to sink function
consequent actions;
• S1: Byte S1 is inserted;
• B2: The error monitoring byte B2 is allocated in the STM–16 for a multiplex section bit
error–monitoring function. This function is a bit interleaved parity (BIP–24) code using even
parity as defined in Recommendation G.707. The BIP–24 is computed over all bits (except
those in the RSOH bytes) of the previous STM–16 frame and placed in the 3x16 respective B2
byte positions of the current STM–16 frame.
• M1: The number of errors detected by monitoring B2 in the sink side is passed to the source
side via the aREI and is encoded in the MS–REI (byte M1) according to 9.2.2.12/G.707.

– RST block: FPGA block implements the RST source functions listed here below.

• B1: The error monitoring byte B1 is allocated in the STM–16 for a regenerator section bit error
monitoring function. This function is a bit interleaved parity 8 (BIP–8) code using even parity as
defined in Recommendation G.707. The BIP–8 is computed over all bits of the previous
STM–16 frame the RSn_CP after scrambling. The result is placed in byte B1 position of the
RSOH before scrambling.
• A1, A2: Frame alignment bytes A1 and A2 (3 x 16 of each) are generated and inserted in the
first row of the RSOH.
• Scrambling is performed according to Recommendation G.707, which excludes the first row of
the STM–16 RSOH (9x16 bytes, including the A1, A2, J0 and bytes reserved for national use
or future international standardization) from scrambling.

TX SIDE

– RST block: FPGA block implements the RST sink functions listed here below.

• The STM–16 frame alignment process is performed according to G.783 Recommendation.
• After the recovery of the frame phase start the received signal is descramblered using the
generator polynomial specified in G.707 Recommendation.
• B1 check is performed. Even bit parity is computed for each bit ”n” of every byte of the preceding
scrambled STM–16 frame and compared with bit ”n” of B1 recovered from the current frame
in order to detect errored blocks

– MST block: it is located in FPGA block and the function performed are listed below;

• B2: The 3 x 16 error monitoring B2 bytes are recovered from the MSOH. A BIP–24–16 code is
computed for the STM–16 frame. The computed BIP–24–16 value for the current frame is
compared with the recovered B2 bytes from the following frame and errors are reported .
B2 Errored Block events happened during the last second are reported in an “Alarms and
controls” block register.
B2 Errored Block is also used to calculate total number of errored blocks.
• M1: MS–REI information is decoded according to G.707 from byte M1 and reported as a 1
second count
MS–REI Errored Block events happened during the last second are reported in an “Alarms and
1AA 00014 0004 (9007) A4 – ALICE 04.10

controls” block register.
MS–REI indication is also used to calculate total number of remote errored block.
• K2: MS AIS detection

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– MSA block: pointer detection process.
The pointer interpreter can detect two defect conditions:

• Loss Of Pointer (LOP);

• AU–AIS.

If either of these defect conditions are detected, then a logical all–ones (AIS) signal is generated

– HPT block:

• B3: The error monitoring byte B3 is recovered. BIP–8 is computed for the VC–4 frame. The
computed BIP–8 value for the current frame is compared with the recovered B3 byte from the
following frame.
The process for detecting excessive errors and signal degrade is described in ITU–T
Reccomandation. G.806.
B3 Errored Block event happened during the last second of VC–4 #0 are reported in “Alarms
and controls” block register.
B3 Errored Block of VC–4 #0 are also used to calculate total number of errored block.
• G1[1–4]: The REI is recovered and the derived performance primitives is reported for
processing.
• G1[5]: The RDI defect is processed as described in ITU–T Reccomandation. G.806.
• C2: Unequipped defect is detected (refer to G.783)

– HPA block:

The following function are performed:

• C2 extraction: Byte C2 is recovered from VC–4 #0. If a dPLM is detected (see ITU–T G.806),
then it will be reported in an “Alarms and controls” block register.

• H4 extraction: Multiframe indicator is derived from the H4 byte. The received H4 value is
compared to the next expected value in the multiframe sequence. The H4 value is assumed to
be in phase when it is coincident with the expected value. If several H4 values are received
consecutively not as expected but correctly in sequence with a different part of the multiframe
sequence, then subsequent H4 values will be expected to follow this new alignment. If several
H4 values are received consecutively not correctly in sequence with any part of the multiframe
sequence, then a loss of multiframe (LOM) event is reported. When several H4 values have
been received consecutively correctly in sequence with part of the multiframe sequence, then
the event will be ended and subsequent H4 values will be expected to follow the new alignment.

• extraction of payload from packetsand process the heaer content

• automatic client based band and latency preset

• client clock adaptation
1AA 00014 0004 (9007) A4 – ALICE 04.10

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• RIBUS I/F
This block is used to read/write from/to the ”RIBUS” serial stream (SPI: serial peripheral

inventory), to control the LED on the unit, to release the Management–bus in case of power

failure, and to use the remote inventory. RIBUS I/F is powered by the + 3.3 VS supplied by the
rear access panel.


• M–BUS Driver

DC/DC CONVERTERS

The board presents, on its front panel, one LED, the use and meaning of the LED and of the

• Alarms and Controls
This block collect the alarm detected on the board and also sends conabds like loopacks.

• Buses
RIBUS: also called SPI (serial peripheral bus), from the SC (shelf controller on MATRIX unit),
to communicate inventory and peripheral data.
unit), to communicate data about SDH asics and traffic configuration, SDH alarms collection,
performance monitoring, etc.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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VCXO
4xANY module Primary 2XANY 622.08
Client #1
#1

#1 HPA
Vitual FPGA G.A.
Concatenation X
4xANY module
Client #3
#3 FRAMER

#3
Ï
Ï HPT MSA MST/RST
(*)
TTF
(*)
L

4xANY module
Ï
Ï H
Client Secondary 2xANY
#2 #2
System clock a

#2 HPA
Vitual
ÏÏ
Ï System clock b
Concatenation Ï
ÏÏ

from/to
Client
#4
ÏÏ
Ï Ï
Ï
Ï
#4
Ï
ÏÏ Internal STM–16
Frame
Ï CMISS

Configuration Status Management
Bus (ISPB)

CDR
ÏÏÏÏ
ÏÏÏ
ÏÏ Ï
Ï Ï
M–BUS
Driver
CLIENT
PHYSICAL Bus–OFF
INTERFACE Remote RIBUS
Inventory
4xANY module #4 ID
details RIBUS
I/F F +3.3 Vdc
Unit
Failure

#1
ALARMS
#2

#3 CONGI
from

#4 CONTROLS

1.8V

3.3 V DC/DC
CONVERTERS
2.5 V
1.5 V

(*)– TTF blocks are used only for interface purpose
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 287. 4 x ANY HOST C card block diagram

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4.46 COADM1


The COADM1 board is two slots wide and can be plugged in every slot of the Access Area without

constraint.

COADM 1 channel unit realizes wavelengths multi–demultiplexing allowing to add/drop 1 ch out of the 8
supported according to CWDM grid and the pass–through of remaining WDM channels not terminated.

One specific item per ITU–T channel is foreseen:

– 1470 nm.
– 1490 nm.
– 1510 nm.
– 1530 nm.
– 1550 nm.
– 1570 nm.
– 1590 nm.
– 1610 nm.

The functionality of the board has to be considered for ring application, and performing ’one side’ channel
termination: thus, two separate boards are required at a node of the ring in order to achieve the complete
OADM functionality.

Actual OADM functionality is based on specific devices performing mux/demux functionality as regards
the channel to be locally terminated (by specific add/drop port) and supporting both bidirectional WDM
ports for ’network connection’ and bidirectional WDM ports for ’pass–through’ connection (to/from
opposite OADM board).

’Loss of Signal’ detection on CWDM optical signal received is is not managed.

The wavelength, which is added/dropped in COADM1, is specified in one of the additional fields of the
board Remote Inventory.

The configuration of the COADM1 requires the operator to specify the added/dropped wavelength.

The operator has to connect the bundle of pass–through channels between two COADM1 boards
(respectively on west and east side of the NE).

Note – The bundle of a COADM1 cannot be connected to the bundle of another COADM1 with different
added/dropped wavelength.

Remote inventory is handled by a dedicated EEPROM carrying the inventory code associated to the
optical device; the communication towards Shelf Controller is performed by ’RIBUS block” through ’SPI’
bus.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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To/From
colored port
or
transponder CWDM
λx 1xx0
output signal
CWDM
λgrid – λx

OADM
λx 1xx0 CWDM
input signal
CWDM
λgrid – λx

LOS
DETECTION
LOS HANDLING
To/From
OADM
opposite
side

Remote Inventory

EEPROM RIBUS
COADM1 unit

SPI bus

TO / FROM Shelf Controller
on MATRIX board
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 288. COADM1 unit block diagram

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4.47 COADM2


The COADM2 board is two slots wide and can be plugged in every slot of the Access Area without

constraint.

OADM 2ch board realizes wavelengths multi–demultiplexing allowing to add/drop 2 ch out of the 8
supported according to CWDM grid and the pass–through of remaining WDM channels not terminated.

Four specific items are foreseen, considering to support the termination of two adjacent wavelengths per
item:

– 1470 – 1490 nm;

– 1510 – 1530 nm;

– 1550 – 1570 nm;

– 1590 – 1610 nm.

The functionality of the board has to be considered for ring application, and performing ’one side’ channel
termination: thus, two separate boards are required at a node of the ring in order to achieve the complete
OADM functionality.

Actual OADM functionality is based on specific devices performing mux/demux functionality as regards
the two channels to be locally terminated (by specific add/drop port) and supporting both bidirectional
WDM ports for ’network connection’ and bidirectional WDM ports for ’pass–through’ connection (to/from
opposite OADM board).


The two wavelengths, which are added/dropped in COADM2, are specified by the content of the additional
fields of the board Remote Inventory.

The configuration of the COADM2 requires the operator to specify the added/dropped wavelengths.

The operator has to connect the bundle of pass–through channels between two COADM2 boards
(respectively on west and east side of the NE).

Note 1 – The bundle of a COADM2 cannot be connected to the bundle of a COADM1.

Note 2 – The bundle of a COADM2 cannot be connected to the bundle of another COADM2 with different
added/dropped wavelengths.

optical device; the communication towards Shelf Controller is performed by ’RIBUS block through ’SPI’
bus.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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To/From
colored port
or
transponder CWDM
λx 1xx0
output signal
CWDM λy 1xx0


OADM
λx 1xx0 CWDM
input signal
CWDM λy 1xx0

LOS
DETECTION
LOS HANDLING
To/From
OADM
opposite
side

Remote Inventory

EEPROM RIBUS
COADM2 unit

SPI bus

on MATRIX board

Figure 289. COADM2 block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.48 COMDX8


MUX/DEMUX 8ch board realizes wavelengths multi–demultiplexing on the whole group of 8 CWDM

channels supported. One item is, then, foreseen.

The functionality of the board can be considered both for linear and ring application; contrary to OADM
board, no ’pass–through’ link is provided, then pass–through of wavelengths not terminated must be
realized on each single wavelength.

In ’ring’ application, the board performs ’one side’ channels termination: thus, two separate boards are
required at a node of the ring in order to achieve the complete OADM functionality.


The COMDX8 board is two slots wide and can be plugged in every slot of the Access Area without
constraint.

Specific devices performs mux/demux functionality as regards the whole group of 8 channels to be locally
terminated (by specific add/drop port).

Bidirectional WDM ports for ’network connection’ are also supported.

optical device; the communication towards Shelf Controller is performed by ’RIBUS block“ through ’SPI’
bus.

The functionality of ’Loss of signal’ received on CWDM input of ’passive’ boards is handled as showed
in the following Figure 290.

An optical splitter is used in order to provide a low percentage of CWDM power level received to a
detection stage including a large bandwidth photodetector and the specific HW for the generation of a LOS
primitive.

LOS alarm is reported through ’RIBUS block’ towards Shelf Controller on MATRIX unit.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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λ1 1470
λ2 1490 CWDM
λ3 1510
OUTPUT CHANNELS 1530
(from colored port or
λ4 MUX
1550
Transponder interface)
λ5 1570
λ6 1610
λ7 1590
λ8
λ1 1470
λ2 1490
λ3 1510
LOS HANDLING CWDM
INPUT CHANNELS
λ4 1530
Optical Splitter
input signal
(to colored port or DEMUX
λ5 1550
Transponder interface)
λ6 1570

λ7 1610
1590
λ8 LOS
x% of
DETECTION CWDM Rx
signal
LOS alarm

MUX/DEMUX8 unit Remote Inventory

EEPROM RIBUS

SPI bus

on MATRIX board
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 290. MUX/DEMUX8 (COMDX8) block diagram and LOS detection in ’passive’ boards

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4.49 2xCH Transponder SFP without optics (COWLA2)


This board realizes the function of double multi–rate transponder–regenerator in CWDM network.

Double because it has two channels, multi–rate because it can handle various kinds of standard signals,
transponder–regenerator because it can work both as transponder and as regenerator.

Each channel of COWLA2 is constituted of two bi–directional optical interfaces on which is realized ’3R’
functionality (Re–amplification, Reshaping and Retiming). When working as transponder the optical
interfaces of the COWLA2 channel are one ’BW’ and one colored, so wavelength assignment is
performed. On the contrary if both optical interfaces of the channel are colored, COWLA2 works as
regenerator. Double ’BW’ optical interface configuration, regenerator ’BW’, isn’t foreseen because not
applicable in the 1660SM (with CWDM unit) network scenarios.

Colored interfaces, ’server or WDM domain’, are input–output of others equipment resident boards; these
perform Coarse Wavelength Division Multiplexing using optical multiplexer–demultiplexer or Optical
Add–Drop Multiplexer passive components. ’BW’ lines, ’client domain’, are typically connected toward
remote generic ’BW’ clients.

COWLA2 unit supports the following signal types:

– FDDI (125 Mb/s); not operative in current release
– Fast Ethernet (125 Mb/s); not operative in current release
– Escon (200 Mb/s); not operative in current release
– Digital Video (270 Mb/s); not operative in current release
– Fiber Channel (1.0625 Gb/s); not operative in current release
– FICON (1.0625 Gb/s); not operative in current release
– Gb Ethernet (1.25 Gb/s); not operative in current release
– 2 Fiber Channel (2.125 Gb/s); not operative in current release
– STM16/OC48;
– 2 Gb Ethernet (2.5 Gb/s); not operative in current release
– STM16 w/ FEC (2.667 Gb/s). not operative in current release

In case of SDH services the board performs the management of Regeneration Section overhead on Rx
direction. For all others standard signals only ’3R’ functionality is foreseen without protocol specific
handling.

For all protocols optical LOS and URU alarms are generated.

In case of optical LOS on Rx interface, Automatic Laser Shut down procedure is activated in the
correspondent Tx side; at the same time laser shutdown or generic AIS insertion is done in the transponder
channel Tx direction.

When non–SDH services are configured, COWLA2 performs only ’3R’ functionality; signal is transparently
regenerated without protocol specific management.

In case of SDH services, besides ’3R’ regeneration, the following functionalities are realized on received
side:
1AA 00014 0004 (9007) A4 – ALICE 04.10

– alignment on received A1, A2 byte and generation of relative LOF alarm

– received section trace identifier byte J0 extraction and generation of relative TIM alarm. J0
management is configurable as one repeated byte or as 16 byte modality (15 byte + CRC–7)

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– received error monitoring byte B1 extraction and manipulation (RS non intrusive monitoring).
Performance monitoring computation is done in order to produce DEG and LOWBER alarms.
Primitive parameters are passed to Shelf Controller that computes PM handling.

– RS–AIS (MS–AIS with J0 bit at all ’1’, Alcatel proprietary alarm) detection on the incoming signal and

generation of relative RS–AIS alarm.

2xCh transponder SFP is a one slot wide plug–in unit constituted by a front panel and a Printed circuit
Board Assembly (PBA).

On the front panel are available four connectors for optical lines access and a multi–color LED used as
visual indicator for card failure alarm and in–service/standby card operating status.

Block diagram of COWLA2 unit is reported in Figure 291.

Power supplies for all board components are produced from battery interface through DC/DC converts
modules.

Optical received signal O Rxm (1 = m = 4) is converted into electrical format, D Rxm, from SFPm
photo–detector receiver. This block accomplishes re–amplification and reshaping.

Electrical received signal, D Rxm, enters into any–rate deserializer Dxm that realizes signal retiming and
1 to 16 de–serialization.

Received de–serialized signals, Dpn Rxm (1 = n = 16, 1 = m = 4) and clock, Ckp Rxm, go into FPGA.

FPGA component, basing on configuration provisioning, cross–connect a 16 bit parallel data input, Dpn
Rxm, with a 16 bit parallel data output, Dpn Txm. In case of SDH service it’s done received regenerator
section overhead bytes management.

Parallel signals, Dpn Txm, and clock, Ckp Txm, are sent to the any–rate serializer Mxm that carries out
16 to 1 data multiplexing.

Multiplexed signal, D Txm, enters into SFPm laser transmitter that produces the optical output signal O
Txm.

The bi–directional optical to optical path described above constitutes one transponder channel.

FPGA registers are configured from Shelf Controller using ISPB bus.

FPGA manages programming and alarms of SFPs and any–rate serializers–deserializers through
dedicated serial I2C bus interfaces and parallel input–output.

PLLs VCXO loop filter blocks are a constituent part of deserializers’s Clock and Data Recovery circuits
and of serializers’s Clock Multiplier Unit. They provide appropriate clock reference for
serializer–deserializer components.

Configuration device (Config Device) contains the program image that is downloaded into FPGA after
power–on.

Board remote inventory information are contained in RI EEPROM, a serial non–volatile memory
accessible via SPI bus.

RIBUS block basically it reads or writes general input–output for commands activation or alarms
1AA 00014 0004 (9007) A4 – ALICE 04.10

acquisition and pilots on–board SPI slave bus. RIBUS is controlled from SC through SPI back–plane bus.

In the following various COWLA2 blocks will be described.

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SFP OPTICAL MODULE

SFP optical module is a pluggable fiber optic transceiver that arises from a Multi–Source Agreement.

Optical wavelength could be BW or colored conform to CWDM grid. Line bit–rate could be single speed

or multi–rate.

On COWLA2 it’s for now foreseen the use of mono–mode, multi–rate BW or multi–rate 8 wavelength
colored SFP, capable of maximum span budget of about 80 Km.

Photo detector transceiver and laser transmitter achieve respectively optical to electrical and electrical to
optical conversion;

In addition there are some configuration and alarm pins:

– Tx fault indicates a laser fault

– LOS specifies an optical loss of signal

– Presence reflects the insertion–extraction of the module

– Tx disable when set shuts down the laser

– Rate select is an optional command for data rate select for multi–rate transceiver.

These signals are input–output of FPGA and can be read–written using dedicated registers. Tx disable
and LOS are used by FPGA for ALS functionality.

Tx disable, LOS and Presence are also connected to RIBUS block for testing or future utilization.

SFP module includes a 512 bytes serial EEPROM, that contains inventory and vendor specific
information. This EEPROM can be read and written via ISPB bus.

SERIALIZER/DESERIALIZER

“Deserializer” main functions are clock recovery, data re–sampling and 1 to 16 de–serialization over a
continuous bit–rate from 30 Mb/s up to 3.2 Gb/s.

“Serializer” main functions are data re–timing and 16 to 1 serialization over a continuous bit–rate from 30
Mb/s up to 3.2 Gb/s.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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FPGA


– flexible any rate data channel cross connection

– E–SNCP/I (for all services) E–SNCP/N (for SDH services) protection schemes toward client or server
domain

– Automatic Laser Shut down procedure implementation

– STMn Regenerator Section bytes termination for SDH services

– laser shut down or generic AIS insertion on Tx transponder channel direction when a LOS is detected
on Rx side

– SFP and serializer/deserializer management by ISPB.

DC/DC CONVERTERS

Power supply block produces the required on board supplies starting from 48 V ± 20 % battery input . All
components work with 3.3 V voltage except FPGA that requires also 1.5 V.

ISPB BUS

By mean of ISPB the Shelf Controller (SC) can load proper configuration setting within FPGA internal
register, monitor the current status and alarms, collect data for performance monitoring and so on.

RIBUS block


REMOTE INVENTORY

It is the memory containing the board information, for identification purposes (see para. 3.17 on page 370
for details).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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O Rx 1 D Rx 1

FPGA
O Tx 1
SFP #1 SERIALIZER
MODULE D Tx 1
DESERIALIZER

#1

CROSS–CONNECTION MATRIX
O Rx 2 D Rx 2
O Tx 2 SFP #2 D Tx 2 SERIALIZER
MODULE
DESERIALIZER

#2

STMn RS Sink
O Rx 3 D Rx 3

GENERIC AIS
O Tx 3 SFP #3 SERIALIZER
MODULE D Tx 3
DESERIALIZER

#3
O Rx 4 D Rx 4
O Tx 4 SFP #4 D Tx 4
SERIALIZER
MODULE
DESERIALIZER

#4
#1
ALARMS
#2

#3
#4 CONTROLS

ÏÏÏ
Ï Configuration Status

Management
Ï M–BUS
Bus (ISPB)
ÏÏ
ÏÏ
Ï Driver

Bus–OFF
RIBUS(SPI)

ID
RIBUS
I/F F +3.3 Vdc
Unit
Failure

Remote CMISS
internal voltages

Inventory
1.5V

DC/DC
3.3 V
CONGI

CONVERTERS
from

2XCH TRANSPONDER SFP W/O OPTICS
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 291. 2xCH Transponder SFP Without optics COWLA2

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4.50 PQ2/EQC card


The PQ2/EQC unit through the Equipment Controller (EC) manage:

• local dialog with a personal computer (F interface RS 232)

• local dialog with a personal computer (USB interface; not operative in current release)

• dialog with the Operation System for Network Management operation through Q3 and DCC
interface

• dialog with a remote Operation System for Network Management operation through interface
QAUX .

• dialog with the external equipment for Network Management operations through Interface Q2
(Mediation Device Function)

• remote alarms (RE) , alarms criteria towards the rack lamps (RA), housekeeping alarms (HK)
and front cover led

• ISSB bus

The EC performs as well all the SW functions related to the control and management activities like
info–model processing, event reporting and logging, equipment data base management, SW
downloading and management, etc.
To support its activities the EC function requires a non volatile mass storage device (FLASH CARD), boot
memory (FEPROM) and RAM memory.

F interface:

It is used for connection to a local Craft Terminal; The standard implementation of the physical layer for
the F interface consists of an RS–232 UART port accessible from the PQ2/EQC card front panel

USB interface

The USB interface is foreseen as an alternative option for connection to external PC supporting the Craft
Terminal function; it is currently not operative.

Q3 interface:

It is dedicated to an OS station connection through Local Access Network (LAN); QB3 requires a 10BASE2
or a 10BASET interface that is physical provided by CONGI card

DCC interface:

It is a TMN related communication interface based on the use of the Embedded Communication Channels
available in the SOH portion of the SDH frame. Through the QECC interface the 1660SM can exchange
management messages with a remote OS.
In the 1660SM up to three full duplex ECC channels can be terminated from each SDH interface: one
DCC_M at 576 kbit/s, one DCC_R at 192 Kbit/s and one DCC_P 64 Kbit/s (F2, F3 bytes of VC4 ).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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QAUX interface:

It is provided as an additional TMN communication interface for message exchange between the NE and
a Remote OS station based on the use of a 2 Mbit/s proprietary protocol. It can be physically terminated

on a 2 Mbit/s auxiliary channel on the SERVICE card.

Q2 interface:

A mediation function interface is provided to connect the 1660SM to non–SDH network element
The RS–485 interface and the cable connector are provided on the CONGI card.

RE, RA, HK and leds interface:

RE consists of parallel I/O signals used for remote alarms that can be accessed on the CONGI card
RA is dedicated to send commands toward the rack to light up the relevant lamps.; the physical interface
is available on the CONGI card.
By pressing a push button is possible to store an alarm;
HK consist of parallel I/O signals used to handle housekeeping signals (for example alarms received from
Fans Subrack, open door etc.); In this way they can be supervised by Craft Terminal. The physical
interface is available on the CONGI card.
The Equipment Controller also drive the leds present on the front cover to display alarms or status
indication concerning the equipment ; for the meaning of the leds see para 2.4 on page 123.
By pressing a push button present on the PQ2/EQC front cover is possible to check the efficiency of the
leds.

ISSB bus:

It is an high performance bus supporting communication among the EC function, the SC function on the
MATRIX and Local Microprocessor present on the ATM board.


• RESET PUSH–BUTTON used for EC reset.

• RIBUS I/F
This block control the LED on the unit and is also used by the Shelf Controller on the MATRIX
to read the remote inventory data though the ”RIBUS” .


DC/DC CONVERTERS
This block converts the 48/60 V power supply to secondary voltages necessary for the circuits
on the board:
+3.3 V and + 2.5 V used to supply all the components in the board.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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To/From
F
Craft
INTERFACE
Terminal

NOT DCC DCC
USB To/from
OPERATIVE MANAGEMENT STM–N port
INTERFACE

Q2
To/from
Q3
CONGI
EC QAUX
Reset To/from
SERVICE
ISSB
To/from
MATRIXE main
and spare,
ATM board

Lamp test
Remote alarms
RE
REMOTE ALARMS
Rack alarms To/from
RACK LAMPS
FEPROM RA CONGI
HOUSEKEEPING Housekeeping
Alarm storing LEDS
HK
RAM MANAGEMENT

FLASH
CARD front cover leds
Remote
Inventory From/to
RIBUS
MATRIXE
RIBUS ID main and spare
I/F
+3.3 Vdc
Unit
Failure
from
3.3 V CONGI A B
DC/DC 48/60 V
EQUICO 2.5 V
CONVERTERS

Figure 292. 1660SM PQ2/EQC Card Block Diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.51 MATRIXE card


The MATRIXE card used in the 1660 SM equipment performs different functions :

• connections between ports (ATM matrix included)

• equipment synchronization functions

• Shelf Controller functions

• performance monitoring collection

• power supply

• remote inventory

As the MATRIXE is in 1+1 redundant configuration, all the functions realized by the unit are redundant as
well.

CONNECTIONS

The connections between MATRIXE and ports are realized by means of links at 2.5 Gbit/s (link X, link
L and link H in Figure 293. on page 571)

On the MATRIXE are implemented the following SDH functions to realize the connections :

• MSP (Multiplex Section Protection)
It performs the Multiplex Section Protection (linear and MS–PRING) according to the MSP algorithm
result.
Refer to para 3.13.2 on page 335 for details on MSP linear protection.

• AU4 squelching
It is used to avoid mis–connections when the MS–SPRING protection is active. For each incoming
and outgoing AU4 , should be possible to insert AIS.

• SNCP (Sub–Network Connection Protection)
It performs the Sub–Network Connection Protections, in case of SNCP–ring network configuration,
switching from A to B path signals (A and B are two generic transmission side).
SNCP is of types HO–SNCP (for VC4 path signals) and LO–SNCP (for VC3 ,VC12, etc. path
signals).
It can be SNCP/I and SNCP/N (not operative in current release);
Refer to para 3.13.4 on page 339 for details on SNCP protection

• HPC (High order Path Connection)
This block acts as connection matrix, supporting cross–connection for a max of 384x384 STM1
equivalent signals at VC–4 level.

• LPC (Low order Path Connection)
This block acts as connection matrix, supporting cross–connection for a max of 256x256 STM1
equivalent signals at VC–12 level.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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EQUIPMENT SYNCHRONIZATION

The equipment synchronization is realized by the SETS function (Synchronous Equipment Timing
Source) that distributes to each equipment port the pertaining synchronization signals.

A high stability oscillator at 10MHz is present to guarantee an holdover or free running working mode
compliant to the ITU–T Recs.

The clock reference working modes can be: locked, hold over and free running.

When working in locked mode , the SETS block can select its reference signal among (the selection is
accomplished by means of the software and craft terminal):

• timing reference signals coming from the SDH ports (T1 )
• 2 MHz signal coming from the PDH ports (T2 )
• 2 MHz clocks (T3) or 2 Mbit/s signals (T6) coming from the SERVICE card
The T3/T6 clocks are two (i.e. T3a, T3b or T6a, T6b).

The SETG block (Synchronous Equipment Timing Generation) generates :

• a system clock T0 (at 622.08 MHz) locked to the selected reference (T1, T2, T3/T6) and
distributed to the equipment.
• CK38Mhz : it is derived from the system clock (T0) and is distributed to all the ports. Its
frequency is 38.88 MHz.
• MFSY : it is the multiframe synchronism at 500 Hz, obtained from the ck38MHz. It is distributed
to all the ports.
• a 2 MHz clock T4 or a 2 Mbit/s signal T5 used as synchronization clock towards the external,
accessible from the SERVICE board.
The T4/T5 clocks are two (T4a, T4b and T5a, T5b).

For a detailed description of the synchronization subsystem refer to para 3.14 at page 363.

SHELF CONTROLLER FUNCTIONS

The MATRIXE houses the circuitry necessary to realize the Shelf Controller.

The SC provide the resources to support the SW functions related to the control and management
operation of the boards. To perform its functions, the SC directly interfaces the ASICS on the board
implementing the SDH functions for data collection (faults or alarm event detections, performance
monitoring data) and configuration provisioning.
As the SC is involved in critical activities ( for instance EPS ) , is 1+1 protected.

The internal interfaces supporting SC element for communication tasks are:

– Management –Bus. It is a parallel bus connecting the SC processor to all the transport Asics located
on the traffic cards to provide communications among the units and the Controller, for management
of the units (management of payload processing functions).

– ISSB : Intra Shelf Serial Bus is a serial bus for communication among SC, EC (on the PQ2/EQC
card) and , if present, other processor in the Shelf.

– RIBUS . It is a serial bus connecting the SC processor to the serially interfaced devices called
RIBUS–I/F, located on each board for simple read or write operations, for communications about
Remote Inventory, cards failure, bus releasing.
1AA 00014 0004 (9007) A4 – ALICE 04.10

A push–button is present to reset the SC.

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For a detailed description of the Controller refer to para 3.12 on page 315, where the control subsystem
is described.

PERFORMANCE MONITORING COLLECTION

The “Performance Monitoring Management” block housed on the MATRIXE card realizes Performance
Monitoring functionalities; it collects and stores the data ( Defect seconds and Errored blocks) coming from
all the flows.

The Performance monitoring can be made at :

• Adaptation and Regeneration section
• Multiplex section
• Multiplex section adaptation
• HSUT and LSUT
• HPOM and LPOM
• HPT and LPT

POWER SUPPLY

The unit receives via backpanel connectors the –48V coming from CONGI boards.

The DC/DC converter present on the board generates the following voltage:

• + 3.3 V
• + 2.5 V
• +1.8 V
• +1.6 V

The Remote–Inventory and RIBUS–I/F blocks are powered by the 3.3 V power service coming from the
CONGI boards .

REMOTE INVENTORY

It is the memory used to maintain the board history and data.

For more details about the Remote Inventory function refer to para 3.17 on page 370.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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PERFORMANCE
MONITORING
MANAGEMENT

MATRIX
LPC Link L
MSP

SNCP from/to all
AU4 Link H port cards
Squelcing HPC
Link X

T2
Timing T1 (port) from ports
Synchronization
T0 (SETS) T3a/T6a
10MHz T3b/T6b
OSC SETG
to/from
Reset T4a/T5a SERVICE
T4b/T5b

MFSY
T0 CK38 to ports
T0

SC Management bus Management bus
M–BUS
Driver
FLASH Bus From/to
OFF
EPROM spare MATRIXE
(1 Mb)
Remote +3.3 Vdc and ports
Inventory
RIBUS RIBUS
I/F
Unit
Failure ID
RIBUS
ISSB From/to
spare MATRIXE
and PQ2/EQC

3.3 V
48/60 V
2.5 V DC/DC
from CONGI A B
1.8 V CONVERTERS +3.3 Vdc
MATRIX 1.6 V
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 293. MATRIXE card block diagram

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4.52 CONGI card


The 1660SM equipment can house two CONGI cards, referred as CONGI A main (slot 10) and CONGI

B (slot 12).
They are not intended as main and spare : each card provides a set of functions . Both units are necessary
to provide the complete set.

CONGI A can be used as stand alone but in this case only a subset of interfaces can be used .

Table 55. reports the interfaces present on each CONGI card.

Table 55. CONGI A and CONGI B interfaces

CONGI A (slot 10) CONGI B (slot 12)

POWER POWER

Housekeeping Remote Alarms (a subset) Housekeeping Remote Alarms ( a subset)

Rack lamps (R/M) Not used

QMD (Q2) Not used

Q3 10 base 2 Not used

Q3 10 base T Not used

INT led INT led

The main functions performed by the unit are:

[1] Input power stage

[2] AND/OR and Remote Alarms

[3] Housekeeping interface (only on CONGI in slot 10)

[4] R/M interface (only on CONGI in slot 10)

[5] QMD interface (only on CONGI in slot 10)

[6] RIMMEL interface

[7] Q3/QB3 interface (only on CONGI in slot 10)

[8] Remote inventory
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[1] Input power stage

This circuit decouples the power station battery .
It contains the ”Main Power block” with two fuses, EMI input filters, a ”protection circuit block” , a ”step

up converter” to provide –9 V and a DC/DC converter to provide the +3.3 V to the RIBUS I/F block ( see

para. 3.17 on page 370 for details ). In case of fuse broken an alarm is generated (FUSE)2.

A solder strap is present to provide the main power (48V) in modality “two wires” (if +Vbatt is connected
to ground or “three wire” (if + Vbatt is not connected to ground) in order to obtain a DC/I decoupling system.

[2] AND/OR and Remote Alarms

The circuit generates the remote alarms and lights up the the Rack lamps in case of station battery fault.

It is powered from the 3.3Vdc power from the service battery and uses it to control the station battery. In
case of loss of 3.3 Vdc a PWANDOR alarm is generated.

The AND/OR circuit monitors the station battery and provides an alarm (BAT FAIL) in case the voltage
level decreases more than 20 % of the nominal value. If BAT FAIL alarm of the CONGI in slot 10 or the
same alarm of the CONGI in slot 12 are present , the ORALIM alarm is generated and set to the PQ2/EQC
card.

Table 56. on page 573 and Table 57. on page 574 report a brief description of the alarms provided by
the AND/OR block respectively on CONGI in slot 10 and CONGI in slot 12 . They are all Electronic Ground
contacts (GND = alarm, OPEN = no alarm) sent towards the housekeeping and remote alarms connector.

Table 56. Remote alarm provided by the AND/OR block available on CONGI in slot 10

ACRONYM DESCRIPTION
T*TOR Fault or loss of one station battery .
It concurs to generate NURG, T*NURG and RNURG (it can be stored)
T*AND Fault or loss of both batteries stations. It concurs to generate T*URG and RURG (it
can be stored).
T*INT It indicates an internal alarm. It is received from PQ2/EQC
T*URG It indicates an urgent alarm. It is provided from PQ2/EQC
T*NURG It indicates a not urgent alarm. It is received from PQ2/EQC

N.B. On the Craft Terminal (C.T.) and on the Operation System (O.S). application the T*URG, and
T* NURG remote alarm are named in a different way; the relation between this two terminology
is explained in Table 77. on page 650.
1AA 00014 0004 (9007) A4 – ALICE 04.10

2. For the right management of the FUSE alarm refer to MAINTENANCE section of the METRO
OMSN C.T Operator’s Handbook. As a matter of fact some setting must be checked when two CONGI
with different Factory code / ANV suffix are equipped in the subrack.

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Table 57. Remote alarm provided by the AND/OR block available on CONGI in slot 12

ACRONYM DESCRIPTION
T*TORC It indicates a loss of +3.3V generated by the on board DC/DC converter of one

CONGI card.

T*IND Indeterminate alarm synthesis. Indicate synthesis of alarms not associated to other
severity (not used)
T*TUP It indicates an PQ2/EQC microprocessor fault (it can be stored)
T*TANC It indicates loss of + 3.3 V generated by the on board DC/DC converters of both
CONGI cards (it can be stored).
LOSQ2 It indicates loss of communication with the Operation System (not used)

[3] Housekeeping interface

Two Housekeeping operating mode are supported for CONGI unit:

– CONGI unit preset 2 wire provide 6 inputs and 2 outputs contacts suitable for customer purpose.

– CONGI unit preset 3 wire provide 4 inputs and 2 outputs contacts suitable for customer purpose.

[4] R/M interface
It is used to connect the rack lamps and incoming call signal.
Table 58. Rack lamps signals

ACRONYM FUNCTION
T*RATTD alarms storing
T*RURG urgent alarm
T*RNURG not urgent alarm
T*CH incoming call
T*TOR absence of one battery
N.B. On the Craft Terminal (C.T.) and on the Operation System (O.S). application the T*RURG, and
T* RNURG remote alarm sent toward the rack lamp are named in a different way; the relation
between this two terminology is explained in Table 77. on page 650.

[5] QMD interface
It is a RS–485 interface that allows the dialogue between the NE (EC function) and a non SDH equipment.
In this case the NE acts as a mediation device.

[6] RIMMEL interface

This block provide a serial communication interface with the FANS Shelf in order to receive information
like presence of fans unit, fan alarms, fans unit remote inventory etc. (for details about connection with
FANS Shelf refer to Installation Handbook).
“Rimmel block” is also connected with the Shelf Controller (housed on the MATRIXE) and Equipment
Controller (housed on the PQ2/EQC) in order to:

– manage the HOUSEKEEPING contact

– provisioning remote alarm
1AA 00014 0004 (9007) A4 – ALICE 04.10

– read the 2/3 wire operating mode

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[7] Q3/QB3 interface
The Q3/QB3 interface on CONGI is used for OS connection. Two connectors are available :

– 2 BNC for 10 Base 2 connection type

– RJ45 for 10 base T connection type.

The Coaxial Transceiver Interface (CTI) circuit performs the driver/receiver interface between the Q3/QB3
coaxial cable ( BNC) and the universal ethernet adapter (AUI).
The purpose of the AUI adapter is to adapt the signal, coming from the Equipment Controller on the
PQ2/EQC, to the LAN interface. It is directly connected to the RJ45 connector or through CTI to BNC
connector.

[8] Remote inventory
It is the memory used to maintain the board history and communication and routing data relevant to the
NE ;Remote Inventory activity is managed by the RIBUS I/F block as described on para. 3.17 on page
370.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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2/3 wire mode Input Power Stage

+ Batt_A Fuse MAIN – Batt

EMI

Station POWER TO ALL
+Batt
battery – Batt_A Fuse BLOCK FILTER BOARDS
STEP UP
–9V CONVERTER

PROTECTION +3.3Vdc
DC/DC TO ALL
CICUIT 3.3 V
BLOCK BOARDS
to
RIBUS I/F
Fuse
To PQ2/EQC
48V BAT FAIL
To other CONGI

20% PWANDOR To PQ2/EQC

OR ALIM
RACK LAMPS OR To PQ2/EQC
R/M BAT FAIL From
other CONGI
AND/OR alarms from
URG, NURG, LOSQ2, INT, UP

HOUSEKEEPING REMOTE ALARM
AND REMOTE 6/4 HOUSKEEPING_IN HK–IN
ALARM
2 HOUSKEEPING_OUT HK–OUT to/from
RIMMEL PQ2/EQC
FANS unit
and
FANS management MATRIXE
Serial Link

NON SDH
EQUIPMENT QMD to/from
M PQ2/EQC
INTERFACE TRANSCEIVER U
(Q2) X not used

OPERATION –9V
SYSTEM COAX
TRANSCEIVER
10BASE2 INTERFACE
(CTI) UNIVERSAL to/from
ETHERNET M PQ2/EQC
10BASET INTERFACE U
ADAPTER X not used
Q3 (AUI)
INTERFACE

+3.3 Vdc
FAIL

Remote RIBUS to/from
RIBUS MATRIXE
Inventory I/F
CMISS main and spare
CONGI
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 294. CONGI – Block diagram

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4.53 SERVICE card


The SERVICE card provides the following functions :

[1] AUX (auxiliary) channels management

[2] Input/output clock management

[3] EOW channels management

[4] POWER SUPPLY for internal board use.

[1] AUX channels management

It provides :

– four G.703 64 Kbit/s channels, ITU–T G.703 compliant

– four V11 channels , every one composed by data input, data output and clock

– four RS–232 channels

– two 2 Mbit/s G.703 signals that can be used as auxiliary channels

All the electrical interfaces are managed by the Matrix present on the unit.

[2] Input/Output clock management

Function performed:

– the unit can receives up to two 2 MHz clock (T3a and T3b) or up to two 2Mbit/s signals (T6a and T6b)
that could be used to synchronize the N.E. The unit provide software programmability to switch
between the two mode.

– the unit provides up to two 2 MHz clock (T4a and T4b) or up to two 2Mbit/s signals (T5a and T5b)
that can be used by another N.E. for synchronism purpose. The unit provide software
programmability to switch between the two mode.

[3] EOW management

The EOW channels allows to realize two different connections types:

a) between two stations (selective call)

b) omnibus call (one station is connected with all the other

To this purpose a telephone jack is present on the unit front panel.

Two extension channels with different connectors (RJ45 and RJ11) are available to establish a connection
with an external telephone set.

Moreover the channel on RJ11 can be used to establish a connection with an external telephone network
(future application).
The ”Omnibus call” is identified with ”00”.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Two LEDs L1 and L2 indicate the line status according to the type of call . Table 59. on page 578 and
Table 60. on page 578 show the L1 and L2 LEDs meaning for a selective/multiple call and for the omnibus
call.

Table 59. L1, L2 LEDs status for selective call

STATUS CALLING PARTY CALLED PARTY THIRD PARTY
L1 L2 L1 L2 L1 L2
(green) (yellow) (green) (yellow) (green) (yellow)
Line engaged ON –– ON –– ON ––
Selective call ON –– F –– ON ––
Replay to selective call ON –– ON –– ON ––
Third party inclusion ON –– ON –– ON ––
Third party inclusion ON ON ON –– ON ––
allowed
Third party selection ON ON ON –– F ––
ended
Reply to third party ON –– ON –– ON ––
Clear third party ON –– ON –– ON ––
Clear forward ON –– ON –– –– ––
Clear back ON –– ON –– –– ––

Table 60. L1, L2 LEDs status for omnibus call
STATUS CALLING PARTY CALLED PARTY NO ANSWER FROM
REPLY CALLED PARTY
L1 L2 L1 L2 L1 L2
(green) (yellow) (green) (yellow) (green) (yellow)
Line engaged ON –– ON –– ON ––
Omnibus call ON –– F F F F
T 60 seconds ON –– ON F F F
An answer at least
T 60 seconds ON –– ON ON F F
Called party inclusion
T 60 seconds ON –– ON F ON F
An answer at least
T 60 seconds ON –– ON ON ON F
Called party inclusion
Third party exclusion ON –– ON F ON F
Clear back ON –– ON F ON F
Clear forward –– –– –– –– –– ––

LEGENDA
1AA 00014 0004 (9007) A4 – ALICE 04.10

ON : LED on fixed
–– : LED off
F : LED flashing

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Selective call

The connection between two stations is made when the operator selects the service area desired and the
phone number of the station to call.

The logical sequence of the main operations about the connection is the following:

1) Manual selection of the zone where we want to call, pushing Selection Button. The relative
Zone’s Led will show the selection (ORANGE color).

2) Verify the state of the line in the zone:

– Leds L1 and L2 show the state of the line

– Free or Engaged Tone are sent to the Phone

3) If the line is free and the Inclusion Button is pushed, the phone will be linked to the Party Line
of the selected zone and the zone becomes engaged. The Green Led L1 will be ON on all
stations of the zone.

4) Selection of the phone number on the keyboard telephone handset

5) Recognize call on called station

The called station recognize the phone number and the consequent action is that the led L1
(Green) will flash and the buzzer will ring.

6) Start of the conversation

When the user hangs on the phone the conversation shall start In this condition the buzzer will
be off and the led L1 (green) will be on.

7) End of the conversation

The connection will finish when the caller or the called user will hang off the phone making free
the zone.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Omnibus call

The Omnibus connection between one station and all the others in one zone is made when the operator
selects the service area desired and the Omnibus call phone number ’00’.

The logical sequence of the main operations about the connection is the following:

1) Manual selection of the zone where we want to call, pushing Selection Button. The relative
Zone’s Led will show the selection (ORANGE color).

2) Verify the state of the line in the zone:

– Leds L1 and L2 show the state of the line
– Free or Engaged Tone are sent to the Phone

3) If the line is free and the Inclusion Button is pushed, the phone will be linked to the Party Line
of the selectioned zone that becomes engaged. The Green Led L1 will be ON on all stations
of the zone.

4) Selection of the phone number that is 00 for an Omnibus call.

5) Recognize call on called station the leds L1 (Green) and L2 (Yellow) will flash and the buzzer
will ring.

6) Start of the conversation

When the called users hang on the phone the conversation shall start. In this situation the
buzzer will be off, led L1 will be on (green) and led L2 will be flashing (yellow). During the
conversation, the caller talks and all the other users listen to, but if any of the other users press
the Inclusion Button they shall talk in the Omnibus Call while the button remains pressed.

7) End of the conversation

The connection will finish when the caller will hang off the phone making free the line.
In the Omnibus call when the users called want to finish the listening, they hang off the phone.

Matrix

The Matrix:

– receives / transmits data from /to the electrical interfaces (G.703, V11, RS–232, 2 Mbit/s, 2Mhz)

– receives configurations data from ”Management Bus”

– receives/transmits a serial signal from/to the digital party line (serial port)

– receives /transmits data (SOH bytes) from/to the STM–N ports and PQ2/EQC and realize cross
connections.

– receives clock and synchronism from the MATRIXE
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Digital party line

The function performed by the Digital Party Line are:

– manages the information coming from the SOH matrix

– detects DTMF code coming from the different channels
– party line
– manages LEDs , buzzer , push buttons and speech extensions present on the card front unit
– receives configuration information from the ”Management Bus”

AD/DA

This block is a voice–band audio processor and perform the transmit encoding (A/D conversion) and
receive decoding (D/A conversion) together with transmit and receive filtering for voice–band
communication systems.


• RIBUS I/F
release the Management–bus in case of power failure, and to use the remote inventory:
• M–BUS Driver

[4] POWER SUPPLY

The unit receives via backpanel connectors the –48V coming from CONGI boards.

The DC/DC converter present on the board generates the following voltage:

• + 3.3 V
• + 2.5 V to supply the party line and the SOH Matrix
• – 9 V to supply the phone

The Remote–Inventory and RIBUS–I/F blocks are powered by the 3.3 V power service coming from the
CONGI boards .
1AA 00014 0004 (9007) A4 – ALICE 04.10

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2 x 2 Mbit/s

T3a/T6a G.703 AUX to/from
2 x 2MHz input T3b/T6b STM–N ports
QAUX
T4a/T5a
OH to/from
2 x 2MHz output T4b/T5b DCC
MATRIX PQ2/EQC
T3
4 x 64 Kbit/s G.703 T4

ck system A
ck system A
4 x V.11 V.11

51 MHz

4 x RS232 RS–232

Serial
Port 2.5 V
L1 L2 Z1 Z8
Config. Status to/from
MATRIXE
Buzzer main and spare
zone Management
selection DIGITAL Bus
line PARTY M–BUS
reset LINE Driver
line
seizure

RAM Bus–OFF
RJ11
External Phone AD/DA RIBUS
extension Remote RIBUS
Inventory I/F
RJ45
External Phone AD/DA
extension FAULT

Telephone AD/DA

–9V

3.3 Vdc
from
3.3 V 48/60 V CONGI A B
2.5 V DC/DC
CONVERTERS
–9 V

SERVICE

Figure 295. SERVICE block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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4.54 FAN SHELF 19” AND RELEVANT FAN UNIT


The FANS SHELF 19” is composed by a mechanical structure and a back–plane.

The Fan Shelf is used to prevent high temperature inside the 1660SM equipment and must be equipped
with four FAN UNIT FOR FAN SHELF 19” and two FILTERS (DUST FILTER FOR FAN SHELF 19 or
METALLIC FAN GRID).

In the lower part of the shelf are present 5 connectors the meaning of which is explained in Figure 84. on
page 173.

Each FANS UNIT is composed by four fans and some electronic circuits necessary to:

• fans and alarms management

• filter management


• power supply

FANS ALARM MANAGEMENT

The core of the FAN UNIT FOR FAN SHELF is the “Fan Controller” that perform the following functionality:

– FAN power supply:at the start up the control of FANS is distributed in sharing mode, so the max
current value is reduced at only one FAN at a time.

– FAN control: the sensing criteria is integrated in order to have an alarm if almost one fan is out of order.
If an alarm is present (FAN AL1, FAN AL2, FAN AL3, FAN AL4) because a fan is temporary out of
order, the Fan controller try every 8 sec. to restart the fan.

– Temperature sensor: an external sensor generate an alarm (TEMP AL) when the temperature
exceed 55_ C.

– Remote inventory: through this interface the fan controller read the information stored in the flash
EPROM.

– LED control: the meaning of the led is reported in Figure 84. on page 173.

– Serial Alarms Interface: the FAN controller reports the alarm on a serial link toward the CONGI board
in order to transfer the information to the Shelf Controller on the MATRIXE.

The Fans controller generate an alarm called ALM_URG B #n if at least one fan is faulty or the 12Vdc is
not present.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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FILTER

Two filters are present at the bottom of the fan shelf in order to prevent dusty problem at cooled circuit.
This filter could not be removed permanently because the bottom grid performs the function of anti–fire

protection.

Two electro–mechanical sensor checks if the filters has been removed from the Shelf. These information
(FILTER AL1 and FILTER AL2) are than reported to the fan controller of each FAN UNIT FOR FAN SHELF
19”.
Dust Filter and Metallic Fan Grid are alternative parts.

REMOTE INVENTORY

It is a flash EPROM where are stored information about the unit like construction date, code number, maker
name, Card–type, etc.

POWER SUPPLY

The main power supply is coming from two connectors: power supply “A” and power supply “B” coming
from station battery.
The voltage value for both battery is : 48 o 60 Vdc ± 20% 3A max; in case of failure an alarm is generated
(AL BAT_A, AL BAT_B)

A DC/DC converter on the unit provides the 12V necessary to power the FANs. Another DC/DC converter
provides the 3.3V power supply voltage from which through a serial regulator is derived a 2.5 V.

If one of the above secondary voltage are not present , is generated an alarm (PSU ALM #n).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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BATTERY A PSU ALM #3
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ PSU ALM #2 PSU ALM

SLOT ID
BATTERY B 1
_
PSU ALM #1
ÏÏÏÏÏÏÏÏ
FAN UNIT PSU ALM #0

Housekeeping
BATTERY A
ÏÏÏÏÏÏÏÏ
FOR FAN SHELF 19”

CONGI
ÏÏÏÏÏÏÏÏ

to
BATTERY B
#0
FILTER AL1
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ALM_URG_B #0

ÏÏ
ÏÏ FILTER AL2

ÏÏÏÏÏÏÏÏ
ALM_URG_B #1

ALM_URG_B #2
1
_
ALM_URG

ALM_URG_B #3
ÏÏ ÏÏÏÏÏÏÏÏ
SLOT ID

ÏÏ F ÏÏÏÏÏÏÏÏ
I S FAN UNIT
PSU ALM #1
ÌÌ Ï
ÏÏ
Ï
ÌÌ ÏL
T
E
N
S
FILTER AL1
BATTERY A
ÏÏÏÏÏÏÏÏ
FOR FAN SHELF 19”
ÏÏÏÏÏÏÏÏ ALM_URG_B #1
O BATTERY B
E R #1
Ï
ÌÌ Ï
ÏÏ
R
FILTER AL1
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
FILTER AL2
1
ÏÏ
ÏÏ ÏÏÏÏÏÏÏÏ
Ï
ÏÏÏÏÏÏÏÏ
SLOT ID

ÏÏÏÏÏÏÏÏ
FAN UNIT
ÏÏ
ÏÏ BATTERY A
ÏÏÏÏÏÏÏÏ
FOR FAN SHELF 19”
ÏÏÏÏÏÏÏÏ
PSU ALM #2

BATTERY B ALM_URG_B #2
#2
ÏÏ
ÏÏ F
FILTER AL1
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
I S
FILTER AL2
ÌÌ Ï
ÏÏ
Ï
ÌÌ ÏL
T
E
N
S
FILTER AL2 ÏÏÏÏÏÏÏÏ
E
O ÏÏÏÏÏÏÏÏ
SLOT ID

R
Ï
ÌÌ Ï
Ï
R ÏÏÏÏÏÏÏÏ
ÏÏ 2
BATTERY A
ÏÏÏÏÏÏÏÏ
FAN UNIT
FOR FAN SHELF 19”
ÏÏÏÏÏÏÏÏ PSU ALM #3

BATTERY B ALM_URG_B #3
ÏÏ #3
ÏÏÏÏÏÏÏÏ
ÏÏ FILTER AL1
FILTER AL2
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
FAN SHELF 19”
1AA 00014 0004 (9007) A4 – ALICE 04.10

Figure 296. Fans shelf 19” general block diagram

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Figure 297. Fans unit for fan shelf 19” block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
FAN UNIT FOR FAN SHELF19”
CONGI unit ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
to FANS MANAGEMENT
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ NOT USED
B A
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ INTERFACE INTERFACE
ALARM ALARM
NOT USED
AL_FAN
SERIAL SERIAL
_ AL_FAN
ALM_URG_B
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 1
AL_12V
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ALARM FILTER AL2
NOT USED
ALM_URG_A FANS CONTROLLER
FILTER FILTER AL1
LED
ALARM SENSOR
POWER FANS CONTROL
SLOT ID

FAULTY FANS
INVENTORY
REMOTE
FAN
FAN
FAN
FAN

control 4
control 3
control 2
control 1

FAN AL1

FAN AL4
FAN AL3
FAN AL2

AL_12V

ALBAT_B
ALBAT_A

SENSOR
TEMPERATURE
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ TEMP_AL
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ + 12 V + 12 V + 12 V + 12 V
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ FAN AL4 FAN AL3 FAN AL2 FAN AL1
FANS4 FANS3 FANS2 FANS1
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ALBAT_B
REGULATOR
M R SERIAL
+2.5 V
R E +2.5 V Converter
A W +3.3 V DC/DC
BATTERY B
PSU ALM L O +3.3 V
A P Converter
+12 V BATTERY A
DC/DC
+12 V ALBAT_A
AL_12V



4.55 ASSEMBLED FANS UNIT


The ASSEMBLED FANS UNIT must be inserted in the “1660SM SUBRACK WITH FANS SHELF” in order

to prevent high temperature inside the equipment.

In the “1660SM SUBRACK WITH FANS SHELF” can be equipped up to two ASSEMBLED FANS UNIT
and one FILTER.

In the lower part of the “1660SM SUBRACK WITH FANS SHELF” are present 2 connectors on the left
(1st battery voltage and alarms) and one connector on the right (2nd battery voltage)

Each ASSEMBLED FANS UNIT is composed by six fans and some electronic circuits necessary to:

• fans and alarms management


• power supply

FANS ALARM MANAGEMENT

The core of the unit is the “Fan Controller” that perform the following functionality:

– FAN power supply:at the start up the control of FANS is distributed in sharing mode, so the max
current value is reduced at only one FAN at a time.

– FAN control: the sensing criteria is integrated in order to have an alarm if almost one fan is out of order.
If an alarm is present (FAN AL1, FAN AL2, FAN AL3, FAN AL4, FAN AL5, FAN AL6) because a fan
is temporary out of order, the Fan controller try every 8 sec. to restart the fan.

– Temperature sensor: an external sensor generate an alarm (TEMP AL) when the temperature
exceed 55_ C.

– Remote inventory: through this interface the fan controller read the information stored in the flash
EPROM.

– LED control: the meaning of the led is reported in Figure 85. on page 174.

– Serial Alarms Interface: the FAN controller reports the alarm on a serial link toward the CONGI board
in order to transfer the information to the Shelf Controller on the MATRIXE.

The Fans controller generate an alarm called ALM_URG B #n if at least one fan is faulty or the 12Vdc is
not present.

REMOTE INVENTORY

It is a flash EPROM where are stored information about the unit like construction date, code number, maker
name, Card–type, etc.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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POWER SUPPLY

The main power supply is coming from two connectors: power supply “A” and power supply “B” coming
from station battery.

The voltage value for both battery is : 48 or 60 Vdc ± 20% 3A max; in case of failure an alarm is generated

(AL BAT_A, AL BAT_B)

A DC/DC converter on the unit provides the 12V necessary to power the FANs. A step down converter
provides the 3.3V power supply voltage.

If one of the above secondary voltage are not present , is generated an alarm (PSU ALM #n).

FILTER

One filter is present at the bottom of the “1660SM SUBRACK WITH FANS SHELF” in order to prevent
dusty problem at cooled circuit. This filter could not be removed permanently because the bottom grid
performs the function of anti–fire protection.
Dust Filter and Metallic Fan Grid are alternative parts.

PSU ALM #1
ÏÏÏÏÏÏÏÏÏ PSU ALM
SLOT ID

1
_
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ASSEBLED FANS UNIT PSU ALM #0

Housekeeping
BATTERY A BATTERY A
ÏÏÏÏÏÏÏÏÏ

CONGI
BATTERY B

to
BATTERY B
ÏÏÏÏÏÏÏÏÏ#0
ALM_URG_B #0
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ 1
_
ALM_URG

ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ ALM_URG_B #1
SLOT ID

ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ PSU ALM #1
ASSEBLED FANS UNIT
BATTERY A
BATTERY B
ÏÏÏÏÏÏÏÏÏ ALM_URG_B #1
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
#1

ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ Back Panel

Figure 298. Assembled Fans unit power supply and alarms general block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Figure 299. Assembled Fans unit block diagram
1AA 00014 0004 (9007) A4 – ALICE 04.10

ASSEMBLED FANS UNT
CONGI unit ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
to FANS MANAGEMENT
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ NOT USED
B A
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ INTERFACE INTERFACE
ALARM ALARM
NOT USED
AL_FAN
SERIAL SERIAL
_ AL_FAN
ALM_URG_B
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 1
AL_12V
NOT USED
ALM_URG_A FANS CONTROLLER
LED
ALARM SENSOR
POWER FANS CONTROL
SLOT ID

FAULTY FANS
INVENTORY
REMOTE
FAN
FAN

control 6
control 1

FAN AL1

FAN AL6

AL_12V

ALBAT_B
ALBAT_A

SENSOR
TEMPERATURE
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ TEMP_AL
+ 12 V
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ + 12 V
FAN AL6
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ FAN AL1
FANS6 FANS1
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ +3.3 V
DOWN
STEP ALBAT_B
M R
R E
A W +3.3 V
Converter
BATTERY B
PSU ALM L O
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ +12 V
A P DC/DC
+12 V BATTERY A
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ AL_12V ALBAT_A


1AA 00014 0004 (9007) A4 – ALICE 04.10

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03

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5 TECHNICAL SPECIFICATIONS

Data indicated in the handbook must be considered as standard values
Data indicated in the contract must be considered as guaranteed values

5.1 General characteristics
Optical Line bit rate SDH: 155.520 Mbit/s (STM–1)
622.080 Mbit/s (STM–4)
2488.320 Mbit/s (STM–16)
9953.280 Mbit/s (STM–64)
SONET:155.520 Mbit/s (OC–3)
622.080 Mbit/s (OC12)

Electrical Line bit rate SDH: 155.520 Mbit/s (STM–1)
SONET:155.520 Mbit/s (OC–3)
PDH: 139.264 Mbit/s (PDH)

Type of optical fiber Single mode according to ITU–TG.652, G.654
and Multimode G.651.

Wave length See Table 66. on page 628, Table 67. on page
630, Table 68. on page 631 and Table 69. on
page 633 .

Span length Depending on fiber type and and optical power
budget reported in Table 66. on page 628,
Table 67. on page 630, Table 68. on page 631
and Table 69. on page 633 .

Application types TM and ADM in protected and unprotected linear
links and rings
DXC (64 STM–1 equivalent port at VC12 level)

Applied standards ITU–T G.703 for electrical interfaces
TU–T G.707 for SDH frame and multiplexing
structure
ITU–T G.957 and G.958 for optical interfaces
ITU–T G.821 and G.826 for transmission quality
ITU–T G813 for synchronization
ITU–T G.783 and G.841 for network protection
architectures
ITU–T G.784 and G.774 for system management
functions
ITU–T G.662 and G.663 for optical amplification
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Max quantity of each interface per shelf 378 x 2Mbit/s interfaces;
48 x 34 or 45 Mbit/s interfaces;
64 x 140Mbit/s interfaces;

256 x STM–1 electrical or optical interfaces;

64 x STM–4 optical interfaces;
300 x Ethernet 10/100 BaseT;
64 x Ethernet 1000 Base SX/LX;

Add–Drop and Cross connect features

Cross–Connections capacity (256 x 256) STM1 equivalent ports at VC12 and
VC3 levels
(384 x 384) STM–1 equivalent ports at VC–4
level.
Cross connect features 1660SM has a symmetrical architecture. All traf-
fic port (PDH SDH) of the same type have the
same functionality and behavior and there is no
inherent split between tributaries and aggregates.
This means that it is possible the allocation of the
PDH and VCi signals into every port.
Connection of concatenated AU4–4c among
STM4, STM–16, STM–64 ports is supported

Transmission delay 125 µs maximum for any traffic pathway

Protections

Network protection SNCP/I and SNCP/N
Drop Continue
Single ended 1+1 MSP
Dual ended 1+1 MSP
Dual ended 1:N MSP
2 fiber MS–SPRING at STM–16 and STM–64 inter-
faces
Collapsed single–node interconnection
Collapsed dual–node interconnection

Equipment protection 1 + 1 MATRIX and Timing EPS
1+1 ATM MATRIX (4X4 and 8x8) EPS
1+1 PR_EA MATRIX EPS
1+1 ISA ES–16 EPS
N +1 63x2 Mbit/s EPS (N= 6 max)
N + 1 3 x34 Mbit/s EPS (N= 15 max)
N + 1 3 x 45 Mbit/s EPS (N= 15 max)
N + 1 4 x STM–1 Electrical EPS (N= 15 max)
N + 1 16 x STM–1 Electrical EPS (N= 15 max)
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Management
interface

Local: Craft Interface RS232 PC compatible SUB–D 9 pins at 38 Kbit/s

(Personal Computer)

Remote: Craft Interface RS232 PC compatible SUB–D 9 pins at 38 Kbit/s;
(Personal Computer) it handles up to 31 NEs via DCC (D4 – D12 and/or
D1–D3)

Remote: Transmission Manage- G.773 QB3 10 base 2 and 10 base T
ment Network (TMN)
interface

Information Model According to ITU–T (G.774) and ETSI specification

Remote: Management Q2 (synchronous, bit rate = 19.2 kb/s)
messaging RQ2 (asynchronous, bit rates = 1.2–2.4–4.8–9.6
with Alcatel Non–SDH kb/s)
equipments
(Alcatel proprietary
protocol)

Protocol According to ITU–T G.774 and ETSI rec. ISO–OSI
Stack/Information 7–layers reference model.
Model messages The ATM/IP functions are organized according to
TCP/IP reference model; they are managed by
means of SNMP protocol tunneling over OSI layers

Dual addressing to It allows O.S. redundancy
O.S.

Operation processes

Configuration and provisioning Equipment, ports, add–drop, cross–connect,syn-
chronization, protection, MCF (Message Commu-
nications Function), SEMF (Synchronous Equipment
Management Function) OH connection

Software download It is made locally as well as remotely on non volatile
memories without traffic interruption

Performance monitoring According to G.784, G.826 and G.821.

Unit and Equipment acknowledgement Through Remote Inventory
(Company id, Unit Type, Unit Part Number, Serial
Part Number , Software Part Number etc.)
For detail refer to Operator Handbook.

Security Password, operator profile, back–up for programs
and data
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Output Housekeeping signals (CPO) and By electronic relay contacts to be connected to ex-
Remote Alarms ternal negative voltage:

Max. guaranteed current with closed condition 50 mA

Voltage drops vs. ground with closed condi- –2 V ÷ 0 V
tion

Max. allowed voltage with open condition –72 V

Input Housekeeping signals (CPI)

Max. guaranteed current with closed condition 3 mA

Voltage drops vs. ground with closed condi- –2 V ÷ 0 V
tion

Max. allowed voltage with open condition –72 V

Clock characteristics

Selectable input clock 2048 KHz from 2 Mbit/s port (T2)
2048 kHz external synch clock (2 input, T3a and
T3b) or 2048 Mbit/s external synch (2 input, T6a
and T6b)
STM–N ports (T1)

No. of selected clock (normal mode) 6 max.

Synchronization output 2048 kHz G.703 (2 output, T4a and T4b) or 2048
Mbit/s (2 output T5a and T5b)

Operational modes Locked to reference
Free–run mode ±4.6 ppm (PLL without reference)
Holdover mode drift 0.37 ppm max./day ( PLL with
stored frequency for more than half an hour,with no
selected input frequency)

Synchronization selection Priority and SSM algorithm

Protection against lighting surges TNV1 (Telecommunication Network Voltage) for
21 x 2 Mbit/s K20 access module

Additional features:

VCi Signal Label management
Programmable alarms severity
VC–4, VC–3 and VC–12 Tandem Connection Termination Monitoring (TCT/TCM)
J0 – Section Trace Management
J1/J2 Lower Order Path Trace Management (VC–12 and VC–3)
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.1.1 Optical Safety

5.1.1.1 Optical Safety compliance with European Norms

Compliancy to Optical Safety Norms is declared in that the equipment satisfies standardized Norms:

• EN 60825–1 ed.1994 + A11 ed.1996+A2 ed.2001

• IEC 60825–1 ed.1993 + A2 ed. 2001 (1999)

• EN 60825–2 ed.2000

• IEC 60825–2 ed.2000
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.1.1.2 Hazard Level classification

The HAZARD LEVEL classification of the different optical interfaces is given in Table 61. on page 596.

The hazard level can be assigned in accordance with the requirements of:

– IEC 60825–1 (1993) + Am. 1 (1997) and IEC 60825–2 (1993) + Am. 1 (1997)

or

– IEC 60825–1 (1998) + Am. 2 (2001) and IEC 60825–2 (2000)

Table 61. Hazard level classification of different optical interfaces

UNIT/PORT/ACRONYM OPTICAL INTERFACE HAZARD LEVEL
STM–1 S–1.1 (short haul) 1
STM–1 L–1.1 (long haul) 3A ; 1M
STM–1 L–1.2JE1 (long haul) 3A ; 1M
STM–1 MM1 3A ; 1M

STM–4 S–4.1 (short haul) 1

STM–16 S–16.1 (short haul) 3A ; 1M
STM–16 I–16.1 (Intra Office) 1
STM–16 L–16.2 colored port 16C 6400/12800 1M
STM–64 I–64.1 1
STM–64 S64.2b 1M
STM–64 L64.2b 1M

BST10 1M
BST15 1M
BST17 1M
PR16 1
OPTO TRX 1.25GBE SFP–LX 1000B–LX 1
OPTO TRX 1.25GBE SFP–SX 1000B–SX 1
OPTO TRX 1.25GBE SFP–ZX 1000B–ZX 1

ISA–PR S–4.1 (short haul) 1
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.1.1.3 Location type

The equipment shall be installed in “restricted locations” (industrial and commercial premises) or
“controlled locations” (optical cable ducts and switching centers).

5.1.1.4 Incorporated laser sources characteristics

Output optical interfaces data: the wavelength and the maximum optical power at the output connector
of incorporated laser sources is given in Table 66. on page 628, Table 67. on page 630, Table 68. on
page 631 and Table 69. on page on 633 .

5.1.1.5 Optical Safety Labelling

The labels reported below are put during factory settings, except those (explanatory) concerning the
STM–1 ports. In this case the labels are placed in a plastic bag and provided together with the module.
The customer shall affix the label on the fibre protection cover of P4E4N, P4S1N units or A2S1 adapter
depending on the particular interface of the module (STM–1 port). In the following description it is specified
when the label shall be affixed by the customer.

The optical interfaces which have HAZARD LEVEL 1 (see Table 61. on page 596) carry the following
explanatory label:

The label is put on the fibre protection cover of the following ports:

• STM–1 PORT with S–1.1 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the
customer)
• STM–4 PORT with S–4.1 interface
• STM–16 PORT with S–16.1 interface
• STM–16 PORT with I–16.1 interface

The optical interfaces which have HAZARD LEVEL 3A (see Table 61. on page 596) carry the hazard
symbol label:

The label is affixed near the optical connectors on the front plate of the following interfaces:

• L–1.1 (STM–1 PORT)
• L–1.2JE1 (STM–1 PORT)
• S–16.1 (STM–16 PORT)
• L–16.1 (STM–16 PORT)
• L–16.2 (STM–16 PORT)
1AA 00014 0004 (9007) A4 – ALICE 04.10

• L–16.2 (STM–16 colored PORT 6400/12800)

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The optical interfaces which have HAZARD LEVEL 3A (see Table 61. on page 596) and operate at 2nd
window, carry the following explanatory label (a multilanguage label kit is also provided):

INVISIBLE LASER RADIATION

CAUTION

DO NOT STARE INTO BEAM OR VIEW

LASER RADIATION WHEN OPEN DIRECTLY WITH OPTICAL INSTRUMENTS
DO NOT STARE INTO BEAM OR VIEW CLASS 3A LASER PRODUCT
DIRECTLY WITH OPTICAL INSTRUMENTS P.MAX=31mW, = 1300 nm IEC 825 1993

The label is affixed on the fibre protection cover of the following ports:

• STM–1 PORT with L–1.1 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the
customer)
• STM–4 PORT with L–4.1 interface

The optical interfaces which have HAZARD LEVEL 3A (see Table 61. on page 596) and operate at 3rd

INVISIBLE LASER RADIATION
CAUTION DO NOT STARE INTO BEAM OR VIEW
LASER RADIATION WHEN OPEN DIRECTLY WITH OPTICAL INSTRUMENTS
DO NOT STARE INTO BEAM OR VIEW CLASS 3A LASER PRODUCT
DIRECTLY WITH OPTICAL INSTRUMENTS P.MAX=50 mW, = 1550 nm IEC 825 1993

The label is put on the fibre protection cover of the following ports:

customer)
• STM–1 PORT with L–1.2JE1 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the
customer)
• STM–16 PORT with L–16.2JE2 interface
• STM–16 colored PORT 6400/12800

The optical interfaces which have HAZARD LEVEL 1M (see Table 61. on page 596) and operate at 2nd

The label is affixed on the fibre protection cover of the following ports:

customer)
1AA 00014 0004 (9007) A4 – ALICE 04.10


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The optical interfaces which have HAZARD LEVEL 1M and operate at 3rd window (see Table 61. on page
596), carry the following explanatory label (a multilanguage label kit is also provided):

The label is affixed on the fibre protection cover of the following parts:

customer)
• STM–1 PORT with L–1.2JE1 interface (P4E4N, P4S1N units or A2S1 adapter – affixed by the
customer)
• STM–16 colored PORT 6400/12800

The multilanguage label kit, for STM–1 ports, is placed in the same plastic bag provided together with the
module where explanatory labels (in English language), above mentioned, are put.

For all other ports (STM–4 and STM–16), the multilanguage label kit is inserted in the pre–package.

The multilanguage label kit contains a set of label that reproduce the same (explanatory) above depicted
in the following languages:

• Italian
• Francaise
• Spanish
• German

The customer, to its own discretion, may stick the labels with appropriate language upon the pre–existing
ones or, in case of STM–1 ports, directly on the fibre protection cover of P4E4N, P4S1N units or A2S1
adapter.

N.B. As an aid to identify the right label to be affixed to an optical module (HAZARD LEVEL 1,
HAZARD LEVEL 3A 2nd window, HAZARD LEVEL 3A 3rd window, HAZARD LEVEL 1M 1st
window, HAZARD LEVEL 1M 2nd window, HAZARD LEVEL 1M 3rd window) refer to paragraph
2.2 on page 86 where is reported the relationship between the Part number (ex. 3AL
78815AA––) and the interface type (ex. S–1.1) and then refer to Table 61. on page 596 where
is reported the relationship between the interface type (ex. S–1.1) and the Hazard Level.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.1.1.6 Aperture and fiber connectors

The locations of apertures and fibre connectors are reported on topographical drawings of units front view
and access cards front view in paragraph 2.4 on page 123.

5.1.1.7 Engineering design features

In normal operating conditions, unless intentional manumission, the laser radiation is never accessible.

The laser beam is launched in optical fibre through an appropriate connector that totally shuts up the laser
radiation. Moreover a plastic cover is fitted upon optical connectors by means of screws.

In case of cable fibre break, to minimize exposure times, ALS procedure according to ITU–T G.958 Rec.
is implemented either on STM–1 port or on STM–4 and STM–16 ports.

ALS timing are not longer than maximum specified in G.958.

5.1.1.8 Optical Safety instruction

The safety instructions for proper assembly, maintenance, and safe use including clear warning
concerning precautions to avoid possible exposure to hazardous laser radiation, are reported in para. 2.2
on page 29 thru 36 and more specifically in para.2.2.4.2 on page 33.

5.1.2 Electrical Safety

Safety status of the connections TNV2 (Telecommunication Network Voltage) for
with other equipments Remote Alarms, Housekeeping Alarms (CPO, CPI),
Rack Lamp (RM)
SELV (Safety Extra Low Voltage) for all the other

5.1.2.1 Electrical Safety compliance with European Norms

Compliancy to Electrical Safety Norms is declared in that the equipment satisfies standardized Norms :

• IEC 60950–1 ed.2001

• EN 60950–1 ed.2001

5.1.2.2 Electrical Safety Labelling

The labels reproduced in para.2.2.3.1 on page 31 are affixed during factory settings.

5.1.2.3 Electrical Safety instructions

The safety instructions for proper assembly, maintenance, and safe use including clear warning
concerning precautions to avoid possible exposure to hazardous voltages, are reported in para. 2.2 on
pages 29 thru 36 and more specifically in para.2.2.3.2 on page 31.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.2 Electrical interface characteristics

5.2.1 21 X 2 Mbit/s 75 Ohm electrical characteristics (A21E1)

Type of interface Electrical according to ITU–T Rec. G.703

Bit rate 2048 Kbit/s 50 ppm

No. of channels 21

Code HDB3

Signal amplitude 2.37 Vp on 75 Ohm unbalance

Attenuation 0 to 6 dB at 1024 Khz with law f

Return loss w12 dB 51–102 kHz
w18 dB 102–2048 kHz
w14 dB 2048–3072 kHz

Pulse shape See ITU–T Rec. G.703

5.2.2 21 X 2 Mbit/s 120 Ohm electrical characteristics (A21E1)

The electrical characteristics are the same of para 5.2.1 on page 601 except for:

Signal amplitude 3 Vp on 120 Ohm balance

5.2.3 21 X 2 Mbit/s 120 Ohm K20 electrical characteristics (A21E1)

The electrical characteristics are the same of para 5.2.2 on page 601 except for:

Protection against lighting surges According to ITU–T Rec. K20

5.2.4 3 X 34 Mbit/s electrical characteristics (A3E3)

Type of interface Electrical, according to ITU–T Rec. G703

Bit Rate 34368 Kbit/s 20 ppm

No. of tributaries 3

Code HDB3

Signal amplitude 1Vp/75ohms

Attenuation accepted on the incoming signal 0–12dB at 17.184kHz with law pf

1AA 00014 0004 (9007) A4 – ALICE 04.10

w18 dB 1720–34368 kHz
w14 dB 34368–51550 kHz

Pulse shape as per Fig.17 of ITU–T Rec. G.703

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5.2.5 3 X 45 Mbit/s electrical characteristics (A3T3)

Type of interface Electrical, according to ITU–T Rec. G703 and to
ANSI TS 102 Rec.

Bit rate 44.736 Kbit/s 20ppm

No. of tributaries 3

Code B3ZS

Signal amplitude According to ITU–T Rec. G.703 par.5.8 and ANSI
T1 102 Rec, Tab.5

Attenuation accepted on the incoming signal According to ANSI T1 102, Annex A2.5

Pulse shape as per Fig.14 of ITU–T Rec. G.703 or per Fig.14
of ANSI T1 102 Rec.

5.2.6 STM–1 electrical characteristics (A4 ES1 and ICMI)

Type of interface ITU–T Rec. G.703 compliant

Bit rate 155 520 Kbit/s 20 ppm

Code CMI

Attenuation accepted on the incoming signal 0–12.7 dB at 78 Mhz with law f

Return loss w15 dB at 8–240 Mhz


5.2.7 140 Mbit/s electrical characteristics (ICMI)

Type of interface ITU–T Rec. G.703 compliant

Bit rate 139264 Kbit/s 15 ppm

Code CMI

Attenuation accepted on the incoming signal 0–12 dB at 70 Mhz with law f

Return loss w15 dB at 7–210 Mhz

1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.2.8 Engineering Order Wire characteristics (SERVICE)

Speech Channel Interface Front–panel telephone jack
Handset Impedance 600 ohms

Bandwidth 300 to 3400 Hz
Handset Operating current 18 mA
Input Tx gain –4/0/0 dB
Output Rx gain 0/–7/0dB
Signalling DTMF compliant with ITU–T Rec. Q.23

Analog EOW Extension
Impedance 600 ohms
Bandwidth 300–3400 Hz
Tx level 0 dBr ±0.5 dB
Rx level 0 dBr ±0.5 dB

5.2.9 AUX channels characteristics (SERVICE)

Externally accessible data channel 4 x 64 Kbit/s, G.703 codirectional (Rx synchro-
(OH bytes termination is Software program- nized)
mable) 4 x 64 Kbit/s V11
4 x 9600 baud RS232
2 x 2 Mbit/s G.703

64 Kbit/s (Rx synchronized) G.703
Bit rate 64 Kbit/s
Timing signals 64 Kbit/s and 8 kHz coding style embedded
Bearer Two balanced pairs (120 ohms): one per route
Coding style According to ITU–T Rec. G.703 codirectional
Outgoing pulse shape See ITU–T Rec. G.703
Output Interface characteristics See ITU–T Rec. G.703
Incoming Interface characteristics as per the outgoing interface but modified by the
characteristics of the interconnection pair.
The input circuit can accept an 0 – 3 dB (128
KHz)
1AA 00014 0004 (9007) A4 – ALICE 04.10

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V11 64Kbit/s contradirectional interface

Type electrical, according to ITU–T Rec. V11

Receivers

Input impedance 6 Kohms

Rx levels ”1” or ”OFF” –0.3 V
”0” or ”ON” +0.3 V

Drivers

Differential output 2 V (Min.)

Use: intrabuilding connections

RS–232 oversampled interface 9600 Kb/s

Bit rate 9600 kb/s

Mode RS–232 Tx Rx data only

Electrical levels 24 Vpp

Use : intrabuilding connections

2 Mb/s G.703 /G.704 AUX channel interface

Electrical according to G.703 (75 Ohm or 120 Ohm using a
special cable)

Attenuation 0 to 6 dB

w18 dB 102–2048 kHz
w14 dB 2048–3072 kHz

1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.3 ATM interface characteristics

5.3.1 ATM matrix 4x4 switching capability (ATM4X4)

Throughput towards backpanel 622 Mbit/s

Switching capability VC and VP switching

PDH containers E1, E3

SDH containers VC–12, VC–3, VC–4

Local port VC–4

Port number 16 (any combination)

Connections 4000 max (VC or VP) unidirectional

VC/VP connection Hard and Soft VCC/VPC

Policing UPC and NPC (VC/VP)

Shaping Input and Output (VC/VP)

Congestion management SCD, EPD, TPD

OAM AIS, RDI, CC

Signalling PNNI

Table 62. ATM4X4 board: configurable TPs type and max, number
Board max. TPs VC4–4C VC4 VC3 VC12 E1 E3 T3 E1
acronym number IMA
ATM4X4 16 No Yes Yes Yes Yes Yes No No
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.3.2 ATM matrix 4x4V2 switching capability (ATM4X4V2)



PDH containers E1, E3,T3

SDH containers VC12, VC3, VC4

IMA(**) multiplexing E1 from 1 to 8 channels







OAM AIS, RDI, CC

Signalling PNNI

Table 63. ATM4X4V2 board: configurable TPs type and max, number
acronym number IMA
ATM4X4V2 252 No Yes Yes Yes Yes Yes Yes Yes

(**) For detailed information about IMA refer to AF–PHY–0086.001
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.3.3 ATM matrix 4x4 D3 switching capability (ATM4X4D3)



PDH containers E1, E3,T3

SDH containers VC12, VC3, VC4

IMA(**) multiplexing E1 from 1 to 8 channels







OAM AIS, RDI, CC

Signalling PNNI

Table 64. ATM4X4D3 board: configurable TPs type and max, number
acronym number IMA
ATM4X4D3 16 No Yes Yes Yes Yes Yes Yes Yes

(**) For deatailed information about IMA refer to AF–PHY–0086.001
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.3.4 ATM matrix 8x8 switching capability (ATM8X8)

Throughput towards backpanel 1.2 Gbit/s


PDH containers E1, E3

SDH containers VC–12, VC–3, VC–4, VC4–4c

Local port No







OAM AIS, RDI, CC

Signalling PNNI

Table 65. ATM8X8 board: configurable TPs type and max, number
acronym number IMA
ATM8X8 32 Yes Yes Yes Yes Yes Yes No No
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.4 PR_EA characteristics and MPLS data traffic management (PREA4ETH,
PREA1GBE)

Throughput 600 Mbit/s (with STM1 i/f)

1000 Mb/s (with 4xFE i/f)
1800 Mb/s (with 1xGbE i/f)

PDH containers (not operative) E1, E3

Ethernet frames MAC 802.3, optionally “tagged” with 802.1p/q fields
(user priority and VLAN identifier)
Martini Encapsulation: optional

SDH containers VC–12, VC–3, VC–4 (POS framing,
SDH/HDLC/PPP)

Local SDH port unstruct. VC–4, on opt. STM–1 (POS framing)

Local Ethernet ports 4 x 10/100Base–T
1 x1000Base–LX , 1 x 1000Base–SX or
1 x 1000Base–ZX

Remote Ethernet ports unstruct. VC–4, un–concatenated ethernet frames
over SDH (SDH/GFP framing)

Logical Ports number 63 (any combination)

Managed protocols SNMP,TMN messaging inside DCN

Congestion management W–RED (Weighed–Random Early Discard)
Cut–off on low priority traffic only

Quality of Service (QoS) Best Effort bandwidth (BE–BW)
Min–BW with regulated bursts
Guaranted constant BW

Police mechanism Dual–Rate Leaky–Bucket, based on PIR and CIR
values of the traffic contract

Scheduling HOL and WC–WFQ methods
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.5 PR characteristics

5.5.1 ISA–PR port card interface characteristics

Type of interface Plug–in SFP Optical module at 622.080 Mbps
(STM–4/OC–12), for up to 40 Km; see Table 67.
on page 630 for the optical characteristics

STM–4 / OC–12 ports 4 : 2 east + 2 west

Throughput towards backpanel 6.5 Gbps

Ethernet frames MAC 802.3, optionally “tagged” with 802.1p/q fields
(Ethernet frame priority and VLAN identifier).
Martini Encapsulation

SDH containers SDH VC–4 Virtual Concatenation (VC–4–nv):
VC–4–4v, VC–4–6v, VC4–8v, VC–4–4c

Managed Ethernet ports (located on access cards) 32 x 10/100Base–T
4 x1000Base–LX/SX/ZX
2 x1000Base–LX/SX/ZX and 16 x 10/100Base–T

Managed protocols SNMP V2c, NMS messaging in Band

Quality of Service (QoS) SLAs Best Effort bandwidth
Regulated bandwidth
Guaranted bandwidth

Cabling Optical fiber

Connector LC/PC on SFP (Small Formfactor Pluggable)
module
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.5.2 16FEA–PR access card interface characteristics

Type of interface Electrical, compliant to IEEE–802.3 standard,
10/100 Base–Tx

Transmit operations Auto–negotiation options:
10Mbps, 100Mbps, full–duplex, flow control

Bit rate Autosensing: 10 Mb/s and 100 Mb/s

Provisioning Granularity 100 Kbit/s

Signal amplitude, coding, attenuation, pulse According to IEEE–802.3 standard,
shape, return loss 10Base–T and 100Base–T

Port number 16 per access card used in conjunction with PR
port card

Cabling Twisted–pair, as per IEEE–802.3 rec.

Connector RJ45

5.5.3 2GBA–PR access card interface characteristics

Type of interface Plug–in Optical module 1000Base–LX or
1000Base–SX, 1000Base–ZX

Transmit operations Full–duplex, FlowControl

Bit rate 1000 Mb/s

Provisioning Granularity 100 Kbit/s

Tx and Rx Optical characteristics According to IEEE–802.3 standard,
1000Base–LX, 1000Base–SX and 1000Base–ZX

Port number 2 per access card used in conjunction with PR port
card

Cabling Optical fiber

Connector SFP (Small Formfactor Pluggable)
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.6 ETHERNET interface characteristics

5.6.1 Ethernet 10/100Base–T interface characteristics (ETH–MB + ETH–ATX)

Type of interface Electrical, full compliant to IEEE–802.3 standard,
10Base–T and 100Base–T

Transmit operations Auto–negotiation options:
10Mbps, 100Mbps, full–duplex

Bit rate Autosensing: 10 Mb/s and 100 Mb/s

Signal amplitude, coding, attenuation, pulse According to IEEE–802.3 standard, 10Base–T
shape, return loss and 100Base–T

Throughput towards backpanel (ports card) 622 Mbit/s

SDH containers VC–12, VC–3, VC–4

Port number 11 on the ports card
14 on the access card

Cabling Twisted–pair, as per IEEE–802.3 rec.

Connector RJ45
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.6.2 Ethernet switch port card characteristics (ES1–8FE)

Type of interface 10 / 100 Base T

Local Ethernet ports number 8 per each ports card

Ethernet over SDH ports number 8

VC termination max. VC–12 = 63
VC–3 = 3

Number of VCGs ETH over SDH VC–12 = 8
VC – 3 = 3

VCs per VCG max. VC–12 = 21
VC –3 = 3

VC comp. delay 64 ms

Mapping to SDH GFP–F
LAPS

Class forwarding criteria per port according to 802.1 Q (outer VLAN)
according to 802.1 p
according to 802.3 MAC DA

Look up tables number VLAN–ids = 1 K
MAC addresses = 8K

Multicast Ethernet

VLAN capabilities cVLAN (802.1 D)
pVLAN (SVLAN)

CoS Guaranteed
Best Effort

Policer Metering – token–bucket
Marking – 3 colors
Dropping – out of profile

Scheduler Head of line – 4 piorities
Deficit Round Robin

Spanning tree 802.1d
802.1 w
802.1s

Performance ethernet counter yes
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.6.3 Ethernet switch port card characteristics (ES1–8FX)

Type of interface 100 Base FX

Local Ethernet ports number 8 per each ports card


VC–3 = 3

VC – 3 = 3
VC – 4 = 1

VC –3 = 3
VC –4 = 1


LAPS


MAC addresses = 8K

Multicast Ethernet

VLAN capabilities VLAN (802.1 Q)
pVLAN (802.1ad)

CoS Guaranteed
Best Effort

Policer Metering – single rate token–bucket
Dropping – tail drop

Scheduler Queues/port = 3
Queuing = Strict Priority

802.1 w
802.1s

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5.6.4 Ethernet switch port card characteristics (ES4–8FE)

Type of interface 10 / 100 Base T
1000 Base SX/LX/ZX SFP

Local Ethernet ports number eight 10 / 100 Base T and one1000 Base SX/LX/
ZX SFP per each port card.

Ethernet over SDH ports number 16 (SMII mode), 2 (GMII mode)

VC–3 = 12
VC–4 = 4

Number of VCGs ETH over SDH VC–12 = 16 (SMII), 2 (GMII)
VC – 3 = 12 (SMII), 2 (GMII)
VC – 4 = 4 (SMII), 2 GMII)

VCs per VCG max. VC–12 = 50 (SMII), 63 (GMII)
VC –3 = 2 (SMII), 12 (GMII)
VC –4 = 1 (SMII), 4 (GMII)


LAPS


MAC addresses = 8K

Multicast Ethernet

pVLAN (SVLAN)

CoS Guaranteed
Best Effort

Policer Metering – token–bucket

Deficit Round Robin

802.1 w
802.1s
1AA 00014 0004 (9007) A4 – ALICE 04.10


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5.6.5 Ethernet switch port card characteristics (ISA ES–16)

Local Ethernet ports none


VC–3 = 12
VC–4 = 16

VC – 3 = 12
VC–4 = 16

VC –3 = 3
VC – 4 = 8


HDLC/PPP
LAPS

MPLS + exp. bits

Look up tables number VLAN–ids = up to 64 K
MAC addresses = up to 64K
MPLS labels = up to 64K

Multicast Ethernet
MPLS

MPLS capability Martini enc.
MPLS

pVLAN (SVLAN) (push, pop, swap)

CoS Guaranteed
Regulated
Best Effort

Policer Metering – token–bucket dual rate

1AA 00014 0004 (9007) A4 – ALICE 04.10

Deficit Round Robin

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Congestion Avoidance RED per queue


802.1 w
802.1s


MPLS counter yes

5.6.6 Access Card Gigabit Ethernet interfaces characteristics (GETH–AG)

Type of interface Plug–in Optical module 1000Base–LX or
1000Base–SX or 1000 Base–ZX

Transmit operations Full–duplex, Flow Control

Bit rate 1.25 Gb/s

1000Base–LX, 1000Base–SX and 1000Base–
ZX (refer to Table 71. on page 636, Table 72. on
page 637 and Table 73. on page 638 for details)

SDH containers VC–4xV

Ports number 2 on the access card if used in conjunction with
ETH–MB

Cabling Optical fibre

Connector LC–Duplex SFP (Small Formfactor Pluggable)
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.6.7 Gigabit Ethernet ports card interfaces characteristics (GETH–MB)

Type of interface lug–in Optical module 1000Base–LX or
1000Base–SX or 1000 Base ZX

Transmit operations Full–duplex, Flow Control

Bit rate 1.25 Gb/s

Throughput towards backpanel (ports card) 2 x 622 Mbit/s

1000Base–LX, 1000Base–SX and 1000Base–
ZX (refer to Table 71. on page 636, Table 72. on
page 637 and Table 73. on page 638 for details)

SDH containers VC–4xV

Local Gigabit Ethernet ports number 8 per each ports card

Cabling Optical fibre

Connector LC–Duplex SFP (Small Formfactor Pluggable)
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5.7 4 x ANY clients characteristics

The interface characteristics are related to client type according to the following paragraphs

5.7.1 Gigabit Ethernet LX

The interface is according to IEEE g.802.3 1000Base–LX (clause 38.4)

INPUT SIDE

· Bit Rate 1250 Mb/s
· Bit Rate Tolerance ±100 ppm
· Optical Connector LC
· Receive Sensitivity – 20 dBm max.
· Stressed Receive Sensitivity –14.4 dBm
· Max Receive Optical Power –3 dBm max.
· Opt. Operating Wavelength 1270 nm min., 1355 nm max
· Opt. Return Loss of Receiver 12 dB min.
· Opt. Modulation Amplitude 15 µW min., 1000 µW max.
· Signal detect – Asserted –20 dBm max. , –30 dBm +Hyst. min.
· Signal detect – Clearing –30 dBm min (avg.)
· Hysteresis 0.5 dB min.
· Signal detect Assert Time 100 µs (excepted SPI access time)
· Signal detect Clearing Time 100 µs (excepted SPI access time)

N.B.: GE flow control is not implemented.

OUTPUT SIDE

· Bit Rate Accuracy ±100 ppm
· Laser Type Class 1 laser safety
· Launched Optical Power –11.0 dBm min., –3 dBm max (avg.) 10 µm SMF
–11.5 dBm min., –3 dBm max (avg.) 50 µm MMF
–11.5 dBm min., –3 dBm max (avg.) 62.5 µm MMF
· Opt. Center Wavelength 1270 nm min., 1355 nm max
· Operating Range 2 m B 550 m (MMF 62.5 µm)
2 m B 550 m (MMF 50 µm)
2 m B 5000 m (SMF 9 µm)
· Opt. Spectral Width (∆λRMS) 4 nm max.
· Opt. Extinction ratio 9 dB min
· Opt. Modulation Amplitude 189 µW min.
· Opt. Rise/Fall time (tr/tf) 260 ps max (20% B 80%)
· Relative Intensity Noise –116 dB/Hz max.
· Deterministic Jitter 0.200 UI max.
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5.7.2 Gigabit Ethernet SX

The interface is according to IEEE g.802.3 1000Base–SX

INPUT SIDE

· Bit Rate Tolerance ± 100 ppm
· Max Receive Optical Power – 0 dBm max.
· Signal detect Clearing Time 350µs (excepted SPI access time)

N.B.: GE flow control is not implemented.

OUTPUT SIDE

· Launched Optical Power –9.5 dBm min., –1.5 dBm max (avg.) 50 µm MMF
–9.5 dBm min., –1.5 dBm max (avg.) 62.5 µm MMF
· Opt. Rise/Fall time (tr/tf) 260 ps max (20% B 80%)
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5.7.3 Fiber Channel 100–SM–LL–I

The FC I/F is compliant to Ansi x3.230 standard (100–SM–LL–I).

INPUT SIDE

· Bit Rate 1062.5 Mb/s
· Receive Sensitivity –20 dBm max.
· Stressed Receive Sensitivity –14.4 dBm
· Max Receive Optical Power –3 dBm max.

OUTPUT SIDE

· Launched Optical Power –12.0 dBm min., –3 dBm max (avg.) 9 µm SMF
· Operating Range 2 m B2 Km
· Fiber Core Diameter 9 µm
· Opt. Spectral Width (∆λRMS) 4 nm max.
· Opt. Rise/Fall time (tr/tf) 260 ps max (20%B80%)
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5.7.4 Fiber Channel 100–M5–SL–I

The FC I/F is compliant to Ansi x3.230 standard (100–M5–SL–I) except where specified.

INPUT SIDE

· Receive Sensitivity –13 dBm max.
· Max Received Optical Power –1.5 dBm max.

OUTPUT SIDE

· Launched Optical Power –9.5 dBm min., –1.5 dBm max (avg.) 50 µm MMF
–9.5 dBm min., –1.5 dBm max (avg.) 62.5 µm MMF
· RMS spectral width (max) 4 nm max.
· Opt. Rise/Fall time (tr/tf) 260 ps max (20% 80%)
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5.7.5 Fast Ethernet (100BASE FX)/FDDI

FDDI and Fast Ethernet I/F is compliant to ANSI x3.184–1993 and IEEE 802.3 except where specified.

INPUT SIDE

· Max. Receive Optical Power –8 dBm min. (avg.)
· Opt. Return Loss of Receiver 12.5 dB min.
· Signal detect – Asserted –31 dBm max., –42 dBm + Hyst. min. ;
· Hysteresis 1 dB min. B 3 dB max.

OUTPUT SIDE

· Launched Optical Power –15 dBm min., –8 dBm max (avg.)
· Opt. Spectral Width (∆λRMS) 2.5 nm max.
· Opt. Extinction ratio 8.2 dB min
· Optical Rise/Fall Time (tr/tf) 1.5 ns max. (20% B 80%)
· Relative Intensity Noise (RIN) 125 dB/Hz nom., –112 dB/Hz max.

N.B. :The Client Transmit Port provides a different ”Launched Optical Power” level than what required by
the FDDI FE standards:
– MMF : –20 dBm B –14 dBm
– SMF Cat I : –20 dBm B –14 dBm
– SMF Cat II : 4 dBm B 0 dBm
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5.7.6 ESCON

ESCON I/F is compliant to IBM SA–0394–03

INPUT SIDE

· Signal detect – Asserted –31 dBm max., –42 dBm + Hyst. min.

OUTPUT SIDE


N.B. The Client Transmit Port provides a different ”Launched Optical Power” level than what required by
the ESCON standard:
–MMPL : –20 dBm B –15 dBm
–SMPL : –4 dBm B –0 dBm

The bit rate accuracy required by ESCON standard is ±200 ppm
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5.7.7 Digital Video

Digital Video I/F is compliant to ITU–R Rec. BT.656–4, BT1363–1 and BT1367.

INPUT SIDE

· Bit Rate Tolerance 100 ppm
· Signal detect – Asserted –31 dBm max., –42 dBm + Hyst. min.

OUTPUT SIDE

· Bit Rate Accuracy 100 ppm
· Output jitter 0.2 UIpp (10 Hz– 27 MHz)

N.B: The Client Transmit Port provides a different ”Launched Optical Power” level than what required by
the DV standards:
–MM: –12 dBm B –7.5 dBm
–SM: –12 dBm B –7.5 dBm
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.8 Optical interface characteristics

STM–1 optical characteristics:

Types of optical interfaces S–1.1, L–1.1, L–1.2 or L–1.2JE, MM1
Characteristics are given in Table 66. on page 628.

Optical connectors SC/PC or FC/PC (alternative units)

Pulse shape See ITU–T G.957


Types of optical interfaces S–4.1, L–4.1 , L–4.2
Characteristics are given in Table 67. on page 630




Types of optical interfaces I–16.1, S–16.1, L.16–1, L.16–2 , L.16–2 JE2,
L.16–2JE3, Characteristics are given in Table 68. at
page 631.
The ”second generation” optical interface character-
istics are given in Table 16 which applies for HM1
Optical Units.

Optical connectors SC/PC, FC/PC, SFF, SFP (alternative units)



Types of optical interfaces I–64.1, S–64.2b, L–64.2b

Optical connectors SC/PC


GigaBit Ethernet Optical characteristics Interface type: 1000B–SX, 1000B–LX ,1000B–ZX
Characteristics are given in Table 71. on page 636,
Table 72. on page 637 and Table 73. on page 638
Optical connectors: LC/PC on SFP (Small Formfactor
Pluggable) module
Pulse shape: see IEEE 802.3
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Booster
(Optical Fiber Amplifier) characteristics:

Types of Booster BST10 (+10 dBm), BST15 (+15 dBm) and BST17

(+17 dBm).

Characteristics are given in Table 74. on page 639


Optical Preamplifier (PR16) characteristics:


Wavelength bandwidth (main signal): 1530 to 1565 nm

Input power: –37 dBm to –18 dBm

Output power: –15 dBm
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Table 66. Parameters specified for STM–1 Optical Interface

CHARACTERISTICS UNIT VALUES

DIGITAL SIGNAL STM–1 according to G.707 and G.958

Kbit/s

Nominal bit rate 155520

S–1.1 L–1.1 L–1.2 L–1.2 JE1
Application code (Table 1/G.957)
nb1

Operating wavelength range nm 1261–1360 1280–1335 1480–1580 1530–1560
TRANSMITTER AT REFERENCE
POINT S
Source type SLM/MLM SLM/MLM SLM SLM

Spectral characteristics

maximum RMS width nm 7.7 4 – –
maximum –20 dB width nm – – 1 1
minimum side mode
dB – – 30 30
suppression ratio

Mean launched power

maximum dBm –8 0 0 0
minimum dBm –15 –5 –5 –4

Minimum extinction ratio dB 8.2 10 10 10
OPTICAL PATH BETWEEN S AND R
Attenuation range dB 0–12 10–28 10–28 10–29

Maximum dispersion ps/nm 100 250 1900 3200

Minimum optical return loss of cable
dB NA NA 20 20
plant at S, including any connectors

Maximum discrete reflectance between
dB NA NA –25 –25
S and R
RECEIVER AT REFERENCE POINT R
Type of detector In Ga As In Ga As In Ga As In Ga As
PIN PIN PIN PIN

Mean received power at BER= 1E–10
• Minimum (sensitivity) dBm –28 –34 –34 –34
• Maximum (overload) dBm –8 –10 –10 –10

Maximum optical path penalty dB 1 1 1 1
Maximum reflectance of receiver mea-
dB –14 –14 –25 –25
sured at R
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nb1: To be used with Optical Boosters up to +15 dBm on G652 and G653 fibre
N.A = not applicable
table continue

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STM–1 according to G.707 and
DIGITAL SIGNAL
G.958
Nominal bit rate

Kbit/s 155520

Application (ALCATEL code) MM–1

Operating wavelength range nm 1270–1360

POINT S
Source type SLM
maximum RMS width nm –
maximum –20 dB width nm 1
minimum side mode
dB 30
suppression ratio
Mean launched power
maximum dBm –14
minimum dBm –19
Minimum extinction ratio dB 10

Attenuation range dB 0–10
Maximum dispersion ps/nm NA
dB NA
dB NA
S and R

Type of detector In Ga As
PIN
Minimum sensitivity (BER 10–10) dBm –30
Minimum overload dBm –14
Maximum optical path penalty dB 1 (a)
dB –14
sured at R
NOTES: a= with max 3 Km of multimode fibre 50/125 um G.651
NA= not applicable

end of table.
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Table 67. Parameters specified for STM–4 Optical Interface



Kbit/s

Nominal bit rate 622.080

S–4.1 L–4.1 L–4.2 L–4.2 JE
Application code (Table 1/G.957)
nb3 nb1, nb2
Operating wavelength range nm 1274–1356 1280–1335 1480–1580 1530–1560
POINT S
Source type MLM SLM SLM SLM


maximum RMS width nm 2.5 – – –
maximum –20 dB width nm – 1 1 0.6
minimum side mode
dB – 30 30 30
suppression ratio
Mean launched power

maximum dBm –8 +2 +2 +2
minimum dBm –15 –3 –3 –3
Minimum extinction ratio dB 8.2 10 10 10
Attenuation range dB 0–12 10–24 10–24 10–27
dB 14 20 24 24
dB –20 –25 –27 –27
S and R
Type of detector In Ga As In Ga As In Ga As In Ga As
PIN PIN PIN PIN
Mean received power at BER= 1E–10
• Minimum (sensitivity) dBm –28 –28 –28 –32
dB –20 –20 –27 –27
sured at R

nb1: Suitable for interworking with the L–4.2JE of the ADM product family with max dispersion 2400 ps/nm;
on this application the attenuation range is 10–28 dB.
nb2: For long distance applications and additionally suitable to be used with Optical Boosters up to +15
1AA 00014 0004 (9007) A4 – ALICE 04.10

dBm on G652 and G653 fibre.
nb3: Suitable for interworking with L–4.1 of ADM product family. In this application the power budget is
10–24 dBm, 250 ps/nm dispersion.

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Table 68. STM–16 Optical interfaces (Single Channel)

DIGITAL SIGNAL STM–16 according to G.707

Nominal bit rate Kb/s and G.958

2488320
Application code S–16.1 L–16.1 L–16.2

Operating wavelength range 1270–1360 1280–1335 1500–1580

TRANSMITTER AT REFERENCE POINT S
Source type SLM SLM SLM
– maximum RMS width nm – – –
– maximum –20 dB width nm 1 1 1
– minimum side mode suppression ratio dB 30 30 30
Mean launched power
– maximum dBm 0 +2 +2
– minimum dBm –5 –2 –2
Minimum extinction ratio dB 8.2 8.2 8.2
Attenuation range dB 0–12 10–24 10–24
Maximum dispersion ps/nm 100 250 1600
Minimum optical return loss of cable plant at S, including any dB 24 24 24
connectors
Maximum discrete reflectance between S and R dB –27 –27 –27
RECEIVER AT REF. R
Type of detector InGaAs InGaAs InGaAs
PIN APD APD

Mean received power at
BER= 1E10–10
• Minimum (sensitivity) dBm –18 –27 –28
• Maximum (overload) dBm 0 –8 –8
Maximum optical path penalty dB 1 1 2
Maximum reflectance of receiver measured at R dB –27 –27 –27

Table Continue
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Nominal bit rate Kb/s 2488320

Application code L–16.2JE1 L–16.2 JE2 L–16.2 JE3 I–16.1
nb2 nb1 nb3
Operating wavelength range 1530–1560 1550–1560 1550–1560 1266–1360

Source type SLM SLM–ILM SLM–ILM MLM
– maximum RMS width nm – – – 4
– maximum –20 dB width nm 0.5 0.2 0.2 –
– minimum side mode suppression ratio dB 30 30 30 –
Mean launched power
– maximum dBm +4 +2 +2 –3
– minimum dBm +1 –3 –3 –10
Minimum extinction ratio dB 8.2 8.2 8.2 8.2
Attenuation range dB 13–28 nb1 nb3 0–7

Minimum optical return loss of cable plant at dB 24 24 24 27
S, including any connectors
Maximum discrete reflectance between S dB –27 –27 –27 –27
and R
RECEIVER AT REF. R
Type of detector InGaAs InGaAs InGaAs InGaAs
APD APD APD APD

Mean received power at
BER= 1E10–10
• Minimum (sensitivity) dBm –29 –29 nb3 –18
Maximum reflectance of receiver measured dB –27 –27 –27 –27
at R
nb1: to be used with booster amplifier on G.652 fiber; attenuation range according to the specific 1664OA
power budget
nb2: To be used with booster amplifier up to + 15dBm on G653 fiber; or in stand alone configuration
nb3: To be used with booster in conjunction with the 1664OA preamplifier on G.652 and G.653 fiber;
attenuation range according to the 1664OA characteristics. Suitable for submarine application too, in
conjunction with Alcatel booster/preamplifier: specific reference value of max dispersion at 5400 ps/nm with
optical path penalty 2 dB.
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End of table

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Table 69. STM–16 Optical interfaces (Multi Channel)



Nominal bit rate Kb/s 2488320
Application code 16 x L.16.2JE 16 x L.16.2JE
6400 ps/nm 12800 ps/nm
Central operating wavelength nm see nb1 see nb1
Source type ILM ILM
– maximum RMS width nm – –
– maximum –20 dB width nm 0.2 0.1
– minimum side mode suppression ratio dB 30 30
Mean launched power
– maximum dBm +2 +2
– minimum dBm –3 –3
Minimum extinction ratio dB 8.2 8.2
Max loss budget dB see nb2 see nb2
Loss limited distance Km see nb2 see nb2
Maximum chromatic dispersion ps/nm 6400 12800
Dispersion limited distance Km 320 640
Minimum ORL at S (including connectors) dB 24 24
Total average PMD (1st order) ps 40 40
Operating wavelength range 1530–1561 1530–1561
Type of detector InGaAs APD InGaAs APD
OSNR dBm/0.1nm 19 19
Mean received power at BER= 1E10–10
• Minimum (sensitivity) dBm –23 –23
• Maximum (overload) dBm –10 –10

Maximum reflectance of receiver measured at R dB –27 –27
nb1 : One of the following 16 coloured transmitter according to the ITU–T standard G.692 (ex G.MCS):
• 8 “Red” wavelengths (nm):1547.72 / 15493.2 / 1550.92 / 1552.52 / 1554.13 / 1555.75 / 1557.36 /
1558.98
• 8 “Blue” wavelengths (nm):1531.90 / 1533.47 / 1535.04 / 1536.61 / 1538.19 / 1539.77 / 1541.35 /
1542.94
Laser transmission at 100 Ghz grid space allows compatibility with 32 channel systems
nb2 : According to the WDM system specs
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Table 70. Parameters specified for STM–64 optical interfaces (Single Channel)


DIGITAL SIGNAL STM–64 according to

G.707, G.958, G.691
Nominal bit rate Kbit/s 9,953,280
Application code S–64.2b I–64.1
Operating wavelength range nm 1530÷1565 1290÷1330
TRANSMITTER at reference point S
Source type EA–ILM SLM
Spectral characteristics:
– maximum spectral power density mW/MHz n.a n.a.
– maximum –20 dB width nm t.b.d. 1
– minimum side mode suppression ratio dB 30 30
– chirp parameter radians n.a. n.a.
Mean launch power:
– maximum dBm +2 –1
– minimum dBm –1 –6
Minimum extinction ratio dB 8.2 6
OPTICAL PATH between S and R
Attenuation range dB 3÷11 0÷4
Chromatic dispersion:
– maximum ps/nm 800 6.6
– minimum ps/nm n.a. n.a.
Passive dispersion compensation:
– maximum ps/nm n.a. n.a.
– minimum ps/nm n.a. n.a.
Maximum DGD ps/nm 30 30
Minimum ORL at S (including connectors) dB 24 14
RECEIVER at reference point R
Type of detector PIN PIN
Mean received power:
(@ BER= 10–12 and OSNR=19 dB/0.1 nm)
– minimum (sensitivity) dBm –14 –11
– maximum (overload) dBm –1 –1
Maximum optical path penalty dB 2 1
Maxim. reflectance of receiver measured at R dB –27 –14

t.b.d.= to be defined
n.a. = not applicable
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DIGITAL SIGNAL STM–64 according to
G.707, G.958, G.691

Nominal bit rate Kbit/s 9,953,280

L–64.2b L–62.2b
L–64.2b
“Reduced” “Extended”
Application code with Booster
(refer to (refer to
+10 dB
para. 5.8.3) para. 5.8.2)
Operating wavelength range nm 1530÷1565 1530÷1565 1530÷1565
TRANSMITTER at reference point S
Source type EA–ILM EA–ILM EA–LIM
Spectral characteristics:
– maximum spectral power density mW/MHz n.a n.a. n.a.
– maximum –20 dB width nm t.b.d. t.b.d. t.b.d.
– minimum side mode suppression ratio dB t.b.d. t.b.d. t.b.d.
– chirp parameter radians n.a. n.a. n.a.
Mean launch power:
– maximum dBm +3 +12 (*) +13
– minimum dBm 0 +10 (*) +10
Minimum extinction ratio dB 8.2 8.2 ––
OPTICAL PATH between S and R
Attenuation range dB 0÷16 13÷22 16÷28
Chromatic dispersion:
– maximum ps/nm 1200 1600 2000
– minimum ps/nm n.a. n.a. n.a.
Passive dispersion compensation:
400 (By 20
– maximum ps/nm n.a. n.a.
DCU)
– minimum ps/nm n.a. n.a. ––
Maximum DGD ps/nm 30 30 ––
Minimum ORL at S (including connectors) dB 24 24 ––
RECEIVER at reference point R
Type of detector PIN PIN PIN
Mean received power:
(@ BER= 10–12 and OSNR=19 dB/0.1 nm)
– minimum (sensitivity) dBm –16 (**) –14 –18
– maximum (overload) dBm +3 –1 –3
Maximum optical path penalty dB n.a. 2 n.a.
Maxim. reflectance of receiver measured at R dB –27 –27 ––

t.b.d.= to be defined
n.a. = not applicable

(*) – Achived with 10 dB Booster
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(**) – With fiber

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Table 71. Parameters specified for 1000B–SX Optical Interface

CHARACTERISTICS VALUES

DIGITAL SIGNAL GBE interface according to IEEE 802.3

Nominal bit rate Gbps 1.250 Gbps
Application code 1000B–SX
TX SIDE UNIT CONDITIONS MIN MAX
Output optical power dBm – –9.5 –4.0
Output optical power BOL
dBm – –8.5 –4.0
(25ºC, nominal power supply)
Operating wavelength range nm – 820 860
∆λ rms nm – – 0.85
Relative Intensity Noise dB/Hz – – –117
RX SIDE
Type of detector IN Ga As PIN
Sensitivity dBm * – –18.0
Sensitivity BOL
dBm * – –19.0
See IEEE –12.5 (62.5µm)
Stressed Receiver Sensitivity dBm –
802.3 –13.5 (50µm)
Maximum input optical power dBm – – 0
Maximum input optical power BOL
dBm – – +1.0
Loss of signal – Assert Pin dBm – –30 –18.0
Loss of signal – Deassert Pin dBm – –30 –17.0
LOS Hysteresis dB – 1 4.0
Data Output Rise/Fall time ps – – 250
* With fiber: 550 m MMF 50 µm (500 MHz Km @ 850nm)
500 m MMF 50 µm (400 MHz Km @ 850nm)
275 m MMF 62.5 µm (200 MHz Km @ 850nm)
220 m MMF 62.5 µm (160 MHz Km @ 850nm)
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Table 72. Parameters specified for 1000B–LX Optical Interface



Application code 1000B–LX
Output optical power (SMF) dBm – –11.0 –3.0
Output optical power BOL (SMF)
dBm – –10.0 –3.0
Output optical power on MMF 50
dBm – –11.5 –3.0
62.5µm
Output optical power BOL on MMF
50 62.5µm (25ºC, nominal power dBm – –10.5 –3.0
supply)
∆λ rms nm – – 4.0
Relative Intensity Noise dB/Hz – – –120
RX SIDE
Type of detector IN Ga As PIN
Sensitivity dBm * – –20.0
Sensitivity BOL
dBm * – –21.0
See IEEE
Stressed Receiver Sensitivity dBm – –14.4
802.3
Maximum input optical power dBm – – –3.0
Maximum input optical power BOL
dBm – – –2.0
Loss of signal – Deassert Pin dBm – –30 –20.0
LOS Hysteresis dB – 1 4.0
Data Output Rise/Fall time ps – – 175
* With fiber: 550 m MMF 50 µm (400 MHz Km @ 1300nm)
550 m MMF 62.5 µm (500 MHz Km @ 1300nm)
5000 m SMF 10 µm
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Table 73. Parameters specified for 1000B–ZX Optical Interface



Application code 1000B–ZX
Output optical power (SMF) dBm – 0.0 + 5.0
∆λ rms nm – – 1.0
RX SIDE
Sensitivity
Pmin1 dBm – –24.0 (*)
Pmin2 – –22.0 (**)
Overload dBm – 0 –
Loss of signal – Deassert Pin dBm – –29.5 –24.0
LOS Hysteresis dB – 0.5 6.0
Reflectance ps – – –12.0
(*) – Conditions:
BER=10^–12
Measured at 1250 Mbps, PRBS 2^7–1, NRZ
back to back

(**) – Conditions:
BER=10^–12
Measured at 1250 Mbps, PRBS 2^7–1, NRZ
with fiber
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Table 74. Parameters specified for Optical Booster


BOOSTER + 10 dBm + 15 dBm + 17 dBm

Maximum Output power dBm +12 + 17 + 19

Minimum Output power dBm +10 + 15 + 17

Maximum Input power dBm +4 +4 +4

Minimum Input power dBm –6 –6 –6

Polarization Depending Gain dB 0.5

Reverse ASE power level dBm ≤ –20

Input Optical Return Loss (ORL) dBm ≥ 27

Pump Leakage to Input dBm ≤ –36

Pump Leakage to Output dBm ≤ Pout–30

Maximum ORL tolerable at Input dB 27

Power Wavelength Bandwidth nm 1530÷1565
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5.8.1 Example of a link using 1660SM with L–16.2 JE2 Port and 15 dBm Booster

Booster
Ï Ï ÏÏÏÏÏÏ ÏÏÏÏÏÏ STM16

STM16

Ï Ï ÏÏÏÏÏÏ
Port ÏÏÏÏÏÏ Port
Ï Ï ÏÏÏÏÏÏ ÏÏÏÏÏÏ
Booster S R
Input

min –6dBm 15dBm –29dBm
max 4dBm 17dBm –9dBm

SPECIFICATIONS

Maximum chromatic dispersion 3200 (ps/nm)

Optical fiber used G.652

– fiber attenuation 0.25 dB/km

– chromatic dispersion of the fiber 18 ps/nm/km

– penalty 1 dB

Attenuation range
26 dB
min = +17–(–9)
43 dB
max = +15 –(–29)–1

Minimum span length (26dB/0.25) 104 Km

Maximum span length
172 Km
(due to the attenuation (sensitivity: 43/0.25

Following there are the formulas to calculate the minimum and maximum span length. The maximum
length can be limited by the receiver sensitivity or by the maximum chromatic dispersion, whichever is
most restrictive; the minimum length is limited by the receiver overload.
The optical interface characteristics are deduced from Table 68. on page 631 depending on the type of
interface.
The optical fiber characteristics are reported in rec. ITU–T G.957.

Span attenuation range:
Min Atten.= (max Tx Power)–(min. Rx Overload)=+17–(–9)=26dB
Max Atten.= (minTx Power)–(min. Rx Sensitivity)–(penalty)=+15–(–29)–21=43 dB

Minimum span length (for overload) = (Min Att.)/(fiber att.)=26/0.25=104 Km
Maximum span length (for sensitivity) = (Max Att.)/(fiber att.)=43/0.25=172 Km
Maximum span length (for dispersion) = (Max dispers.)/(fiber disp.)=3200/18=177.7 Km

Thus the maximum fiber span length is limited for attenuation (sensitivity): 172 Km,
1AA 00014 0004 (9007) A4 – ALICE 04.10

while the minimum span to avoid overload problems should be 104 Km.

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5.8.2 Example of a link using 1660SM with L–64.2b “Extended”

The L–64.2B extended application described here below is suitable to cover span with attenuation range
(S–R) up to 28 dB, including optical path penalty (2dB). The performances of this application (max.

attenuation range and max. chromatic dispersion) is between the ones of L64.2b and V64.2. Although it

is not part of standard ITU–T applications, it could be used for some customer specific cases.

The solution is based on usage of BW interfaces of 1660SM (“STM 64 PORT L– 64.2 B FC” card), DCU
(Optical Compensation Device), and booster.

Figure 300. below shows the network block diagram for implementing the application (parameters have
to be considered EOL):

Booster
Pin max.: +4
= 3.5/5 dB
DCU
ÏÏÏ
ÏÏÏÏÏÏ1660SM
L64.2b Port
ÏÏÏÏÏÏ ÏÏÏÏÏ
ÏÏÏÏÏ 20
ÏÏÏ
+10
ÏÏÏ ÏÏÏÏÏÏ
1660SM
L64.2b Port
ÏÏÏÏÏÏ
(Tx) (400ps/nm) (Rx)
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
Pin min.: –6
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
MPI–S MPI–R

Max: +3 Max: – 0.5 28 dBm
Min: 0 Min: –5

max+13dBm max–3dBm
min +10dBm min –18dBm

Figure 300. Example of a link using 1660SM with L–64.2b “Extended”

The L–64.2B Extended application is suitable for transmission with G.652, G.653 and G.655 fibers. Find
below main specifications:

– Wavelength: 1530–1565;

– Attenuation Range [S–R]: 16–28 dB (optical path penalty included – if needed, attenuation range
can be extended via optical attenuators);

– Maximum supported dispersion: 2000 ps/nm (achievable through 20km–400ps/nm dispersion
compensation DCU).

–See Table 75. for the relevant optical parameters
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 75. L–64.2b “Extended” characteristics

Application Code Unit L–64.2b Extended

Transmitter at Reference Point MPI–S/S’

Operating wavelength nm 1530 – 1565

Mean launch power:

– maximum dBm 13

– minimum dBm 10


Main optical path, MPI–S to MPI–R

Attenuation range

– maximum dB 28

– minimum dB 16

Max. chromatic dispersion ps/nm +2000

Passive dispersion conpensation By 20 DCU (400ps/nm)

Receiver at reference point MPI–R/R’

Minimum received power @ BER= 10–12

Minimum (sensitivity) dBm –18

Maximum (overload) dBm –3

(*) This application is based on the use of an external +10 dBm booster.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.8.3 Example of a link using 1660SM with L–64.2b “Reduced”

ÏÏÏÏÏ
1660SM
ÏÏÏÏÏ ÏÏÏÏÏÏ
1660SM
ÏÏÏÏÏÏ
L64.2b Port

L64.2b Port

ÏÏÏÏÏ
(Tx)
ÏÏÏÏÏ ÏÏÏÏÏÏ
ÏÏÏÏÏÏ(Rx)

MPI–S MPI–R

16 dBm

max+3 dBm
min 0 dBm min – 16 dBm

Figure 301. Example of a link using 1660SM with L–64.2b “Reduced”

Table 76. L–64.2b “Reduced” characteristics

Application Code Unit L–64.2b Reduced

Transmitter at Reference Point MPI–S/S’
Operating wavelength nm 1530 – 1565
Mean launch power:
– maximum dBm +3
– minimum dBm 0
Minimum extinction ratio (ER) dB 8.2
Main optical path, MPI–S to MPI–R
Attenuation range
– maximum dB 16
– minimum dB 0
Max. chromatic dispersion ps/nm + 1200
Maximum DGD ps 30
Minimum ORL at S dB 24
Receiver at reference point MPI–R/R’
Minimum received power @ BER= 10–12
Minimum (sensitivity) with fiber dBm –16
Maximum (overload) dBm +3
Maxim. reflectance between S and R dB – 27
Maximum optical path penalty n.a.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.9 Coarse WDM subsystem units characteristics

5.9.1 COADM–1 Channel

General Characteristics

Number of channels that can be add/drop per One channel among the following λ:
unit: 1470 nm, 1490 nm, 1510 nm, 1530 nm,
1550 nm, 1570 nm, 1590 nm, 1610 nm

Connector type MU horizontal

Pass–through Insertion Loss (dB) 2.1

Pass–through
ÂÂ
ÂÂ
ÂÂ ÂÂ
ÂÂ
ÂÂ
ÂÂ
ÂÂ
ÂÂ
ÂÂ
ÂÂ
ÂÂ
ÂÂ
ÂÂ
Â
ÂÂ Â
ÂÂ
Demux side specification

In–Drop Ch. Insertion Channels (nm)
In – Drop Ch.
Loss (dB)
ÂÂ
ÂÂ
ÂÂ
ÂÂ
1.25
1.25
1470 nm
1490 nm
CWDM line In
ÂÂ
ÂÂ
ÂÂ
ÂÂ 1.25 1510 nm
1.25 1530 nm
ÂÂ
ÂÂ
ÂÂ
ÂÂ 1.25 1550 nm
1.25 1570 nm
1.25 1590 nm
DROP Ch
Ch.
1.25 1610 nm
Mux side specificaton

Add Ch.– Out Insertion Channels (nm)
ADD Ch. –Out Loss (dB)

1.25 1470 nm
ÂÂ
ÂÂ
ÂÂ
ÂÂ CWDM Line OUT
1.25 1490 nm

ÂÂ
ÂÂ 1.25 1510 nm
ÂÂ
ÂÂ
ÂÂ
ÂÂ
1.25 1530 nm
1.25 1550 nm
Â
ÂÂ 1.25 1570 nm
1AA 00014 0004 (9007) A4 – ALICE 04.10

1.25 1590 nm
ADD Ch
Ch.
1.25 1610 nm

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5.9.2 COADM–2 Channels


Number of channels that can be add/drop per Two channels among the following λ:

unit: 1470 – 1490 nm
1510 – 1530 nm
1550 – 1570 nm
1590 – 1610 nm


Pass–through Insertion Loss (dB) 2.5

Pass–through

ÂÂ
ÂÂ
ÂÂ ÂÂÂ
ÂÂÂ
ÂÂÂ
ÂÂ
ÂÂ
Â
ÂÂ ÂÂÂ
ÂÂ
ÂÂÂ
ÂÂÂ
ÂÂ
Â

In – Drop Ch.
Loss (dB)
ÂÂÂ
Â
ÂÂÂ
ÂÂÂ
Â 1.55 1470 nm

CWDM line In 1.55 1490 nm
ÂÂÂ
ÂÂÂ
ÂÂÂ
ÂÂÂ 1.55 1510 nm

ÂÂ
ÂÂÂ 1.55 1530 nm
Â
ÂÂ 1.55 1550 nm
Â
ÂÂÂ 1.55 1570 nm
1.55 1590 nm
DROP Ch
Ch.
1.55 1610 nm


Â 1.55 1470 nm
ÂÂ
Â
ÂÂ
ÂÂ CWDM
CWDM Line OUT
1.55 1490 nm
1.55 1510 nm
ÂÂ
ÂÂ
ÂÂ
ÂÂ 1.55 1530 nm

ÂÂ 1.55 1550 nm
Â
ÂÂ 1.55 1570 nm
1AA 00014 0004 (9007) A4 – ALICE 04.10

1.55 1590 nm
ADD Ch
Ch.
1.55 1610 nm

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5.9.3 MUX/DEMUX 8 Channels


Channels number 8

Channels wavelenght 1470 nm, 1490 nm, 1510 nm, 1530 nm,
1550 nm, 1570 nm, 1590 nm, 1610 nm



In – Drop Ch.
Loss (dB)
ÂÂ
ÂÂ
ÂÂ 1.05 1470 nm

CWDM line In 3.15 1490 nm
ÂÂ
ÂÂ
ÂÂ
ÂÂ 2.85 1510 nm
2.55 1530 nm
ÂÂ
ÂÂ
ÂÂ
ÂÂ 2.25 1550 nm
1.95 1570 nm
1.65 1590 nm
DROP Ch
Ch.
1.35 1610 nm


1.05 1470 nm
ÂÂ
ÂÂ
ÂÂ
ÂÂ 1.35 1490 nm
CWDM Line OUT
ÂÂ
ÂÂ 1.65 1510 nm
ÂÂ
ÂÂ
ÂÂ
ÂÂ 1.95 1530 nm
2.25 1550 nm
Â
ÂÂ 2.55 1570 nm
2.85 1590 nm
ADD Ch
Ch.
3.15 1610 nm
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.9.4 2 Channels TRANSPONDER SFP without optical modulle


Optical interface characteristics: Refer to paragraph 5.9.5 on page 647

Optical module type: SFP (APD or PIN) plug–in module
Bit rate client side 2488.320 Mbps : STM–16 / OC–48
2500 Mbps: 2 Gbit Ethernet (not operative in current release)
2.667 Gbps: STM–16 w/FEC (not operative in current release)
2125.00 Mbps: 2 Fiber Channel (not operative in current release)
1250 Mbps: Gbit Ethernet (not operative in current release)
1062.5 Mbps: FICON (not operative in current release)
1062.5 Mbps: Fiber Channel (not operative in current release)
622.080 Mbps: STM–4/OC12 (not operative in current release)
270 Mbps: Digital Video (not operative in current release)
200 Mbps: Escon (not operative in current release)
155.520 Mbps: STM–1/OC3 (not operative in current release)
125 Mbps: Fast Ethernet (not operative in current release)
125 Mbps: FDDI (not operative in current release)

5.9.5 CWDM optical PLUGIN

SFP module type CWDM Silver CWDM Bronze
Detector type APD PIN
Addressed wavelength (nm) 1470,1490,1510,1530,1550,1570,1590,1610
Min. launched power (dBm) 0 0
Max launched power (dBm) 5 5
Allowed bitrates 125 Mbps to 2.7 Gbps 125 Mbps to 2.7 Gbps
Min. extinction ratio (dB) 8.2 8.2
Max. –20dB bandwidth (nm) 1 1
Minimum SMSR (dB) 30 30
Chromatic disp. (p
p (ps/nm)
) 1600 1610 nm (λ) 1000 1610 nm (λ)
1600 1590 nm (λ) 900 1590 nm (λ)
1500 1570 nm (λ) 900 1570 nm (λ)
1400 1550 nm (λ) 900 1550 nm (λ)
1400 1530 nm (λ) 800 1530 nm (λ)
1300 1510 nm (λ) 800 1510 nm (λ)
1200 1490 nm (λ) 700 1490 nm (λ)
1100 1470 nm (λ) 700 1470 nm (λ)
Minimum sensitivity (dBm) –28 –18
Minimum overload (dBm) –9 –3
Max optic. path penalty (dB) 2 1
1AA 00014 0004 (9007) A4 – ALICE 04.10

Max receiver reflect. (dB) –27 –27
Optical connector (Tx/Rx) LC LC

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SFP module type S–16.1 L–16.1 L–16.2

Addressed wavelength (nm) 1270–1360 1280–1335 1500–1580
Min. launched power (dBm) –5 –2 –2

Max launched power (dBm) 0 +2 +2
Allowed bitrates (Mbps) 2488320 2488320 2488320
Min. extinction ratio (dB) 8.2 8.2 8.2
Minimum sensitivity (dBm) –18 –27 –28
Minimum overload (dBm) –3 not available not available
Max receiver reflect. (dB) –27 –27 –27
Optical connector (Tx/Rx) LC LC LC
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.10 Power Supply characteristics

Input Voltage 48/60 Vdc 20%

Input current 25 A max

Power supply interface according to ETS 300132–2

5.10.1 Power consumption

The Alcatel 1660SM is designed for low power consumption. Developing new components with very high
integration density and low voltage supply leads to a significant reduction of power consumption.

Depending on the number and type of I/O ports the power consumption may vary in a wide range.

Some configurations figures are provided below:

• STM–64 node subtending 1xSTM–16 ring and 1 STM–4 ring with 189x2Mb/s tributaries: 500W

• STM–64 node subtending 2xSTM–16 rings with 16xGbE interfaces: 690W
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.11 Alarm Characteristics

Units Alarms:

Each port card or access card of the equipment is provided with a bicolor LED (green/red) on the front

coverplate.

This LED indicates:

– when red, internal failure
– when green, in service unit

ATM MATRIX Alarms:

All the alarm detected on the unit are related to the ATM traffic management; on the front are present
optical indication (LEDs) with the following meaning:

• Red LED (3): detection of an MAJOR or CRITICAL (URGENT) alarm
• Red LED (4): detection of a MINOR (NOT URGENT) alarm
• Yellow LED (5): alarm condition ATTENDED
• Yellow LED (6): detection of an ABNORMAL operative condition.
• Yellow LED (7): detection of an WARNING (INDICATIVE) alarm

Refer to Figure 43. on 132 where the front view of the unit and the led locations are illustrated.

Centralized Equipment Alarms:

All the alarms detected on the units (except ATM matrix board) are collected by the EQUICO unit which
will deliver centralized optical indications (by means of LEDs on its front coverplate). Specifically:

• Red LED (4): detection of an MAJOR (URGENT) alarm
• Red LED (5): detection of a MINOR (NOT URGENT) alarm
• Yellow LED (6): alarm condition ATTENDED
• Yellow LED (7): detection of an ABNORMAL operative condition. Type: active loopbacks,
forcing the unit into service, laser forced ON or OFF, try to restore after ALS
• Yellow LED (8): detection of an WARNING (INDICATIVE) alarm

Refer to para. 2.4 , page 123, where the front view of each unit and the LED locations are illustrated.

N.B. On the Craft Terminal (C.T.) and on the Operation System (O.S). application the URGENT
(URG), NOT URGENT (NURG) and INDICATIVE alarm are named in a different way; the
relation between this two terminology is explained in Table 77. on page 650.

Table 77. Relation between Alarm severity terminology displayed on C.T./O.S. and alarm severity
terminology used for the EQUICO leds and CONGI remote alarm connector pins.

Alarm severity terminology on C.T. and O.S. Alarm severity terminology used for EQUICO
leds and for CONGI remote alarm connector
pins

CRITICAL or MAJOR URG , T*URG, T*RURG,

MINOR NURG, , T*NURG, T*RNURG
1AA 00014 0004 (9007) A4 – ALICE 04.10

WARNING INDICATIVE

INDETERMINATE (not used) ––

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Rack lamps and Remote Alarms:

Some equipment alarms are carried to a connector, for customer applications, such as lighting–up of alarm
lamps (rack–lamps) or to drive a custom–alarms interface. Rack alarm and Remote Alarm are physically

available on the CONGI board connectors. The available alarms are the following:

Rack lamps alarms:

• T*RURG: urgent alarm (see Table 77. on page 650 for the C.T. terminology)
• T*RNURG: not urgent alarm (see Table 77. on page 650 for the C.T. terminology)
• T*RATTD: alarm storing
Remote alarms:
Remote alarms delivered by CONGI in slot 10:

• T*URG: detection of an urgent alarm (from Controller) (see Table 77. on page 650 for the C.T.
terminology)
• T*NURG: detection of a non–urgent alarm (from Controller) (see Table 77. on page 650 for
the C.T. terminology)
• T*INT: detection of an Internal alarm (from Controller)
• T*AND: loss of both battery station
• T*OR : fault or loss of one battery station

Remote alarms delivered by CONGI in slot 12:

• T*TORC: It indicates a loss of +3.3V generated by the on board DC/DC converter of one
• CONGI card.
• T*IND: Indeterminate alarm. It indicates synthesis of alarms not associated to the other severity
(not used)
• T*TUP: It indicates aN EQUICO microprocessor fault
• T*TANC: It indicates loss of + 3.3 V generated by the on board DC/DC converters of both
CONGI cards (it can be stored).
• LOSQ2 : It indicates loss of communication with the Mediation Device (not used).
1AA 00014 0004 (9007) A4 – ALICE 04.10

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HouseKeeping Alarms/Commands:

According to CONGI units settings two operative mode are available:

– 2 wires mode

Four output (CPO) and 12 input (CPI) contacts for house–keeping alarms or commands are available
on the CONGI board connector, for customer applications The available house–keeping contacts are
the following:

• HK–OUT 1 to 4: outgoing contacts
• HK–IN 1 to 12: Incoming contacts

– 3 wires mode:

Four output (CPO) and eight input (CPI) contacts for house–keeping alarms or commands are
available on the CONGI board connector, for customer applications The available house–keeping
contacts are the following:

• HK–OUT 1 to 4: outgoing contacts
• HK–IN 1 to 8: Incoming contacts

Alarm Attending:

The detected SDH units alarm condition can be stored through push–button (10) on the EQUICO unit
(Attended).
This operation will turn OFF the general red LED (4) and will light up the yellow LED (6) on the EQUICO
unit (Attended); The attended command is also sent to the rack lamps (if present) through the CONGI
board.

Trouble–shooting:

The 1660SM equipment has been designed to dialog with a Personal Computer (PC) in order to service,
activate and trouble–shoot the equipment.
Trouble–shoot procedure for the equipment and details of the alarms for each card and relevant
indications are described in the Operator’s Handbook.

Connection with the PC is achieved through connector (2) available on the EQUICO board.

The unit can be connected to an Operations System associated to the Transmission Management
Network in order to execute operations similar to those carried out by the PC.

Characteristics of the cited remote alarms and Housekeeping contacts interface (EM type) are inserted
in Chapter 5.1 on page 591.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.12 Mechanical characteristics

5.12.1 1660SM subrack without fans

Mechanical compatibility ETSI ETS/E3, S9

Equipment size 482 mm Wide x 650 mm High x 280 Deep

Subrack size 482 mm Wide x 650 mm High x 250 Deep

Board size 265 mm High x 213 mm Deep

Equipment weight 35 Kg

Cooling Fans in additional subrack

Rack cabling Vertical between rack and subrack front access

Electrical Connectors IEC 603/DIN 41612, IEC 807 (Sub–D)

IEC 169–1 (coax. 1.0/2.3), BNC 50 Ω, RJ45, RJ11

Back–to–back installation Yes

5.12.2 1660SM subrack with fans shelf



Subrack size 482 mm Wide x 750 mm High x 250 Deep

Board size 265 mm High x 213 mm Deep

Equipment weight 38 Kg

Cooling Integrated Fans

Rack cabling Vertical between rack and subrack front access

Electrical Connectors IEC 603/DIN 41612, EC 807 (Sub–D)

IEC 169–1 (coax. 1.0/2.3), BNC 50 Ω, RJ45, RJ11

Back–to–back installation Yes

5.12.3 Fans shelf 19”


1AA 00014 0004 (9007) A4 – ALICE 04.10

Equipment weight 6,1 Kg

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5.13 Environmental conditions

Main environmental aspects of Alcatel products are:

– energy consumption during manufacturing and use,

– materials harmfulness and recyclability,

– emissions to air, water or soil related to the manufacturing and the use of the product,

– electromagnetic (EM) emissions,

– value recovery at the product end of life.

5.13.1 Electromagnetic Compatibility (EMC) norms

The CE markings printed on the product denote compliancy with the following Directives:

• 89/336/EEC of May 3rd, 1989 (EMC directives), amended:

– by the 92/31/EEC Directive issued on April 28th, 1992

– by the 93/68/EEC Directive issued on July 22nd, 1993

Compliancy to the above Directives is declared, when the equipment is installed as for the manifacturer
handbooks, according to the following European Norms:

• EN 300 386 (V1.3.1), environment “Telecommunication Center”

WARNING

This is a class A product EN55022. In domestic, residential and light industry environments, this
product may cause radio interference in which case the user may be required to take adequate
measures.

5.13.1.1 Electromagnetic Compatibility (EMC) condition

For the EMC condition see also paragraph 3.1 on page 37.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.13.2 Waste from Electrical and Electronic Equipment (WEEE)

The marking printed on the subrack (refer to Figure 1. on page 41 and Table 12. on page 40)

denotes compliancy with the Directive 2002/96/EC On Waste of Electrical and Electronic Equipment.

The general principle is the producer responsibility in the management of the products he puts on the
market when discarded by the owner. The producer responsibility now covers the end of life of the products
sold.

The European directive is effective in a country once transposed. The starting date for the producer
responsibility for the European text is 13th August 2005.

All Alcatel products fall under in Category 3 of Annex 1A of the WEEE directive (Directive 2002/96/ EC)
i.e. ”IT and Telecommunication equipment” under item ”other products transmitting sound, images or other
information by telecommunications.”

Alcatel products fall under WEEE directive name: ”Other product or equipment of transmitting sound,
images or other information by telecommunications” in Annex 1B.

This mark will not cause any responsibility as all responsibilities will be defined by contract.

5.13.3 Acoustical noise

The acoustical noise level of the product complies with:

• ETS 300 753 Environmental Class 3.1 for attended telecommunication equipment rooms
(maximum sound level 7.2 bels)
1AA 00014 0004 (9007) A4 – ALICE 04.10

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5.13.4 Climatic for operating conditions

The Equipment meets the requirements of ETSI Standard with use of fans housed in an external subrack.
The functionality of the 1660SM Equipment, Vs. Temperature, is in compliance with :

ETS 300 019–1–3 :1992 , class 3.2.

Class 3.2: Partly temperature–controlled locations.
(see climatogram on Figure 302. on page 657)

5.13.4.1 Class 3.2: partly Temperature controlled locations

This applies to locations:

– where installed equipment may be exposed to solar radiation and heat radiation. They may also be
exposed to movements of the surrounding air due to draughts in buildings, e.g. through open
windows. They may be subjected to condensed water and to water from sources other than rain and
icing. They are not subjected to precipitation;

– where mould growth or attacks by animals, except termites, may occur;

– with normal levels of contaminants experienced in urban areas with industrial activities scattered
over the whole area and/or with heavy traffic;

– In close proximity to sources of sand or dust;

– with vibration of low significance, e.g. for products fastened to light supporting structures subjected
to negligible vibrations.

The conditions of this class may be found in :

– entrances and staircases of buildings;

– garages;

– cellars;

– certain workshops;

– buildings in factories and industrial process plants;

– unattended equipment stations;

– certain telecommunication buildings;

– ordinary storage rooms for frost resistant products and farm buildings, ect.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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03
5

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Figure 302. Climatogram for Class 3.2 : Partly temperature controlled locations
95
29

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5.13.5 Storage

The 1660SM equipment meet the following requirements Vs. Storage :

ETS 300 019–1–1 : 1992, class 1.2

Class 1.2 : weatherprotected, not temper. controlled storage location.

This class applies to weatherprotected storage having neither temperature nor humidity control. The
location may have openings directly to the open air, i.e., it may be only partly weatherproofed. The
climatogram is shown on Figure 303. on page 659.

This class applies to storage locations :

– where equipment may be exposed to solar radiation and temporarily to heat radiation: They may also
be exposed to movements of the surrounding air due to draughts, e.g. through doors, windows or
other openings. They may be subjected to condensed water, dripping water and to icing. They may
also be subjected to limited wind–driven precipitation including snow;

– where mould growth or attacks by animals, except termites, may occur;

– with normal levels of contaminants experienced in urban areas with industrial activities scattered
over the whole area, ad/or with heavy traffic;

– in areas with sources of sand or dust, including urban areas;

– with vibration of low significance and insignificant shock.

The conditions of this class may occur in :

– unattended buildings ;

– some entrances of buildings ;

– some garages and shacks.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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1AA 00014 0004 (9007) A4 – ALICE 04.10

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Figure 303. Climatogram for Class 1.2: not temperature controlled storage location
29

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5.13.6 Transportation

The 1660SM equipment meets the following requirements Vs. transportation :

ETS 300 019–1–2 : 1992, class 2.2

Class 2.2 : Careful transportation (see Table 78. on page 661 ).

This class applies to transportation where special cars has been taken e.g. with respect to low temperature
and handling.

Class 2.2 covers the condition of class 2.1. In addition class 2.2 includes transportation in all types of lorries
and trailers in areas with well–developed road system.

It also includes transportation by ship and by train specially designed, shock–reducing buffers. Manual
loading and unloading of to 20 Kg is included.

Extension of extreme low temperature during transportation is permitted for the 1660SM equipment in its
standard packing :

AT –40° C for 72 Hours maximum

without damaging the Optical interfaces.
1AA 00014 0004 (9007) A4 – ALICE 04.10

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Table 78. Transportation climatic

Environmental parameter Unit 2.1 and 2.2 2.3

(A) low temperature air °C – 25 – 40

high temperature, air in unventilated
(B) °C + 70 + 70
enclosures (NOTE 1)

high temperature, air in ventilated enclosures
(C) °C + 40 + 40
or outdoor air (NOTE 2)

(D) change of temperature air/air (NOTE 3) °C –25 / +30 –40 / +30

(E) change of temperature air/water (NOTE 3) °C +40 / +5 +40 / +5

relative humidity, not combined with rapid % 95 95
(F)
temperature changes °C +40 +45

relative humidity, combined with rapid % 95 95
(G) temperature changes air/air, at high relative
humidity (NOTE 3 , 6) °C –25 / +30 –40 / +30

absolute humidity, combined with rapid g/m3 60 60
(H) temperature changes : air/air at high water
content (NOTE 4) °C +70 / +15 +70 / +15

(I) low air pressure KPa 70 70

(J) change of air pressure KPa/min no no

(K) movement of the surrounding medium, air m/s 20 20

(L) precipitation rain mm/min 6 (NOTE 7) 6

(M) radiation, solar W/m2 1120 1120

(N) radiation, heat W/m2 600 600

(O) water from sources other than rain (NOTE 5) m/s 1 (NOTE 7) 1

(P) wetness none conditions of wet surfaces

Notes on next page.
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Notes to Table 78. :

NOTE 1 : The high temperature of the surfaces of a product may be influenced by both the
surrounding air temperature, given here, and the solar radiation through a window or

another opening.

NOTE 2 : The high temperature of the surface of a product is influenced by the surrounding air
temperature, given here, and the solar radiation defined below.

NOTE 3 : A direct transfer of the product between the two given temperature is presumed.

NOTE 4 : The product is assumed to be subjected to a rapid decrease of temperature only (no
rapid increase). The figures of water content apply to temperatures down to the
dew–point; at lower temperatures the relative humidity is assumed to be approximately
100 %.

NOTE 5 : The figure indicates the velocity of water and not the height of water accumulated.

NOTE 6 : Occurrence of condensation.

NOTE 7 : For short duration only.
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6 MAINTENANCE

ATTENTION EMC NORMS

WHEN CARRYING OUT THE GIVEN OPERATIONS OBSERVE THE NORMS STATED IN PARA.
3.1.3 ON PAGE 38

6.1 General safety rules

SAFETY RULES

Carefully observe the front–panel warning labels prior to working on optical
connections while the equipment is in–service.

Should it be necessary to cut off power during the maintenance phase, proceed
to switch off the power supply units as well as cut off power station upstream
(rack or station distribution frame)

SAFETY RULES

A TNV–2 (battery) voltage could be present on “R/M interface connector” (cable
side); do not touch the pins when unplugged .

DANGER: Possibility of personal injury. Short circuiting, low-voltage,
low-impedance, dc circuits can cause severe arcing that can result in burns
and/or eye damage. Remove rings, watches, and other metal jewelry before
working with primary circuits. Exercise caution to avoid shorting power input
terminals.

SAFETY RULES

DANGER: Possibility of eyes damage: read carefully and strictly observe the
rules pointed out in para.2.2.4.2 on page 33.
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6.2 General rules

• Check that the equipment is operating with all the shields properly positioned (dummy covers,
ESD connector protections, etc)

• In order to reduce the risk of damage the electrostatic sensitive devices, is mandatory to use
the elasticized band (around the wrist) and the coiled cord joined connect with the ground rack
during the touching of the equipment

6.3 Maintenance Aspects

Maintenance consists of a set of operations which maintain or bring back the assembly to optimum
operating conditions in a very short time, with the aim of obtaining maximum operational availability.

Maintenance is classified as:

• ROUTINE

• CORRECTIVE

6.4 Instruments And Accessories

There is a local terminal (PC) which permits to display all the alarms and manages the Equipment.
The relative processing is described in the operator’s handbook.

Where TMN is implemented, an Operation System displays alarms and manages all the connected
Equipments of the network. Refer to the relevant handbooks.

The need of special tools and accessories to perform possible routine and corrective maintenance
procedures is described inside the procedures themselves.
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6.5 Routine Maintenance

Routine maintenance is a periodic set of measurements and checks. This maintenance discovers those
devices whose function has deteriorated with time and therefore need adjustment or replacement.

Typically, digital equipment requires no routine maintenance.

The equipment allows to assess the quality of the connection links for SECTION and PATH o counting the
errored events and obtaining performance data.

The Performance Monitoring Application, described in the Operator’s Handbook, allows this function.

6.5.1 Routine maintenance every three months

According to the filter type It is suggested to carry out the following operations every three months:

– Metallic filter cleaning

– Dust filter substitution

6.5.1.1 Metallic filter cleaning

Metallic Filter cleaning


WARNING: BEFORE INSTALLING OR REMOVING THE METALLIC FILTER , CHECK
THAT THE PROTECTIVE ADHESIVE FILM HAS BEEN REMOVED.

SAFETY RULES

DANGER: Possibility of personal injury. Personal injury can be caused by
rotating fans.

• Replace the “Metallic filter” from the “FANS Shelf” or from the “Mechanical
Structure with Integrated Fans” as follow :

– unscrew the screws that ensure the Metallic filter to the shelf
– extract the Metallic filter
– clean the metallic filter removing the dust
– Insert and ensure the “Metallic filter” to the shelf using the relevant
screw

Note: the period of one three months is only indicative; according to the environmental conditions could
be necessary to reduce this period.
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6.5.1.2 Dust filter substitution

Dust Filter SUBSTITUTION


WARNING: BEFORE INSTALLING OR REMOVING THE DUST FILTER , CHECK THAT
THE PROTECTIVE ADHESIVE FILM HAS BEEN REMOVED.

SAFETY RULES

rotating fans.

• Replace the “Dust filter” from the “FANS Shelf” or from the “Mechanical
Structure with Integrated Fans” as follow :
– unscrew the screws that ensure the dust filter to the shelf
– extract the Dust filter
– insert the new Dust filter
– ensure the “Dust filter” to the shelf using the relevant screw

Note: It is suggested to replace the filter every 3 months; this period is indicative and must be verified
according to the environmental conditions.
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6.5.2 Routine maintenance every year

It is suggested to carry out the following operations yearly:

•

power cables check

6.5.2.1 Power cables check

SAFETY RULES

–48 V dc.

terminals.

Make these operations:

• Check that the power cable is perfectly safety grounded.

• Make sure that the subrack has been tightly fastened to the rack with screws, to guarantee
grounding (the rack is connected to the station ground).

Note: the period of one year is only indicative; according to the environmental conditions could be
necessary to reduce this period.

6.5.3 Routine Maintenance every five year

It is suggested the replacement of each FANS UNIT equipped in the Fans Subrack or in the “Mechanical
Structure with Integrated Fans” after five years of working.

For the substitution refer to the sequences shown in paragraph 6.6.1 on page 670.
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6.6 Corrective Maintenance (Trouble/Shooting)

Since the Troubleshooting procedure is carried out with the use of the Craft Terminal , please refer ,for
details, to the Maintenance Section of the Operator’s Handbook.

FIXING THE UNITS (AND MODULES) INTO THE SUBRACK

The screw tightening torque for fixing the units (and modules, if any and if fixed by screws) into
the subrack must be:

2.8 kg x cm (0.28 Newton x m) 10 %
Exceeding this value may result in screw breaking.

6.6.1 Fan unit substitution

SAFETY RULES

–48 V dc.

terminals.

When an ALM_URG alarm is displayed on C.T or O.S. ( associated to an Housekeeping alarm) it means
that at least one fan is broken, so it is necessary to replace the “FAN unit” involved.
These alarm indications are also displayed on the Fans front panel.

– with the “FANS Shelf”

• unscrew the screws that ensure the Fan unit to the fans shelf
• extract the Fan unit from the Fan shelf by means the extractors kit, using the central hole under
the led
• insert the new Fan unit into the Fan shelf
• ensure the Fan unit to the “FAN shelf“ using the relevant screw

– with the “Mechanical Structure with Integrated Fans”

• unscrew the screws that ensure the Fan unit to the fans shelf
• extract the Fan unit from the shelf by means the two card lever
• insert the new Fan unit into the Fan shelf
• ensure the Fan unit to the “FAN shelf“ using the relevant screw
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6.7 Set of spare parts

6.7.1 Suggested Spare Parts

The overall number of spares depends on Customer requirements, and should be based on the average
amount of transmission circuits available to be accounted for not only during MTBF but also during MTTR;
the latter depending on the amount of spare parts available.
The set of spare parts is inclusive of a minimum number of spares for each type of replaceable plug–in
unit (see unit list in Chapter 2 on page 83).

6.7.2 General rules on spare parts management

Before storing the spare units make sure that they are working by inserting them in an operating equipment
It is suggested to periodically check those spare units have not been utilized for over a year.
If the spare parts and the equipment are stored in the same environment, make sure that the spare parts
are placed in cabinets to safeguard them from dust and damp.
Moreover, they should also be well grounded to avoid electrostatic discharges.

If the spare parts are stored in another room, or have to be moved from another place, building or site,
make sure that the following is observed:

– the spare parts must be wrapped in anti–static and padded envelopes;

– the spare parts must not touch wet surfaces or chemical agents that might damage them (e.g.
, gas);

– if during transport the temperature is lower than that of the room where they had been kept, make
sure that before using them they pass a certain period in a climatic chamber to prevent thermal
shocks and/or the possibility of steaming up.

When replacing a unit/sub–unit, make sure that the spare unit/sub–unit is set exactly as the
replaced one. For the presettings procedures see section HARDWARE SETTING
DOCUMENTATION.

6.7.3 Particular rules on spare parts management

Whenever some units with flash-memories are common to different kinds of equipment or to different
versions of the same type of equipment, it is possible to maintain one spare part only: this allows spare
part stock saving, even though software downloading will be necessary when the software loaded into the
unit (program part or data part) is different from that necessary in the equipment where the spare unit must
be used.
At the end of the commissioning phase or after an equipment data change, it is suggested to save the
equipment data, e.g. on floppy disk, and store this floppy disk in the spare part stock pointing out the
equipment it refers to.

6.8 Repair Form

To facilitate operation, data on the faulty unit must be reported on the form shown in Figure 304. on page
672.
1AA 00014 0004 (9007) A4 – ALICE 04.10

The repair form must be filled–in with as much data as possible and returned to ALCATEL together with
the faulty unit.

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ALCATE L
REPAIR FORM
Fill in this form and affix it to the faulty unit to be returned to Alcatel

CUSTOMER NAME ORDER NUMBER/CONTRACT NUMBER

SITE BRANCH/UNIT/COUNTRY

SYSTEM/EQUIPMENT PRODUCT RELEASE EQUIPMENT SOFTWARE PART NUMBER

STATION/RACK SUBRACK SLOT
TO BE FILLED IN BY THE SENDER

MNEMONIC ALCATEL PART NUMBER

SERIAL NUMBER FAULTY UNIT SOFTWARE VERSION

FAULT PHASE REASON FOR REPAIR PRESUMED CAUSE

INSTALLATION / CLEAR FAULT DROP IN PERFORMANCE INTERNAL
TURN ON

LIGHTNING
OPERATION INTERMITTENT FAULT UPGRADE/QUALITY ALERT
EXTERNAL AIR COND.

MAINTENANCE TEMPERATURE FAULT OTHER

DATE NAME OF SENDER
FAULT STILL PRESENT
AFTER REPAIR

COMMENTS

PROCESSING FAULTS DETECTED
TO BE FILLED IN BY THE REPAIR OPERATOR

NO FAULTS FOUND UPGRADE SOLDERING / COMPONENT ADJUSTMENT
WIRING
A I C F–L P

STANDARD REPAIRING NOT REPAIRABLE MECHANICAL PRINTED DIRT
(REJECTED) CIRCUIT BOARD
B–D M V1 V1 V2
SUBSTITUTED
QUALITY ALERT CORROSION OTHER
I S–X V3
NOTE : LETTERS ARE FOR FACTORY USE

COMMENTS

DATE REPAIRING NUMBER REPAIRING CENTRE NAME OF REPAIR OPERATOR
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Figure 304. Repair form

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7 DISMANTLING RECYCLING

7.1 WEEE general information

According to the European directive (2002/96/EC) Waste Electric and Electronic Equipment, from August
13th 2005 the ”producer” of the equipment being sold, unless otherwise specified in the contract with the
Customer, is resposible for collecting and treating Electrical and Electronic Equipment.

Equipment put on the market after August 13th 2005 have a label (refer to paragraph 3.4 on page 40)
affixed on the product. The presence of the black label indicates the product has been put on the market
after after August 13th 2005.

In next paragraphs is given a description example of how to disassemble an equipment; the same principle
can be applied to all the subracks and units composing the equipment.

The unit chosen for disassembly is one of the most complex.

– Paragraph 7.2 describes the equipment disassembly; in detail:

• paragraph 7.2.1 on page 676 lists the tools necessary for disassembly

• paragraph 7.2.2 on page 677 describes the subrack disassembly

• paragraph 7.2.3 on page 684 describes the unit disassembly

• paragraph 7.2.4 on page 694 describes the procedure to apply in order to manage Hazardous
materials and components (example battery)

– Paragraph 7.3 on page 696 reports the ECO declaration info.
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7.2 How to disassembly equipment

This equipment is designed for easy disassembly, by using screws and rivets for mechanical assembly
of subracks and modules. The variety of screw types is minimized.

Tools necessary for subrack and units disassembly are reported in paragraph 7.2.1.

The disassembly process depends on the respective recycling methods and can be derived from the
delivered assembly instructions of the product.

These guidelinesare not mandatory.
They are given in order to optimize the disassembling process and material recovery as whole.

7.2.1 Tools necessary for disassembly

The following tools are necessary for unit disassembly:

– # T9 TORX screw driver

– # T20 TORX screw driver

– Crosshead screwdriver

– Wrench #

– Scissors

– Protection gloves
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7.2.2 Subrack disassembly

In Figure 305. on page 677 is shown an example of subrack.

The same rules can be applied to the specific equipment to be dismantled.

In order to disassemble the subrack first remove the boards eventually present, included termination bus.

SUBRACK FRONT VIEW SUBRACK REAR VIEW

Figure 305. Subrack front and rear view
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Procedure:

– Remove the two screws (A) in order to disassemble the handle as reported in Figure 306. on page
678.

– Repeat the same procedure on the other handle.

– Separate the two plastic blocks of the handle as reported in Figure 306. on page 678.

A

A

plastic block

plastic block

Figure 306. Handle removing and disassembly
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– Unscrew all the screws present on rear cover as reported in Figure 307. (dashed lines) on page 679.

– Remove the rear cover in order to access the subrack Back Panel.

Figure 307. Rear cover removing
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– Unscrew all the screws fastening the Back Panel to the mechanical structure of the subrack as
indicated in Figure 308. on page 680 (dashed line).

– Remove the Back Panel from the subrack mechanical structure.

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Figure 308. Back Panel removing

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– Remove the upper and lower guides from the subrack access area by unscrewing the relevant
screws as indicated in Figure 309. on page 681.

Upper and Lower guides
ACCESS AREA

BASIC AREA
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Figure 309. Upper and lower guides plane removing

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– Remove the side wall by unscrewing the relevant screw as indicated in Figure 310. on page 682.

– Remove the two contact springs from the side wall as indicated in Figure 311. on page 683 (refer to
paragraph 7.2.4 on page 694 for info about hazardous parts dismantling).

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Figure 310. Side wall removing

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– Remove the two guides of the “basic area” and the two optical fiber ducts by pulling them out as
indicated in Figure 311. on page 683.

– Unscrew all the screws present on the other “side wall” in order to complete the subrack disassembly.

Optical fiber duct

Optical fiber duct

guides guides

contact spring

contact spring
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Figure 311. Optical fiber duct, guides and contact spring removing

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7.2.3 Unit disassembly

Procedure:

– Remove twe two screws (A) from the side coverplate as indicated in Figure 312. on page 684.

A

A

Figure 312. Side coverplate removal

– Remove the screws (B) that fix the two levers and subsequently pull out them from the front plate
as indicated in Figure 313. on page 685.
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B

B

Figure 313. Levers removal
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– Unscrew and extract the two optical connectors (C) as indicated Figure 314. on page 686.

– Remove the screw (D) fixing the connectors support as indicated in Figure 314. on page 686.

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C
D

Figure 314. Optical connectors support removal

706
E

3AL 91669 AA AA
Rotate the connectors support (E) and pull it sidely to be removed as indicated Figure 314. on page

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– Remove the two screws (F) from the side coverplate as indicated in Figure 315. on page 687.

– Extract from the top the contact spring (G) as indicated in Figure 315. on page 687 (refer to
paragraph 7.2.4 on page 694 for info about hazardous parts dismantling).

– Extract the fibers from the cavity (H) as indicated in Figure 315. on page 687.

F
G

F

H
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Figure 315. Side coverplate and contact spring removal

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– Disconnect the two flat cables (M) as indicated in Figure 316. on page 688.

– Unscrew (L) connectors with the aid of a wrench as indicated Figure 316. on page 688.

– Remove the fibers (N) from supports pulling them out Figure 316. on page 688.

– Remove the two screws (O) on the other side of the board that fixes the dissipator to the Printed
Circuit Board (PCB) as indicated in Figure 317. on page 689.

– The dissipator can now be removed (refer to Figure 318. on page 690).

L L L L L

M L

M

N
N
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Figure 316. Internal connectors removal

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O

Figure 317. Dissipator removal

– Remove the screws (P) from dissipator as indicated in Figure 318. on page 690.

– Now the two modules on the other side of the dissipator are free to be removed (refer to Figure 320.
on page 691);

Pay attention during modules removal because of white conductive paste (refer to paragraph
7.2.4 on page 694 for info about hazardous parts dismantling).

– Remove the plastic part (X) in Figure 319. on page 690 by unscrewing the screw present on the rear
side of the dissipator.
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P P

P
P

P
P P
P

Figure 318. Modules removal from dissipator

– Remove the screws (Q) and (R) that fix the daugther board and pull it out from the mother board (refer
to Figure 319. on page 690).

MOTHER BOARD R

DAUGHTER BOARD

Q
Q

R

X
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Figure 319. Daughter boad removal

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– Cutaway golded connector (S) from daughter board (refer to Figure 320. on page 691)

S

Figure 320. Gold connector removal

– Remove all internal cables as indicated in Figure 321. on page 692. To remove cables it is enough
to pull them out from their support.
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Figure 321. Internal cables removal

– Remove screws (T) that fix the metal support to the mother board as indicated in Figure 322. on page
693.

– Remove the metal support.

– Cutaway the golded connector (U) from mother board.
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T

T
T

Metal support

Figure 322. Connector metal support removal

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7.2.4 Hazardous materials and components

Table 79. on page 694 lists the presence or not of hazardous substance/components.

Note: The system cabling is designed for reduced halogen content. All the traffic cabling is fully PVC free.

Table 79. List of hazardous materials and components present in the equipment

Materials/substances Presence Where
in the
equipment

Batteries External NO
(Mercury/NiCad/Lithium/Other)

Batteries Internal NO
(Mercury/NiCad/Lithium/Other)

Mercury NO

Cadmium NO

Capacitors with PCB’s

Capacitors with substances of concern + NO
height 25 mm, diameter 25 mm or pro-
portionately similar volume

Gas discharge lamps NO

Mercury containing Backlighting lamps NO

Plastic containing brominated flame retar- NO
dants other than in Printed Circuit Assem-
blies

Liquid Crystal Displays with a surface NO
greater than 100 cm2

Asbestos NO

Refractory ceramic fibres NO

Thermal conductive paste YES In all units where dissipators are present a
withe thermal conductive paste is used in
between mechanical parts.
In Figure 319. on page 690 an example is
shown.
Note: protective plastic gloves must be
used in order to avoid contact between
hands and thermal conductive paste.
Pay attention to avoid contact of thermal
conductive paste with eyes.

Radio–active substances NO
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Beryllium Oxide NO

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Materials/substances Presence Where
in the
equipment

Other forms of Beryllium YES Refer to Figure 311. on page 683 and
Figure 315. on page 687 point G.
Note: Copper–beryllium contact spring
must be separated from other material and
must be fused in a specific regulated envi-
ronment.

Pressure volume NO

Liquids Volume NO

Gasses Volume NO

”Hidden” mechanical springs or other NO
equivalent parts

Ozone depleting substances, according to NO
those categories that are already banned
in the Montreal protocol

Chloroparaffins with chain length 10–13 C NO
atoms, chlorination greater than 50% con-
tained in mechanical plastic parts heavier
than 25g,

Lead contained in mechanical parts heavi- NO
er than 25g,

Polychlorinated biphenyls (PCB) or po- NO
lychlorinated terphenyls (PCT),

Polybrominated biphenyl’s and their NO
ethers (CAS no. 32534–81–9, CAS no.
32536–52–0, CAS no 1163–19–5, CAS
no. 13654–09–6) contained in mechanical
parts heavier than 25g, in concentrations
exceeding the natural background levels.
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7.3 Eco declaration

1660SM is an STM–1/4/16/64 MultiService Node for transmission and cross–connection of a wide range
of traditional PDH and SDH signals as well as packed based data flows. It can operate as a multi Terminal

or Add/Drop Multiplexer. Moreover the system can be configured as a small cross–connect with a matrix

size of up to 384x384 STM–1 equivalent at the Hight Order VC level and 256x256 STM–1 equivalent at
the Low Order VC level.

New STM–64 Long Haul optical interfaces with external booster are provided in this SW release.

Key features

Refer to paragraph 5.1 on page 591 “General Characteristics”

Weight and Dimensional Characteristics

Refer to paragraph 5.12 on page 653

EXTENSION OF SYSTEM LIFETIME

The product is designed to ensure an outstanding quality of services through very high traffic transmission,
connection and protection performances and minimum service interruption.

The life utility is at least 5 years. This means that maintenance will be assured for at least 5 years.

The system architecture facilitates future extensibility and upgradability:

• On–site configuration changes as for example the extension of the node traffic capacity without
re–cabling of interconnections.

• Implementation of new features and functionalities by remote Software download.

The terms and conditions of warranty, service availability and spare parts availability are individually
agreed between Alcatel and the Customer and are part of the relevant contractual commitments.

POWER CONSUMPTION

Refer to paragraph 5.10.1 on page 649.

RADIO FREQUENCY EMISSION

Regarding compliance with radio frequency emission requirements refer to paragraph 5.13.1 on page
654.
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ACOUSTICAL NOISE

Refer to paragraph 5.13.3 on page 655

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MATERIALS

Refer to Table 79. on page 694 for details.

DISASSEMBLY

Refer to paragraph 7.2 on page 676.

BATTERIES

The product requires no backup batteries.

PACKAGING

The packaging of this Alcatel equiment complies with the directive 94/62/EEC concerning packaging and
packaging waste. Depending on the means of transportatio,n the racks are packed in a cardboard or
wooden box, which can easily be recycled after use. Environmentally harmful materials are not used for
packaging. The packaging materials are marked according to ISO 11 469. If required by the Customer and
agreed by both parties, Alcatel can take care of the proper disposal of all packaging materials.

For details refer to” Installation Handbook”.

TAKE BACK INFORMATION

On request of customers, Alcatel can take care of the take back of depreciated equipment and of the
ecological safe and appropriate disposal under conditions to be agreed.

For that purpose Alcatel co–operates with qualified companies.

DOCUMENTATION

In order to reduce paper consumption for Customer Documentation, Alcatel delivers the Generic
Customer Documentation on a CD–ROM. The CD–ROM contains interactive HW Descriptions, SW
Descriptions, Functional Descriptions, Maintenance Manuals and User Guides. This allows the operator
to put the documentation on a server accessible by all relevant people in the organization without any
additional paper copies.
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HARDWARE SETTING DOCUMENTATION

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UNITS DOCUMENTATION LIST

This section contains the documents sheets to refer to for unit/sub–unit hardware setting options. The list
of the enclosed documents is given in Table 81. on page 704, according to the ANV part number.

TABLE EXPLANATION:

– UNIT IDENTIFICATION P/Ns AND CHANGE STATUS

Each unit or sub-unit is distinguished by:

• a dual Part No.:

– Factory P/N (4xx.xxx.xxx x)

– ANV P/N (xxx.xxxxx xx) (NOTE)

NOTE The last two ANV-P/N letters (in the following stated as ’suffix’) stand for a ”feasible
alternative”, they might differentiate two units eventhough still functionally
compatible. For this reason the indicated ANV P/N does not include the last two
letters.
For example : the units having P/Ns ”3AL–34065–AAAA” and ”3AL–34065–AABA”
are functionally compatible and, as regards to hardware settings, the MSxxx
document (described hereafter) 3AL–34065–AAAA-MSxxx is applicable for both.

• and by a pair of design production series (change status):

– CS, associated to the Factory P/N (4xx.xxx.xxx x)

– ICS, associated to ANV P/N (xxx.xxxxx xx)

The following table shows an example of correspondence between ”FACTORY P/N + CS” and
”ANV P/N + ICS”

Table 80. Example of correspondence between CS and ’suffix + ICS’

N.B. The P/Ns used in this example have no correspondence with those of the actual equipment part
list!

FACTORY CODE ANV CODE

P/N CS P/N ICS

487.156.612 01 3AL 34422 AA AA 01

487.156.612 02 3AL 34422 AA AB 01

487.156.612 03 3AL 34422 AA AC 01

In this example you can see that the production series is identified only by the CS as far as the
Factory code is concerned, and by the ’suffix + ICS’ if the ANV code is referred to.

Some of the possible positions of the label indicating the unit’s P/Ns and CS–ICS are illustrated
1AA 00014 0004 (9007) A4 – ALICE 04.10

in para. 3.4 on page 40.

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– CROSS–REFERENCE

• Id. Unit alphabetical notation. It indicates the unit containing one or more subunits.
• App. It reports the unit notation (Id) to which the sub–unit belongs.

The HARDWARE SETTINGS can be executed after having checked all the sub–units belonging to
a unit, by considering the above cited cross–reference, and by using the presetting documents
indicated in Table 81. page 704 and presented in the following point.

– ENCLOSED DOCUMENTS
For each type of unit or sub-unit having customizing setting options, the document
”ANV P/N”–MSxxx
is annexed to this handbook (in the case of Documentation on CD-ROM the MSxxx documents may
be given in a CD-ROM different from that containing this Technical Handbook).

The MSxxx documents are enclosed in numerical order. The Edition of the enclosed MSxxx
document is the highest available on the date on which the Technical Handbook is assembled.
Use of the document MSxxx:
• MSxxx means ”document for hardware presetting options” (the MSxxx document’s Part No.
is as that of the unit or sub-unit and its MS acronym defines type).
The xxx part of MSxxx is relevant to ANV internal identification codes.
• As the Customer may have to manage many units of the same type (same P/N) but with different
CS–ICS, the document MSxxx describes with possible different chapters the different setting
options, according to all the possible CSs–ICSs. For this purpose, a table at the beginning of
document (PREFACE) indicates the chapter to be used according to the CS or the
corresponding ’suffix + ICS’, taking into account that:
– a change of the production series does not necessarily imply a change in the setting
options;
a change of the ANV P/N suffix does not imply a new MSxxx document;
– the CS, SUFFIX and ICS must be meant as:
• from specified CS, SUFFIX or ICS (included)
• to next CS, SUFFIX or ICS (excluded) if listed
– the sequence of CSs is increasing from alphanumeric to numeric (e.g. CS=A0 is lower
than CS=01).
Each chapter contains:
– one or more tables defining the relationship between the functions achievable and the
setting options to make;
– the unit layout drawing which shows the exact location of all the setting options.

N.B. IDENTIFIES PIN 1 OF COMPONENT

N.B. When necessary to make ”TC” Hardware Settings fitted on the rear side of the
board, remove the protective cover plate present on the same rear side and
replace it at the end of the operation
The setting options described in the documents MSxxx must be used according to
3AL377470001 (962.000.022 F) MSxxx document, inserted in Table 81. on page 704, which
shows the ’ON’ (closed) position of microswitches.
1AA 00014 0004 (9007) A4 – ALICE 04.10

Those setting options that on the table are indicated by the caption For factory use only should
never be modified.

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EXAMPLE

N.B. The P/Ns used in this example have no correspondence with those of the actual equipment part
list!

Taking into account the same unit of Table 80. on page 701:


P/N CS P/N ICS

487.156.612 01 3AL 34422 AAAA 01

487.156.612 02 3AL 34422 AAAB 01

487.156.612 03 3AL 34422 AAAC 01

and supposing that the setting options valid for CS=01 are equal to those for CS=02, but change
for CS=03, the table at the beginning of the document 3AL 34422 AAAA MSZZQ will be:

FACTORY P/N ANV P/N
CODICE DI FABBRICA CODICE ANV
CHAPTER
CAPITOLO FROM CS FROM SUFFIX FROM ICS
DA CS DA SUFFISSO DA ICS

1 01 ––AA 01

2 03 ––AC 01

If you have the unit identified by one of this identification data:


P/N CS P/N ICS

487.156.612 01 3AL 34422 AAAA 01

487.156.612 02 3AL 34422 AAAB 01

you will use Chapter 1 of document 3AL 34422 AAAA MSZZQ

If you have the unit identified by one of this identification data:


P/N CS P/N ICS

487.156.612 03 3AL 34422 AAAC 01
1AA 00014 0004 (9007) A4 – ALICE 04.10

487.156.612 04 3AL 34422 AAAD 01

you will use Chapter 2 of document 3AL 34422 AAAA MSZZQ

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Table 81. Hardware presetting documentation

The edition of the documents (listed in this table) that are physically enclosed in the handbook is
the highest available when this handbook is assembled. The edition of enclosed documents is

not specified in this table.

Document
ANV P/N
Id NAME App for hardware
(Factory P/N)
presetting
3AL 78830 AD–– 3AL 78830 AAAG
a Control and general interface
MSZZQ
3AL 78836AA––
b EQUICO E
(411.102506 Z)
3AL 81277AA–– 3AL 81277 AAAA
PQ2 Equipment controller b
(487.151.011) MSZZQ
3AL 79093 AA––
c ATM MATRIX 4x4 –
(411.101.035 J)
3AL89917 AA––
d ATM MATRIX D3 –
––.––.––
3AL 81185 AA––
e ATM MATRIX 4x4 ENHANCED –
(411.102.475 Z)
3AL79094 AA––
f ATM MATRIX 8x8 –
(411.101.036 K)
3AL 79631 AA––
g PR_EA MATRIX 4XETH –
(411.101.281 W)
3AL 79752 AA––
h PR_EA MATRIX 1XSTM1 Plug in –
(411.101.407 V)
3AL 81275 AA––
i PR_EA MATRIX 1XGB–ETH –
(411.102.505 Y)
j ISA–ES1 8FE BOARD 3AL 98128 AA–– –
k ISA–ES1 8FX BOARD (SFP) 3AL98150AA–– –
l ISA–ES4 8FE + 1GE BOARD 3AL 81879AA–– –
m ISA–ES16 BOARD 3AL 81915 AA–– –
3AL 37747 0001 3AL 37747 0001
Microswitches ”ON” position
(962.000.022 F) MSZZQ

3AL 79202 AA–– 3AL 79202 AAAA
ATM MATRIX 8x8 f
(487.156.804 W) MSZZQ

3AL 79425 AA–– 3AL 79425 AAAA
NETWORK PROCESSOR 2 g, h, i
(483.100.252 ) MSZZQ
3AL 80481 AA–– 3AL 80481 AAAA
ATM MATRIX 4x4 c
(487.156.138 Z) MSZZQ
1AA 00014 0004 (9007) A4 – ALICE 04.10

3AL 81183 AA–– 3AL 81183 AAAA
ATM MATRIX 4x4 ENHANCED e, d
(487.156.274) MSZZQ

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Document
ANV P/N
Id NAME App for hardware
(Factory P/N)
presetting

3AL81878AAAA

L2 ETHERNET PORT BOARD l 3AL81878AA––
MSZZQ
3AL81916AAAA
PBA–ISA–PREA V2 m 3AL81916AA––
MSZZQ
3AL98127AAAA
PBA–ISA FE V2–155 j 3AL98127AA––
MSZZQ
3AL98149AAAA
PBA–ES1–8FX k 3AL98149AA––
MSZZQ
1AA 00014 0004 (9007) A4 – ALICE 04.10

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1660 S M Tec R5

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