JTAG ,IEEE 1149.6, BOUNDARY SCAN ,VLSI,DFT

1. Boundary scan
EXTEST (1149.6)

2. Why is IEEE 1149.6 needed?
• The original IEEE 1149.1 boundary scan standard was
developed primarily for DC-coupled and single-ended
interconnects such as shown in Figure
While it makes some allowance for differential interconnects, such as shown in Figure 2, the
design and provision of IEEE 1149.1 boundary-scan cells can result in poor test coverage of such
interconnects depending on if each differential lead in the pair is equipped with boundary scan
cells. It is not unusual that only one of the leads in the pair has a boundary-scan cell, resulting in
Testing AC-Coupled and Differential High-Speed Nets
5
fault detection on only one of the nets. Or the boundary scan cell is implemented behind the
differential driver or receiver, resulting in fault detection only to the pair level rather than net or
pin-level detection.

3. EXTEST
Figure shows the details of the IEEE 1149.6 test
receiver suitable for both DC and AC
EXTEST
At the single-ended receiver end, the AC signal
is fed into what is called a hysteretic
comparator, which compares the received
signal with a delayed version of itself in order
to determine the rising or falling nature of the
signal. The output – a logic 1 if the signal is
rising; a logic 0 if it is falling – is passed to the
downstream boundary-scan cell where it can
be captured and scanned out in the normal
way

4. IEEE 1149.6 supplemental instructions
IEEE 1149.6 calls for two instructions that
supplement those of IEEE 1149.1 so as to
support the additional architectural features.
These instructions are
1. EXTEST_PULSE
2. EXTEST_TRAIN

5. EXTEST_PULSE
• EXTEST_PULSE creates a pulse of inverted data
on the driver that lasts as
long as the TAP stays in the Run-Test/Idle state

6. • EXTEST_PULSE generates a single pulse. The pulse is framed by way
of entry to (leading edge) and exit from (trailing edge) the Run-
Test/Idle TAP controller state

7. EXTEST_TRAIN
• EXTEST_TRAIN, we see a “train” of pulses at ½
the TCK frequency while we are in the Run-
Test/Idle state

8. • EXTEST_TRAIN generates a stream of pulses (Figure 12). The pulse
train starts (initial edge) upon entry to the Run-Test/Idle TAP
controller state and continues (toggle edge) on each subsequent
rising TCK edge until the Run-Test/Idle state is exited.

9. AC test signal generation
• A possible implementation for generation of
an ac test signal is shown in Figure 41, for
both the EXTEST_TRAIN and EXTEST_PULSE
instructions

10. AC Pin Output Data Cell
AC/DC selection cell that can be used to cause an AC pin or a set of AC
pins to revert to EXTEST behavior when either EXTEST_PULSE or
EXTEST_TRAIN is loaded

11. Bidirectional Data Pad
Cel

12. An example device with several
Advanced I/O pins
1149.1 and 1149.6 circuitry is shown in
. The designer has marked some of the
pins as “DC” or “AC
Receiver A could be AC-coupled by external
components, so its pin is chosen for AC treatmen
Receiver B is guaranteed to be AC-coupled by virtue
that the AC-coupling is actually integrated on chip
Receiver C is a standard 50-Ω terminated differential
receiver. It could be AC or DC coupled depending on
the application, so the designer chooses the AC
designation for its pins
Receiver D is known to be an “ordinary” logic input
so it is considered a “DC”
input and will be given 1149.1 resources only

13. driver E is differential and could be
connected to other ICs at the board
level that have 1149.6 capability, so it is
a good idea to have the driver support
the EXTEST_PULSE and EXTEST_TRAIN
instructions
Driver F is “ordinary” so it is treated
as a DC pin
DRIVER G AND RECEIVER H form a
terminated, differential , bidirectional
pin pair

14. Expected AC-EXTEST Execution
•

15. EXAMPLE FOR AC EXTEST
•
shown an AC scan cell witha built-in AC pattern generator, it generates AC patterns using “AC-
Pattern-ClocK’ and boundary-scan Capture register cell. First, the EXTEST value from the
Update scan cell is copied into the boundary-scan Capture
register cell with “AC- TesLMarkeT’ and “AC- Pattern- ClocK’. Subsequent
“AC-Pattern-ClocK’ starts to generate a AC pattern and the pattern is fed into the system pin

16. •
The right portion of Figure shows an example of input scan cell with the
AC-EXTEST capability. There is an extra AC pattern sample flip-flop with an “AC-Sync”
signal, which can be generated either explicitly or implicitly When “AC- Test_Ran”
signal becomes active, signifying the AC-EXTEST has been executed under the
Run-TestAdle controller state, the Capture scan cell captures value from the AC
pattern sample flip-flop; otherwise, it captures a value from the system pin. This
selection of capture source is controlled by the signal the “AC- Test_Ran”