Please using verilog and cadence

1. PLL BASED FREQUENCY
SYNTHESIZER USING FPGA
BY
ARUN KUMAR M (21BEC1063)
SAIPRANAV K (21BEC1207)
V.KARTHIK RAM (21BEC1020)
SHREY UPADHYAY (21BEC1460)

2. ABSTRACT:
• This project presents the design and implementation of a Phase-
Locked Loop (PLL) based frequency synthesizer using Verilog.
• The Verilog hardware description language was used to model and
simulate the system, taking advantage of its ability to describe
complex digital designs in a concise and efficient manner.
• The successful simulation results validate the effectiveness of the
design approach and highlight the potential for further enhancements
and applications in the field of digital signal processing.

3. HOW IS THIS PROJECT RELATED TO DSP?
• A phase-locked loop (PLL)-based frequency synthesizer is commonly
used in digital signal processing (DSP) applications to generate stable
and accurate clock signals or frequency references
• PLLs are commonly used in Clock and Data Recovery circuits to extract
the clock signal from a noisy or distorted data stream.
• PLLs can be employed to reduce jitter by synchronizing and
smoothing the phase and frequency of a noisy or jittery signal.

4. WHAT IS A PLL?
• A phase-locked loop (PLL) is an electronic feedback system designed
to generate an output signal that is phase-locked to a reference
signal.
• The main purpose of a PLL is to align the phase and frequency of the
output signal with those of the reference signal.
• This synchronization ensures that the output signal maintains a
constant phase relationship with the reference signal over time.

5. KEY COMPONENTS OF PLL:
A PLL consists of three key components:
• Phase detector (also known as a phase comparator or mixer): It
compares the phases of two signals, and generates a voltage
according to the phase difference. It multiplies the reference input
and the voltage-controlled oscillator output.
• Voltage-controlled oscillator: Generates a sinusoidal signal, whose
frequency closely matches the center frequency provided by the low-
pass filter.
• Low-pass filter: A kind of loop filter that attenuates the high-
frequency alternating current (AC) component of the input signal to
smoothen and flatten the signal to make it more DC-like.

6. Block diagram
X
Y
COMBINATION OF
TWO NUMBERS
COMPLIMENT
ADDITION OF TWO
NUMBERS
SUBTRACTION OF TWO
NUMBERS
ENCODED OUTPUT
SUBTRACTION OF TWO
NUMBERS
ADDITION OF TWO
NUMBERS
SEPERATION OF TWO
NUMBERS
COMPLIMENT
A B
A
B

7. Verilog implementation OF PLL
1. Create a Verilog file with module name defined as PLL_Integer_N.
2. Define all input and output ports required.
3. Implement the Phase Frequency Detector part using always block and
assign the value of ‘pfd_out’ using xor operation between ‘clk_out’ and
‘clk_in’.
4. Implement the Charge Pump module using always block and assign the
value of ‘cp_out’ based on the value of ‘pfd_out’.
5. Implement the Loop filter module using always block and assign the
value of ‘lf_out’ based on the accumulation of ‘cp_out’ over time.
6. Implement the Voltage-Controlled Oscillator module using always block
and assign the value of ‘vco_out’ and ‘vco_divider’ based on the
accumulation of ‘lf_out’.
7. Implement the Output Clock Divider module using always block and
assign the value of ‘divider_count’ based on the increment of counter.

8. Verilog implementation OF PLL
8. Update the value of ‘clk_out_reg’ based on the most
significant bit of ‘divider_count’.
9. Use the assign statement to connect ‘clk_out’ to ‘clk_out_reg’.
10.End the module using end module.
11.Write a test bench for the above Verilog implementation to
check its working in ModelSim.
12.Further use other open source tools to generate a VLSI
Design

9. Verilog implementation OF PLL
module PLL_Integer_N (
input wire clk_in,
input wire rst,
input wire enable,
output wire clk_out
);
// Phase Frequency Detector (PFD)
reg pfd_out;
always @(posedge clk_in or posedge rst) begin
if (rst)
pfd_out <= 1'b0;
else
pfd_out <= clk_out ^ clk_in;
end

10. Verilog implementation OF PLL
// Charge Pump (CP)
reg [1:0] cp_out;
always @(posedge clk_in or posedge rst) begin
if (rst)
cp_out <= 2'b0;
else if (enable)
cp_out <= pfd_out ? 2'b01 : 2'b10;
end
// Loop Filter (LF)
reg [9:0] lf_out;
always @(posedge clk_in or posedge rst) begin
if (rst)
lf_out <= 10'b0;
else if (enable)
lf_out <= lf_out + cp_out;
end

11. Verilog implementation OF PLL
// Voltage-Controlled Oscillator (VCO)
reg [9:0] vco_divider;
reg vco_out;
always @(posedge clk_in or posedge rst) begin
if (rst)
vco_divider <= 10'b0;
else if (enable)
vco_divider <= vco_divider + lf_out;
vco_out <= vco_divider[9];
end

12. Verilog implementation OF PLL
// Output Clock Divider (Divider)
reg [15:0] divider_count;
reg [15:0] clk_out_reg;
always @(posedge clk_in or posedge rst) begin
if (rst)
divider_count <= 16'b0;
else if (enable)
divider_count <= divider_count + 1'b1;
clk_out_reg <= divider_count[15];
end
assign clk_out = clk_out_reg;
endmodule

13. TESTBENCH
module PLL_Integer_N_tb;
reg clk_in;
reg rst;
reg enable;
wire clk_out;
// Instantiate PLL module
PLL_Integer_N pll_inst (
.clk_in(clk_in),
.rst(rst),
.enable(enable),
.clk_out(clk_out)
);
// Clock generation
always begin
#5 clk_in = ~clk_in; // Toggle the input clock every 5 time units
end

14. TESTBENCH
// Testbench stimulus
initial begin
// Initialize inputs
clk_in = 0;
rst = 1;
enable = 0;
// Apply reset
#10;
rst = 0;
// Wait for a rising edge of clk_out
@(posedge clk_out);
// Disable reset and enable the PLL
#10;
rst = 1;
enable = 1;
// Wait for some time
#100;

15. TESTBENCH
// Disable the PLL
#50;
enable = 0;
// Re-enable the PLL
#200;
enable = 1;
// Wait for some time
#100;
// Apply reset again
rst = 0;
// Wait for a rising edge of clk_out
@(posedge clk_out);
// Disable reset and enable the PLL
#20;
rst = 1;

16. TESTBENCH
// Wait for some time
#150;
// Disable the PLL
#10;
enable = 0;
// Stop simulation
$finish;
end
endmodule

17. CADENCE SIMULATION:

18. VERILOG OUTPUT:

19. THANK YOU!!