IntroductionIntroductionWhat is SPI?Properties of SPISPI Master Core SpecificationVerification ApproachEnvironment DiagramTestcasesBUGS!!Conclusion
What is SPI?What is SPI?SPI stands for Serial Peripheral Interface.Synchronous Serial Bus protocoldeveloped by Motorola.Also known as SSI(Synchronous SerialInterface)4-wired serial bus.Simple, fast, easy to use.Accepted by wide number of devicesoffering serial data transmission.
Properties of SPIProperties of SPIAlways FULL DUPLEX.Devices communicate in master-slave mode, master initiates the transfer.Single master – multiple SlavesSingle slave is active at a given instance oftime.Variable transmission speed from slavesupported.
INTERFACEINTERFACEThe SPI bus specifies four logic signalsSCLK: serial clock (output from master)MOSI: master output, slave inputMISO: master input, slave outputSS: slave select (slave enable signal,output from master)
Data TransmissionData TransmissionHost configures the masterMaster initiates the transfer by selectingthe slave, and starting the SCLK.Data from master shifts out from MOSIand slave data shifts in via MISO
FeaturesFeaturesFull duplex synchronous serial data transferVariable length of transfer word up to 128 bitsMSB or LSB first data transferRx and Tx on both rising or falling edge of serialclock independently8 slave select linesFully static synchronous design with one clockdomainTechnology independent VerilogFully synthesizable
Wishbone InterfaceWishbone Interface SPI Master acts as a slave to the Wishbone Interface. Wishbone communicates with the host Bus signals are as described below:
SPI Core registersSPI Core registersData receive registers, Data transmit register◦ Both are same registers, total four registers each of 32 bits◦ Received data is stored in Rx0, Rx1, Rx2, Rx3 after readcycle◦ Transmitted data is stored in Tx0, Tx1, Tx2, Tx3 duringwrite cycleDivider register◦ This register specifies the SCLK frequency which is derivedby dividing the Master clock
Registers Contd.Registers Contd.Slave Select register◦ bits [7:0] defines the current active slave out of 8slaves.◦ It employs 1-hot encoding as to enable only 1 slave ata time, it its automatically set by master if ASS bit inCTRL is set to 1.Control and status register
Verification approachVerification approachMaster agent is established to simulate thewishbone protocol signals from host side.Slave agent is established to simulate the SPIprotocol.Each agent has its individual sequencer, monitorand driver.The virtual sequencer and scoreboard areincluded in the environment and the top levelmodule which encapsulates the RTL along withthe Testcases.
Steps to drive the DUVSteps to drive the DUV To drive the DUV we need to make the signalswb_we_i = 1,wb_stb_i = 1,wb_cyc_i = 1. This will activate the SPI Master Core and indicate avalid write cycle. Supply the address of the SPI core registers to writeinto and wait for the ack to arrive from the core. After configuring the data, divider, and ss registers atlast configure the CTRL register by making GO_BUSYbit to 1 and start the slave data transfer.
Contd.Contd.After slave completes writing the datainto core’s data registers wb_int_o signalwill be asserted.This indicates end of a valid bus cycle andcore is ready to proceed for next cycle.
BUGS!!BUGS!!Able to find two BUGS!! In the design ofSPI master core.First bug is found in MISO coming fromslave side.When the SCLK starts, the data to betransferred is not arriving at triggeringedge of the SCLK as a result X istransferred into the master.
Another BUG!! Is found in the MOSIcoming out of the master core.The applied data to be transmitted toslave is shifted 1-bit right, when collectedfrom slave monitor.01001001110111010101100011000100 MOSI from mastermonitor00100100111011101010110001100010 MOSI from slavemonitor
Design with Multiple SlavesDesign with Multiple Slaves• Design with a single master and multipleindependent slaves.• This Design supports up to 8 slaves which can beaddressed using SS signal independently.
ConclusionConclusionDesign was verified based on UVMmethodology.Simulation was done in Questasim usingSystemVerilog.Two critical bugs were found duringVerification.Functional coverage was implementedand achieved 92.85% of functional codecoverage for this design.
Pros & Cons of SPIPros & Cons of SPIFast & easy to implement.Best choice for point-to-pointconnections.Easily supported by devices.Lack of ACK mechanism.Doesnt have in-built addressing forslavesMultiple slaves increases its complexity.No data error control and flow control.Cant detect if slave present or not.