This document presents a 5-level three-phase cascaded hybrid multilevel inverter. It consists of a standard 3-leg inverter with an H-bridge connected in series to each leg, using separate DC voltage sources of 24V and 48V. The control signals are generated using a FPGA controller with PWM modulation. A simulation model was developed in PSCAD/EMTDC. Experimental results show the output voltages have 5 levels with THD between 15.6-18.3% and the output currents are close to sinusoidal with THD between 2.7-4.2%. The hybrid multilevel inverter topology reduces the number of switches and capacitors compared to other multilevel inverter structures.
This document describes the design and simulation of a five-level cascaded inverter using multilevel sinusoidal pulse width modulation strategies. It presents the circuit design of a single-phase five-level cascaded inverter and discusses four types of multilevel sinusoidal PWM techniques - alternative phase opposition disposition, phase disposition, phase-shifted, and phase opposition disposition. The total harmonic distortion for each technique is analyzed through MATLAB/Simulink simulations. The results show that phase opposition disposition PWM has the lowest harmonic content compared to the other techniques.
Equal Switching Distribution Method for Multi-Level Cascaded Inverterijsrd.com
the paper proposes a new method of equal switching distribution that can be applied to cascaded multilevel inverters. This method is based on the fact that in the cascaded multilevel inverters, the output phase voltage is the sum of voltage waveforms produced by all cascaded cells. By periodically exchanging cells' voltage waveforms, the proposed method ensures equal average switching's distribution between all cascaded cells. This method is applied to the 13-level inverter, which consists of three cascaded 5-level H-bridge cells per phase. However, the proposed method can be extended to any desired number of voltage levels and applied to any type of cascaded multilevel inverter. Extensive simulation results of the tested 13- level inverter with the equal switching distribution are presented. Moreover, the proposed method is compared to the standard control approaches and its advantages are shown.
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...VLSICS Design
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
Common Mode Voltage reduction in Diode Clamped MLI using Alternative Phase Op...Mohd Esa
The main objective of this paper is to reduce the Common Mode Voltage (CMV) in the Diode Clamped Multilevel Inverter (DCMLI).Three phase Y-connected RL load is connected to DCMLI. The common mode voltage exists between neutral point of Y-connected load and system ground.CMV causes premature failure of bearings of induction motor and is essential to reduce. In this paper, Alternative Phase Opposition Disposition SPWM technique is used to reduce common mode voltage. Two level, five level, seven level and nine level DCMLI are compared in terms of THD and CMV.The effect of a passive LC filter on THD was studied. The simulation of circuit is carried out by using MATLAB/Simulink. Simulation result portrays reduction in THD and CMV by using APOD-SPWM controlled higher level Inverters.
Harmonic Analysis of Three level Flying Capacitor InverterMohd Esa
The aim of this paper is to determine the Total harmonic distortion (THD) of three phase three level flying capacitor inverter fed star connected R-L load. The modulation Techniques used is Phase Disposition Sinusoidal pulse width modulation (PD-SPWM) and Phase Opposition Disposition Sinusoidal pulse width modulation (POD-SPWM).The Modulation index is varied to analyze its effect on Current THD and Voltage THD.This paper also presents the comparison of PD-SPWM and POD-SPWM controlled Flying capacitor Inverter in terms of THD. The simulation result shows that PD-SPWM has better performance when compared to POD-SPWM. The simulation of circuit is done by using MATLAB/Simulink.
A Overlapping Carrier Based SPWM for a 5-Level Cascaded H-bridge Multilevel I...IJPEDS-IAES
This paper proposes a switching control for a cascaded H-bridge inverter
structure with reduced switches which is used to improve the THD
performance of a single phase five level CHB MLI. The multi level inverter
is simulated for the conventional carrier overlapping APOD and the proposed
carrier overlapping APOD pulse width modulation (PWM) switching control
technique. The total harmonic distortion (THD) of the output voltages are
observed for both PWM control techniques. The performance of the
symmetric CHB MLI is simulated using MATLAB/Simulink. It is observed
that the proposed carrier overlapping APODPWM provides output with
relatively low THD as compared to the conventional carrier overlapping
APODPWM.
Implementation of Three phase SPWM Inverter with Minimum Number of Power Elec...IJMTST Journal
In the past decades, the researchers have dealt with the conventional topology, which possesses sum switches of Multilevel Inverter is applied to PWM method. The present research work has been introduced a new method of multilevel inverter using reduced switches is applied with PWM technique. In introduction part the conventional new multilevel inverter & switching pattern are explained. In second part PWM technique of proposed work and circuits is explained. The width of this pulses are modulated in order to obtain inverter output voltage control and to reduce its harmonic content. Sinusoidal pulse width modulation or SPWM is the most common method in motor control and inverter application. Conventionally, to generate the signal, triangle wave as a carrier signal is compared with the sinusoidal wave, whose frequency is the desired frequency.
This document describes the design and simulation of a five-level cascaded inverter using multilevel sinusoidal pulse width modulation strategies. It presents the circuit design of a single-phase five-level cascaded inverter and discusses four types of multilevel sinusoidal PWM techniques - alternative phase opposition disposition, phase disposition, phase-shifted, and phase opposition disposition. The total harmonic distortion for each technique is analyzed through MATLAB/Simulink simulations. The results show that phase opposition disposition PWM has the lowest harmonic content compared to the other techniques.
Equal Switching Distribution Method for Multi-Level Cascaded Inverterijsrd.com
the paper proposes a new method of equal switching distribution that can be applied to cascaded multilevel inverters. This method is based on the fact that in the cascaded multilevel inverters, the output phase voltage is the sum of voltage waveforms produced by all cascaded cells. By periodically exchanging cells' voltage waveforms, the proposed method ensures equal average switching's distribution between all cascaded cells. This method is applied to the 13-level inverter, which consists of three cascaded 5-level H-bridge cells per phase. However, the proposed method can be extended to any desired number of voltage levels and applied to any type of cascaded multilevel inverter. Extensive simulation results of the tested 13- level inverter with the equal switching distribution are presented. Moreover, the proposed method is compared to the standard control approaches and its advantages are shown.
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...VLSICS Design
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
Common Mode Voltage reduction in Diode Clamped MLI using Alternative Phase Op...Mohd Esa
The main objective of this paper is to reduce the Common Mode Voltage (CMV) in the Diode Clamped Multilevel Inverter (DCMLI).Three phase Y-connected RL load is connected to DCMLI. The common mode voltage exists between neutral point of Y-connected load and system ground.CMV causes premature failure of bearings of induction motor and is essential to reduce. In this paper, Alternative Phase Opposition Disposition SPWM technique is used to reduce common mode voltage. Two level, five level, seven level and nine level DCMLI are compared in terms of THD and CMV.The effect of a passive LC filter on THD was studied. The simulation of circuit is carried out by using MATLAB/Simulink. Simulation result portrays reduction in THD and CMV by using APOD-SPWM controlled higher level Inverters.
Harmonic Analysis of Three level Flying Capacitor InverterMohd Esa
The aim of this paper is to determine the Total harmonic distortion (THD) of three phase three level flying capacitor inverter fed star connected R-L load. The modulation Techniques used is Phase Disposition Sinusoidal pulse width modulation (PD-SPWM) and Phase Opposition Disposition Sinusoidal pulse width modulation (POD-SPWM).The Modulation index is varied to analyze its effect on Current THD and Voltage THD.This paper also presents the comparison of PD-SPWM and POD-SPWM controlled Flying capacitor Inverter in terms of THD. The simulation result shows that PD-SPWM has better performance when compared to POD-SPWM. The simulation of circuit is done by using MATLAB/Simulink.
A Overlapping Carrier Based SPWM for a 5-Level Cascaded H-bridge Multilevel I...IJPEDS-IAES
This paper proposes a switching control for a cascaded H-bridge inverter
structure with reduced switches which is used to improve the THD
performance of a single phase five level CHB MLI. The multi level inverter
is simulated for the conventional carrier overlapping APOD and the proposed
carrier overlapping APOD pulse width modulation (PWM) switching control
technique. The total harmonic distortion (THD) of the output voltages are
observed for both PWM control techniques. The performance of the
symmetric CHB MLI is simulated using MATLAB/Simulink. It is observed
that the proposed carrier overlapping APODPWM provides output with
relatively low THD as compared to the conventional carrier overlapping
APODPWM.
Implementation of Three phase SPWM Inverter with Minimum Number of Power Elec...IJMTST Journal
In the past decades, the researchers have dealt with the conventional topology, which possesses sum switches of Multilevel Inverter is applied to PWM method. The present research work has been introduced a new method of multilevel inverter using reduced switches is applied with PWM technique. In introduction part the conventional new multilevel inverter & switching pattern are explained. In second part PWM technique of proposed work and circuits is explained. The width of this pulses are modulated in order to obtain inverter output voltage control and to reduce its harmonic content. Sinusoidal pulse width modulation or SPWM is the most common method in motor control and inverter application. Conventionally, to generate the signal, triangle wave as a carrier signal is compared with the sinusoidal wave, whose frequency is the desired frequency.
This document presents a comparative investigation of a 7-level cascaded multilevel inverter using different multicarrier pulse width modulation techniques. It discusses the classification, operation, and modulation strategies of multilevel inverters including diode clamped, flying capacitor, and cascaded H-bridge topologies. Simulation results in MATLAB/Simulink are presented to analyze the total harmonic distortion for a 7-level cascaded H-bridge multilevel inverter using phase disposition, alternate phase opposition disposition, and phase opposition disposition pulse width modulation techniques. The research aims to improve the output waveform quality and reduce switching losses of the 7-level inverter.
APPLICATIONS OF FLOATING-GATE MOSFET IN THE DESIGN OF INVERTER AND RING OSCIL...elelijjournal
This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Space Vector Modulation Strategy for NPC ConverterIRJET Journal
This document describes a control strategy for an eight-switch neutral point clamped (NPC) converter. The NPC converter uses only two legs instead of the conventional three legs to reduce the number of switches. A simplified space vector pulse width modulation (SVPWM) algorithm is used to calculate the time durations of the voltage vectors and generate control pulses for the switches. Computer simulations are presented to verify that the control strategy can regulate the DC bus voltage and draw sinusoidal line currents with unity power factor from the AC mains.
PWM Switched Voltage Source Inverter with Zero Neutral Point Potentialijsrd.com
A three phase three-level pulse width modulation
(PWM) switched voltage source inverter with zero neutral
point potential is designed. It consists of three single-phase
inverter modules and each module is composed of a
switched voltage source and inverter switches. The major
advantage is that the peak value of the phase output voltage
is twice as high as that of the conventional neutral-pointclamped
PWM inverter. Thus, the proposed inverter is
suitable for applications with low voltage sources such as
batteries, fuel cells, or solar cells. Furthermore, three-level
output waveforms of the inverter can be achieved without
the switch voltage unbalance problem. Since the average
neutral point potential of the inverter is zero, a common
ground between the input stage and the output stage is
possible. Therefore, it can be applied to a transformer-less
power conditioning system. The SVS inverter is tested by a
PSIM simulation and hardware is implemented and verified.
This document summarizes three topologies of cascaded H-bridge multilevel inverters: the existing topology, proposed topology I, and proposed topology II. The existing topology uses two DC sources per phase. Proposed topology I uses one DC source for all three phases and transformers. Proposed topology II also uses one DC source for all phases and reduces the number of switches compared to the other topologies. MATLAB simulations were performed and results were compared in terms of voltage THD and equipment requirements. The existing topology had the best performance based on FFT analysis, but proposed topology II is best in terms of cost and switching losses when considering single DC source topologies.
Investigation of THD for Cascaded Multi-Level Inverter Using Multicarrier Mod...IJERA Editor
This document summarizes an investigation into the total harmonic distortion (THD) of cascaded multi-level inverters using different multicarrier modulation techniques. It describes three modulation techniques - phase shifted multicarrier modulation (PSHM), level shifted multicarrier modulation (LSHM), and wave level shifted multicarrier modulation (WLSHM). Simulation results for 7-level, 9-level, 11-level, and 13-level inverters show that WLSHM achieves the lowest THD compared to the other techniques. The document concludes that WLSHM is the best modulation method for reducing THD in cascaded multi-level inverters.
Common Mode Voltage reduction in Diode Clamped MLI using SPWM TechniquesMOHD ABDUL MUQEEM NAWAZ
This document discusses techniques to reduce common mode voltage in diode clamped multilevel inverters using sinusoidal pulse width modulation. It presents simulation results comparing phase disposition, phase opposition disposition, and alternative phase opposition disposition SPWM methods in 3-level, 5-level, 7-level and 9-level inverters. The zero common mode SPWM technique is also analyzed, showing it can eliminate common mode voltage. Simulation results show that higher level inverters and carrier disposition techniques like alternative phase opposition disposition more effectively reduce common mode voltage and total harmonic distortion.
Performance Evaluation of a Three Phase Nine Level Inverter with Reduced Swit...Scientific Review
This paper presents a three phase nine level cascaded H-bridge (CHB) multilevel inverter with RL load. A sinusoidal and trapezoidal PWM method is used to achieve minimum total harmonics distortion (THD) in the output current of multilevel inverters. The analysis of the output current harmonics is carried out and compared with the seven level conventional cascaded H-bridge inverters. The proposed inverter is verified through simulation and the simulation results are compared with the conventional multilevel inverter. From the result the proposed inverter offers much less total harmonic distortion.
THD analysis of SPWM & THPWM Controlled Three phase Voltage Source InverterIRJET Journal
This document analyzes and compares the total harmonic distortion (THD) of a three-phase voltage source inverter controlled by two modulation techniques: sinusoidal pulse width modulation (SPWM) and third harmonic pulse width modulation (THPWM). The simulation results show that THPWM has better performance than SPWM, with lower current and voltage THD values. Specifically, THPWM provides current THD below 2% and voltage THD below 55% across all tested carrier frequencies, while SPWM has higher THD, with minimum values of 2.06% for current and 65.98% for voltage. Therefore, THPWM is determined to produce output voltage and current of better quality compared to SPWM.
A Novel Hybrid Negative Half Cycle Biased Modulation Scheme for Cascaded Mult...IJPEDS-IAES
This paper proposes a new Modified hybrid modulation scheme for cascaded multilevel inverter. The proposed method employs novel single carrier sinusoidal pulse width modulation with its negative cycle biased (HNHCBM) for reducing switching losses when compared to other sinusoidal modulation methods using a hybrid scheme. This scheme is a derivative of various single carrier sinusoidal pulse width modulation scheme and main advantages are reduced harmonics, enhanced output voltage, reduced power loss in the series cells and ease of implementation. The simulation results are analysed with matlab/simulink and compared with experimental results obtained using 5-level inverter and the results are summarized.
Analysis Approach for Five Phase Two-Level Voltage Source Inverter with PWM T...ijsrd.com
this paper gives idea of comparison of five phase two-level voltage inverter (FPTLVSI) without filter circuit and control scheme and FPTLVSI with filter circuit and PWM control scheme for induction motor drive. The paper demonstrates using mat lab simulations about comparison in term of harmonics analysis for different firing angles and find best angle suitable for output with minimum harmonics for FPTLVSI without filter circuit and control scheme and harmonics analysis of FPTLVSI with filter and PWM control scheme. This paper suggests simulation of comparison of harmonics point of view five phase two-level voltage inverter (FPTLVSI) without filter circuit and control scheme and with filter circuit and PWM control scheme for induction motor drive.
A Novel Topology of Multilevel Inverter with Reduced Number of Switches and D...IAES-IJPEDS
This paper introduces new topology of cascaded multilevel inverter, with considerable reduction in the number of switches and DC voltage sources. The proposed topology is based on asymmetrical multilevel inverter which produces 21 levels of output with the use of 11 unidirectional switches, 3 diodes and 4 DC voltage sources. The advantages of this topology are reduction in the number of switches (2 nos.) and gate driver circuits (2 nos.), reduction in the number of DC sources (2 nos.) also cost, complexity, and space required for hardware is reduced without sacrificing the quality output of the inverter. To reduce the THD further Level shifting SPWM techniques such as PD, POD & APOD are used and comparison is shown on the basis of THDs obtained from the above SPWM techniques. Frequency of carrier waves is 1KHz, and modulation index is 1.0. To validate the proposed topology the circuit is simulated and verified by using MATLAB/Simulink.
A New Proposal for OFCC-based Instrumentation AmplifierYayah Zakaria
This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA
architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values
of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
The document presents a hybrid pulse width modulation (HPWM) method for voltage source inverter (VSI) fed induction motor drives. It proposes a generalized PWM (GPWM) algorithm that varies a constant to generate different discontinuous PWM (DPWM) algorithms along with the space vector PWM (SVPWM) algorithm. The GPWM approach uses instantaneous phase voltages to calculate inverter gating times, reducing complexity compared to the classical SVPWM approach. Simulation results show that SVPWM gives better performance at low modulation indices, while DPWM is better at higher indices. Therefore, the paper presents a HPWM algorithm to achieve superior waveform quality across all modulation indices.
Multilevel inverters are emerging as the new breed of power converter options for high power applications. They typically synthesis the staircase voltage waveform (from several dc sources) which reduced harmonic content. This paper presents a simple selective harmonic elimination (SHE) modulation for single-phase cascaded H-bridge (CHB) multilevel inverter. The optimum switching angle of the transcendental equations describing the fundamental and harmonic components is solved by means of the Newton-Raphson (NR) method. The proposed SHE scheme is performed through simulation using MATLAB/Simulink. This simulation results are then verified through experiment using Altera DE0-Nano field-programmable gate array (FPGA). The proposed SHE is efficient in eliminating the lowest-order harmonics and producing a higher quality output waveform with a better harmonic profile.
This paper presents the design of the feedback loop for single controller power factor correction converters. The feedback loop design must account for the large second harmonic component of the rectified input voltage. The size of the bulk capacitor and the corresponding loop gain affect the converter's performance in terms of total harmonic distortion, discontinuous conduction mode operation, and output regulation. The paper provides design procedures and examples for a boost-forward power factor correction converter. Simulation and experimental results validate the design approach.
Hybrid topology of asymmetric cascaded multilevel inverter with renewable ene...Asoka Technologies
This paper presents a binary topology of Multimodule level inverters produce a staircase output voltage from renewable DC voltage sources. The MLI (Multi Level Inverter) Requires many number of semiconductor switches is main drawback of multilevel inverters. The MLI can be classified as two method, one is symmetric and another asymmetric converters. In symmetrical multilevel inverter can apply same voltage level to all cascaded circuit, in asymmetric multilevel inverters can be vary input source voltage at each cascaded H-bridge by using binary algorithm. In this paper, a discrete binary topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converter can produce sixty three levels of voltage from five discrete DC source. The Total Harmonic Distortions (THD) is minimized by discrete binary topology. The working operation and performance of the proposed multilevel inverters studies has been verified by simulation of using SIMULINK / MA TLAB results.
Comparative analysis of cascade h-bridge multilevel Voltage source inverterPvrtechnologies Nellore
The document compares cascade h-bridge multilevel voltage source inverters. It presents the basics of cascaded H-Bridge multilevel inverters, their working principle, circuit topologies, control techniques, and provides a comparative analysis of different level H-Bridge topologies in terms of total harmonic distortion and fast Fourier transform. The analysis shows that while complexity increases with more levels, total harmonic distortion decreases and output voltage increases, improving output power quality. Various level topologies are simulated using PSIM software to validate the analytical results.
The document lists 82 topics related to embedded system design. The topics are organized under different fields including RTOS, PSoC, CAN, TCPIP, Power Consumption, Wireless Technologies, Robotics, and Bio-Medical/Image Processing. Each topic provides a brief description of a research project related to embedded systems and the listed field.
Diode Free T-Type Five Level Neutral Point Clamped Inverter for Low Voltage D...IJTET Journal
Abstract—The multilevel inverter is used as a solution to increase the inverter operating voltage above the voltage limits of classical semiconductors. A Diode Free T-Type Five Level NPC inverter for Low Voltage DC System is proposed in this paper. The T-Type inverter topology is more efficient and conventional than I-type inverter topology. Considerable suppression of the harmonic current is the ultimate goal of multilevel inverter. Losses like Semiconductor loss, conduction loss are mainly due to IGBT & diode in the current path. So the proposed system is designed with cool MOSFET without diode. The middle bidirectional switch is replaced by two pair of MOSFET. Hence the five level NPC inverter is more significant for low and medium power range DC source and for Renewable energy system.
Inductorless DC-AC Cascaded H-bridge MultilevelBoost Inverter for Electric/...mkanth
This document describes an inductorless DC-AC cascaded H-bridge multilevel boost inverter for electric vehicle applications. It works by using an H-bridge in series with each inverter leg to boost the output voltage beyond what is possible with a traditional inverter. The inverter uses capacitor voltage regulation and fundamental switching control to output a 5-level phase voltage. Experimental results validated that it can achieve a much wider modulation index range compared to traditional inverters, allowing it to boost the output voltage.
This document presents a comparative investigation of a 7-level cascaded multilevel inverter using different multicarrier pulse width modulation techniques. It discusses the classification, operation, and modulation strategies of multilevel inverters including diode clamped, flying capacitor, and cascaded H-bridge topologies. Simulation results in MATLAB/Simulink are presented to analyze the total harmonic distortion for a 7-level cascaded H-bridge multilevel inverter using phase disposition, alternate phase opposition disposition, and phase opposition disposition pulse width modulation techniques. The research aims to improve the output waveform quality and reduce switching losses of the 7-level inverter.
APPLICATIONS OF FLOATING-GATE MOSFET IN THE DESIGN OF INVERTER AND RING OSCIL...elelijjournal
This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Space Vector Modulation Strategy for NPC ConverterIRJET Journal
This document describes a control strategy for an eight-switch neutral point clamped (NPC) converter. The NPC converter uses only two legs instead of the conventional three legs to reduce the number of switches. A simplified space vector pulse width modulation (SVPWM) algorithm is used to calculate the time durations of the voltage vectors and generate control pulses for the switches. Computer simulations are presented to verify that the control strategy can regulate the DC bus voltage and draw sinusoidal line currents with unity power factor from the AC mains.
PWM Switched Voltage Source Inverter with Zero Neutral Point Potentialijsrd.com
A three phase three-level pulse width modulation
(PWM) switched voltage source inverter with zero neutral
point potential is designed. It consists of three single-phase
inverter modules and each module is composed of a
switched voltage source and inverter switches. The major
advantage is that the peak value of the phase output voltage
is twice as high as that of the conventional neutral-pointclamped
PWM inverter. Thus, the proposed inverter is
suitable for applications with low voltage sources such as
batteries, fuel cells, or solar cells. Furthermore, three-level
output waveforms of the inverter can be achieved without
the switch voltage unbalance problem. Since the average
neutral point potential of the inverter is zero, a common
ground between the input stage and the output stage is
possible. Therefore, it can be applied to a transformer-less
power conditioning system. The SVS inverter is tested by a
PSIM simulation and hardware is implemented and verified.
This document summarizes three topologies of cascaded H-bridge multilevel inverters: the existing topology, proposed topology I, and proposed topology II. The existing topology uses two DC sources per phase. Proposed topology I uses one DC source for all three phases and transformers. Proposed topology II also uses one DC source for all phases and reduces the number of switches compared to the other topologies. MATLAB simulations were performed and results were compared in terms of voltage THD and equipment requirements. The existing topology had the best performance based on FFT analysis, but proposed topology II is best in terms of cost and switching losses when considering single DC source topologies.
Investigation of THD for Cascaded Multi-Level Inverter Using Multicarrier Mod...IJERA Editor
This document summarizes an investigation into the total harmonic distortion (THD) of cascaded multi-level inverters using different multicarrier modulation techniques. It describes three modulation techniques - phase shifted multicarrier modulation (PSHM), level shifted multicarrier modulation (LSHM), and wave level shifted multicarrier modulation (WLSHM). Simulation results for 7-level, 9-level, 11-level, and 13-level inverters show that WLSHM achieves the lowest THD compared to the other techniques. The document concludes that WLSHM is the best modulation method for reducing THD in cascaded multi-level inverters.
Common Mode Voltage reduction in Diode Clamped MLI using SPWM TechniquesMOHD ABDUL MUQEEM NAWAZ
This document discusses techniques to reduce common mode voltage in diode clamped multilevel inverters using sinusoidal pulse width modulation. It presents simulation results comparing phase disposition, phase opposition disposition, and alternative phase opposition disposition SPWM methods in 3-level, 5-level, 7-level and 9-level inverters. The zero common mode SPWM technique is also analyzed, showing it can eliminate common mode voltage. Simulation results show that higher level inverters and carrier disposition techniques like alternative phase opposition disposition more effectively reduce common mode voltage and total harmonic distortion.
Performance Evaluation of a Three Phase Nine Level Inverter with Reduced Swit...Scientific Review
This paper presents a three phase nine level cascaded H-bridge (CHB) multilevel inverter with RL load. A sinusoidal and trapezoidal PWM method is used to achieve minimum total harmonics distortion (THD) in the output current of multilevel inverters. The analysis of the output current harmonics is carried out and compared with the seven level conventional cascaded H-bridge inverters. The proposed inverter is verified through simulation and the simulation results are compared with the conventional multilevel inverter. From the result the proposed inverter offers much less total harmonic distortion.
THD analysis of SPWM & THPWM Controlled Three phase Voltage Source InverterIRJET Journal
This document analyzes and compares the total harmonic distortion (THD) of a three-phase voltage source inverter controlled by two modulation techniques: sinusoidal pulse width modulation (SPWM) and third harmonic pulse width modulation (THPWM). The simulation results show that THPWM has better performance than SPWM, with lower current and voltage THD values. Specifically, THPWM provides current THD below 2% and voltage THD below 55% across all tested carrier frequencies, while SPWM has higher THD, with minimum values of 2.06% for current and 65.98% for voltage. Therefore, THPWM is determined to produce output voltage and current of better quality compared to SPWM.
A Novel Hybrid Negative Half Cycle Biased Modulation Scheme for Cascaded Mult...IJPEDS-IAES
This paper proposes a new Modified hybrid modulation scheme for cascaded multilevel inverter. The proposed method employs novel single carrier sinusoidal pulse width modulation with its negative cycle biased (HNHCBM) for reducing switching losses when compared to other sinusoidal modulation methods using a hybrid scheme. This scheme is a derivative of various single carrier sinusoidal pulse width modulation scheme and main advantages are reduced harmonics, enhanced output voltage, reduced power loss in the series cells and ease of implementation. The simulation results are analysed with matlab/simulink and compared with experimental results obtained using 5-level inverter and the results are summarized.
Analysis Approach for Five Phase Two-Level Voltage Source Inverter with PWM T...ijsrd.com
this paper gives idea of comparison of five phase two-level voltage inverter (FPTLVSI) without filter circuit and control scheme and FPTLVSI with filter circuit and PWM control scheme for induction motor drive. The paper demonstrates using mat lab simulations about comparison in term of harmonics analysis for different firing angles and find best angle suitable for output with minimum harmonics for FPTLVSI without filter circuit and control scheme and harmonics analysis of FPTLVSI with filter and PWM control scheme. This paper suggests simulation of comparison of harmonics point of view five phase two-level voltage inverter (FPTLVSI) without filter circuit and control scheme and with filter circuit and PWM control scheme for induction motor drive.
A Novel Topology of Multilevel Inverter with Reduced Number of Switches and D...IAES-IJPEDS
This paper introduces new topology of cascaded multilevel inverter, with considerable reduction in the number of switches and DC voltage sources. The proposed topology is based on asymmetrical multilevel inverter which produces 21 levels of output with the use of 11 unidirectional switches, 3 diodes and 4 DC voltage sources. The advantages of this topology are reduction in the number of switches (2 nos.) and gate driver circuits (2 nos.), reduction in the number of DC sources (2 nos.) also cost, complexity, and space required for hardware is reduced without sacrificing the quality output of the inverter. To reduce the THD further Level shifting SPWM techniques such as PD, POD & APOD are used and comparison is shown on the basis of THDs obtained from the above SPWM techniques. Frequency of carrier waves is 1KHz, and modulation index is 1.0. To validate the proposed topology the circuit is simulated and verified by using MATLAB/Simulink.
A New Proposal for OFCC-based Instrumentation AmplifierYayah Zakaria
This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA
architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values
of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
The document presents a hybrid pulse width modulation (HPWM) method for voltage source inverter (VSI) fed induction motor drives. It proposes a generalized PWM (GPWM) algorithm that varies a constant to generate different discontinuous PWM (DPWM) algorithms along with the space vector PWM (SVPWM) algorithm. The GPWM approach uses instantaneous phase voltages to calculate inverter gating times, reducing complexity compared to the classical SVPWM approach. Simulation results show that SVPWM gives better performance at low modulation indices, while DPWM is better at higher indices. Therefore, the paper presents a HPWM algorithm to achieve superior waveform quality across all modulation indices.
Multilevel inverters are emerging as the new breed of power converter options for high power applications. They typically synthesis the staircase voltage waveform (from several dc sources) which reduced harmonic content. This paper presents a simple selective harmonic elimination (SHE) modulation for single-phase cascaded H-bridge (CHB) multilevel inverter. The optimum switching angle of the transcendental equations describing the fundamental and harmonic components is solved by means of the Newton-Raphson (NR) method. The proposed SHE scheme is performed through simulation using MATLAB/Simulink. This simulation results are then verified through experiment using Altera DE0-Nano field-programmable gate array (FPGA). The proposed SHE is efficient in eliminating the lowest-order harmonics and producing a higher quality output waveform with a better harmonic profile.
This paper presents the design of the feedback loop for single controller power factor correction converters. The feedback loop design must account for the large second harmonic component of the rectified input voltage. The size of the bulk capacitor and the corresponding loop gain affect the converter's performance in terms of total harmonic distortion, discontinuous conduction mode operation, and output regulation. The paper provides design procedures and examples for a boost-forward power factor correction converter. Simulation and experimental results validate the design approach.
Hybrid topology of asymmetric cascaded multilevel inverter with renewable ene...Asoka Technologies
This paper presents a binary topology of Multimodule level inverters produce a staircase output voltage from renewable DC voltage sources. The MLI (Multi Level Inverter) Requires many number of semiconductor switches is main drawback of multilevel inverters. The MLI can be classified as two method, one is symmetric and another asymmetric converters. In symmetrical multilevel inverter can apply same voltage level to all cascaded circuit, in asymmetric multilevel inverters can be vary input source voltage at each cascaded H-bridge by using binary algorithm. In this paper, a discrete binary topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converter can produce sixty three levels of voltage from five discrete DC source. The Total Harmonic Distortions (THD) is minimized by discrete binary topology. The working operation and performance of the proposed multilevel inverters studies has been verified by simulation of using SIMULINK / MA TLAB results.
Comparative analysis of cascade h-bridge multilevel Voltage source inverterPvrtechnologies Nellore
The document compares cascade h-bridge multilevel voltage source inverters. It presents the basics of cascaded H-Bridge multilevel inverters, their working principle, circuit topologies, control techniques, and provides a comparative analysis of different level H-Bridge topologies in terms of total harmonic distortion and fast Fourier transform. The analysis shows that while complexity increases with more levels, total harmonic distortion decreases and output voltage increases, improving output power quality. Various level topologies are simulated using PSIM software to validate the analytical results.
The document lists 82 topics related to embedded system design. The topics are organized under different fields including RTOS, PSoC, CAN, TCPIP, Power Consumption, Wireless Technologies, Robotics, and Bio-Medical/Image Processing. Each topic provides a brief description of a research project related to embedded systems and the listed field.
Diode Free T-Type Five Level Neutral Point Clamped Inverter for Low Voltage D...IJTET Journal
Abstract—The multilevel inverter is used as a solution to increase the inverter operating voltage above the voltage limits of classical semiconductors. A Diode Free T-Type Five Level NPC inverter for Low Voltage DC System is proposed in this paper. The T-Type inverter topology is more efficient and conventional than I-type inverter topology. Considerable suppression of the harmonic current is the ultimate goal of multilevel inverter. Losses like Semiconductor loss, conduction loss are mainly due to IGBT & diode in the current path. So the proposed system is designed with cool MOSFET without diode. The middle bidirectional switch is replaced by two pair of MOSFET. Hence the five level NPC inverter is more significant for low and medium power range DC source and for Renewable energy system.
Inductorless DC-AC Cascaded H-bridge MultilevelBoost Inverter for Electric/...mkanth
This document describes an inductorless DC-AC cascaded H-bridge multilevel boost inverter for electric vehicle applications. It works by using an H-bridge in series with each inverter leg to boost the output voltage beyond what is possible with a traditional inverter. The inverter uses capacitor voltage regulation and fundamental switching control to output a 5-level phase voltage. Experimental results validated that it can achieve a much wider modulation index range compared to traditional inverters, allowing it to boost the output voltage.
This document discusses a multilevel inverter project for drive applications. Multilevel inverters can operate at higher voltages and produce lower harmonic components. The project involves simulating a 3-phase 3-level cascaded H-bridge inverter in MATLAB Simulink. A DSP processor is used to generate switching signals, which are then sent to a gate driver circuit to drive the inverter. Hardware implementation of a 3-level inverter gate driver is presented, along with gate drive pulses and dead band generation. Future work includes implementing a 3-phase 3-level inverter for motor speed control and comparing THD of sine and space vector modulation.
This ppt gives the basic idea about multilevel inverter.this ppt includes
1.Introduction
2.Advantages of multilevel inverters
3.Types of multilevel inverters
4.Working of multilevel inverters
5.Applications.
The document presents a new topology for a submultilevel inverter and proposes connecting multiple submultilevel inverters in series to create a generalized multilevel inverter. The proposed multilevel inverter uses fewer switching devices than existing topologies and is analyzed under symmetric and asymmetric conditions. Simulation results using MATLAB-SIMULINK show the asymmetric 31-level inverter has distortion of only 0.2% using 12 switches, while the symmetric 13-level inverter has 0.8% distortion using 16 switches.
The document summarizes a presentation on e-banking services provided by HDFC Bank in India. It provides background on HDFC Bank's founding and operations, describes the different types of electronic banking available including internet banking, phone banking and mobile banking. It then outlines the objectives and findings of a study conducted on users of ATM and internet banking services, including that most users were satisfied with ATM services but some faced issues like cards getting stuck in machines. Suggestions to address problems include educating users, improving security, and making applications easy to use.
Space Vector Modulation(SVM) Technique for PWM InverterPurushotam Kumar
This document discusses space vector pulse width modulation (SVM) for three-phase voltage source inverters. It begins by introducing SVM and its benefits over other PWM techniques, such as reduced total harmonic distortion. It then provides details on how SVM works, including transforming a three-phase reference signal to a rotating vector in the d-q reference frame. The document explains the eight possible switching states, sectors, and how to calculate switching times to synthesize the reference signal using adjacent active vectors and zero vectors. It concludes by comparing SVM to sinusoidal PWM, showing SVM offers better voltage utilization and harmonic performance.
Multi Carrier based Multilevel Inverter with Minimal Harmonic DistortionIJPEDS-IAES
This paper presents performance features of Asymmetric Cascaded
Multilevel inverter. Multilevel inverters are commonly modulated by using
multicarrier pulse width modulation (MCPWM) techniques such as phaseshifted
multicarrier modulation and level-shifted multicarrier modulation.
Amongst these, level-shifted multicarrier modulation technique produces the
best harmonic performance. This work studies about multilevel inverter with
unequal DC sources using level shifting MCPWM technique. The
Performances indices like Total Harmonic Distortion (THD), number of
switches and DC Sources are considered. A procedure to achieve an
appropriate level shifting is also presented is this paper.
One of the preferred choices of electronic power conversion for high power applications are multilevel inverters topologies finding increased attention in industry. Cascaded H-Bridge multilevel inverter is one of these topologies reaching the higher output voltage, power level and higher reliability due to its modular topology. Level Shifted Carrier Pulse Width Modulation (LSCPWM) and Phase Shifted Carrier Pulse Width Modulation are used generally for switching cascaded H-bridge (CHB) multilevel inverters. This paper compares LSCPWM and PSCPWM in terms of total harmonics distortion (THD) and output voltage among inverter cells. Simulation for 21-level CHB inverter is carried out in MATLAB/SIMULINK and simulation results are presented.
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses. In this paper single phase to three phase power conversion using PWM technique. The simulation is carried out in MATLAB/Simulink environment which demonstrate the feasibility of proposed scheme.
PWM control techniques for three phase three level inverter drivesTELKOMNIKA JOURNAL
In this paper two very efficient pulse width modulation techniques were discussed named Sin pulse width modulation and space vector pulse width modulation. The basic structure of the three-level inverter neutral-point clamped is introduced and the basic idea about space vector pulse width modulation for three-level voltage source inverter has been discussed in detail. Nearest three vectors space vector pulse width modulation control algorithm is adopted as the control strategy for the three phase three level NPC inverter in order to compensate the neutral-point shifting. Mathematical formulation for calculating switching sequence has determined. Comparative analysis proving superiority of the space vector pulse width modulation technique over the conventional pulse width modulation, and the results of the simulations of inverter confirm the feasibility and advantage of the space vector pulse width modulation strategy over sin pulse width modulation in terms of good utilization of dc-bus voltage, low current ripple and reduced switching frequency. Space vector pulse width modulation provides advantages better fundamental output voltage and useful in improving harmonic performance and reducing total harmonic distortion.
This document summarizes a research paper on minimizing total harmonic distortion (THD) in a three-phase, five-level cascaded H-bridge inverter. It first describes the configuration and operation of a cascaded H-bridge multilevel inverter. It then reviews the generalized formulation of selective harmonic elimination (SHE) for multilevel inverters. The document presents a MATLAB/Simulink model of a three-phase, five-level inverter that compares sinusoidal pulse width modulation to SHE for harmonic reduction. Simulation results show that SHE reduces THD from 71.2% to 4.66% by eliminating specific lower-order harmonics through optimization of the switching angles.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Multilevel inverters have become more popular over the years in electric high power application
with the promise of less disturbances and the possibility to function at lower switching frequencies than
ordinary two-level inverters. This paper presents information about several multilevel inverter topologies,
such as the Neutral-Point Clamped Inverter and the Cascaded Multi cell Inverter. These multilevel
inverters will also be compared with two-level inverters in simulations to investigate the advantages of
using multilevel inverters. Modulation strategies, component comparison and solutions to the multilevel
voltage source balancing problem will also be presented in this work.
Keywords — multilevel, Neutral-clamped, PWM.
This document discusses performance enhancement of a multilevel inverter using genetic algorithms. It presents an optimal solution for eliminating pre-specified harmonics from a stepped waveform generated by a multilevel inverter topology with equal DC sources. A genetic algorithm is proposed that reduces computational burden and allows for fast convergence in solving the non-linear equations involved. Simulation results show the genetic algorithm approach achieves significant improvement in harmonic profile compared to the conventional Newton-Raphson method.
Modelling and Simulation of a Sensorless Control of a True Asymmetric Cascade...IJPEDS-IAES
This paper introduces a new method to track the saliency of an AC motor fed
by a multilevel converter through measuring the dynamic current response of
the motor line currents due the IGBT switching actions. The method uses
only the fundamental PWM waveform (i.e there is no modification to the
operation of the multilevel converter) similar to the fundamental PWM
method proposed for a 2-level converter. Simulation results are provided to
demonstrate the performance of the complete sensorless speed control of a
PM motor driven by such a converter over a wide speed range. Finally the
paper introduces a comparison between the 2-level converter and the
multilevel converter in terms of the reduction of the total harmonic distortion
(THD) using the fundamental PWM method in both cases.
Asymmetrical Cascaded Multi Level Inverter using Control Freedom Pulse width ...IAES-IJPEDS
In this paper, the suggested topologies are gained by cascading a full bridge inverter with dissimilar DC sources. This topology has several new patterns adopting the fixed switching frequency, multicarrier control freedom degree with mixture conceptions are established and simulated for the preferred three-phase cascaded multilevel inverter. In outstanding switching arrangement terminations, there are convinced degrees of freedom to produce the nine level AC output voltages with terminated switching positions for producing altered output voltages. These investigations focus on asymmetrical cascaded multilevel inverter engaging with carrier overlapping pulse width modulation (PWM) topologies. These topologies offer less amount of harmonics present in the output voltage and superior root mean square (RMS) values of the output voltages associated with the traditional sinusoidal pulse width modulation. This research studies carries with it MATLAB/SIMULINK based simulation and experimental results obtained using appropriated prototype to prove the validity of the proposed concept.
Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascad...IJAAS Team
This paper presents unipolar pulse width modulation technique with sinusoidal sampling pulse width modulation are analyzed for three-phase five-level, seven-level, nine-level and eleven-level cascaded multi-level inverter. The unipolar PWM method offers a good opportunity for the realization of the Three-phase inverter control, it is better to use the unipolar PWM method with single carrier wave compared to two reference waves. In such case the motor harmonic losses will be considerably lower.The necessary calculations for generation of unipolar pulse width modulation strategies have presented in detail. The unipolar SPWM voltage switching scheme is selected in this paper because this method offers the advantages of effectively doubling the switching frequency of the inverter voltage. The cascaded multi level inverter fed induction motor is simulated and compared the total harmonic distroction for all level (five-level, seven-level, nine-level and elevel-level)of the inverter. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Application of SVM Technique for Three Phase Three Leg Ac/Ac Converter TopologyIOSR Journals
This paper presents a simulation of a three-phase three-leg AC/AC converter topology using nine IGBTs and space vector pulse width modulation (SVM) technique. The proposed topology reduces the number of switches compared to conventional back-to-back and matrix converters. Simulation results show the converter provides sinusoidal input and output voltages with unity power factor under constant frequency and variable frequency operation. Experimental results from a 5kVA prototype verify the validity of the proposed scheme.
Simulation and study of multilevel inverter (report)Arpit Kurel
The document discusses the simulation and study of a multilevel inverter. It begins with an abstract that outlines that multilevel inverters are used to convert DC power to AC power at required voltage and frequency levels for applications like motor drives and grid connections. It then discusses different multilevel inverter topologies like diode clamped, flying capacitor, and cascaded H-bridge. For this project, a three phase five level inverter is simulated using sinusoidal PWM technique in MATLAB/Simulink. The topology used is a cascaded H-bridge inverter with separate DC sources. The multilevel inverter reduces harmonic contents in the output waveform compared to a three level inverter.
The Operating Improvement of the Supply Source and the Optimization of PWM Co...IJPEDS-IAES
In this paper the operating improvement of the supply source and the
optimization of PWM control are proposed. A comparison (based on the
better operating in terms of input voltage) between the multilevel inverters
(NPC multilevel inverter and H bridge inverter) is studied. Then two control
strategies (the SPWM and the suboptimal PWM) are applied to the multilevel
inverter which has the better voltage performance. At last a comparison
between these two control techniques based on two essential points, the THD
and the output voltage value. A comparison between our results and results
taken from literature is also presented in this paper. Simulations are carried
out using PSIM environment.
Performance Evaluation of Nine Level Modified CHB Multilevel Inverter for Var...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Fuzzy Logic Controlled Harmonic Suppressor in Cascaded Multilevel InverterIJPEDS-IAES
This paper presents an investigation of seven level cascaded H-bridge (CHB)
inverter in power system for compensation of harmonics. For power quality
control a Fuzzy Logic Control (FLC) giving comparatively better harmonic
reduction than the conventional controllers. Harmonic distortion is the most
important power quality problem stirring in multilevel inverter; the
harmonics can be eliminated by an optimal selection of switching angles. A
hybrid evaluation technique evaluates the obtained optimal switching angles
that are attained from the fuzzy inference system as well as neural network.
The proposed method will be implemented in MATLAB working platform
and the harmonic elimination performance will be evaluated.
This document analyzes a transistor clamped H-bridge split phase PWM inverter. It presents the circuit diagram of the proposed inverter which uses coupled inductors to prevent short circuits and reduce reverse recovery losses. A double reference single carrier modulation technique is used to generate PWM signals from two reference signals and a triangular carrier, producing a five-level output voltage. Simulation results in MATLAB Simulink show the five-level output voltage waveform and total harmonic distortion of 8.43%, demonstrating reduced harmonics compared to conventional inverters. The proposed inverter topology and modulation control method aim to improve efficiency, reliability and output waveform quality.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance Evaluation of a Three Phase Nine Level Inverter with Reduced Sw...Scientific Review SR
This paper presents a three phase nine level cascaded H-bridge (CHB) multilevel inverter with RL load. A sinusoidal and trapezoidal PWM method is used to achieve minimum total harmonics distortion (THD) in the output current of multilevel inverters. The analysis of the output current harmonics is carried out and compared with the seven level conventional cascaded H-bridge inverters. The proposed inverter is verified through
simulation and the simulation results are compared with the conventional multilevel inverter. From the result the
proposed inverter offers much less total harmonic distortion
VARIABLE FREQUENCY DRIVE. VFDs are widely used in industrial applications for...PIMR BHOPAL
Variable frequency drive .A Variable Frequency Drive (VFD) is an electronic device used to control the speed and torque of an electric motor by varying the frequency and voltage of its power supply. VFDs are widely used in industrial applications for motor control, providing significant energy savings and precise motor operation.
Null Bangalore | Pentesters Approach to AWS IAMDivyanshu
#Abstract:
- Learn more about the real-world methods for auditing AWS IAM (Identity and Access Management) as a pentester. So let us proceed with a brief discussion of IAM as well as some typical misconfigurations and their potential exploits in order to reinforce the understanding of IAM security best practices.
- Gain actionable insights into AWS IAM policies and roles, using hands on approach.
#Prerequisites:
- Basic understanding of AWS services and architecture
- Familiarity with cloud security concepts
- Experience using the AWS Management Console or AWS CLI.
- For hands on lab create account on [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
# Scenario Covered:
- Basics of IAM in AWS
- Implementing IAM Policies with Least Privilege to Manage S3 Bucket
- Objective: Create an S3 bucket with least privilege IAM policy and validate access.
- Steps:
- Create S3 bucket.
- Attach least privilege policy to IAM user.
- Validate access.
- Exploiting IAM PassRole Misconfiguration
-Allows a user to pass a specific IAM role to an AWS service (ec2), typically used for service access delegation. Then exploit PassRole Misconfiguration granting unauthorized access to sensitive resources.
- Objective: Demonstrate how a PassRole misconfiguration can grant unauthorized access.
- Steps:
- Allow user to pass IAM role to EC2.
- Exploit misconfiguration for unauthorized access.
- Access sensitive resources.
- Exploiting IAM AssumeRole Misconfiguration with Overly Permissive Role
- An overly permissive IAM role configuration can lead to privilege escalation by creating a role with administrative privileges and allow a user to assume this role.
- Objective: Show how overly permissive IAM roles can lead to privilege escalation.
- Steps:
- Create role with administrative privileges.
- Allow user to assume the role.
- Perform administrative actions.
- Differentiation between PassRole vs AssumeRole
Try at [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
Rainfall intensity duration frequency curve statistical analysis and modeling...bijceesjournal
Using data from 41 years in Patna’ India’ the study’s goal is to analyze the trends of how often it rains on a weekly, seasonal, and annual basis (1981−2020). First, utilizing the intensity-duration-frequency (IDF) curve and the relationship by statistically analyzing rainfall’ the historical rainfall data set for Patna’ India’ during a 41 year period (1981−2020), was evaluated for its quality. Changes in the hydrologic cycle as a result of increased greenhouse gas emissions are expected to induce variations in the intensity, length, and frequency of precipitation events. One strategy to lessen vulnerability is to quantify probable changes and adapt to them. Techniques such as log-normal, normal, and Gumbel are used (EV-I). Distributions were created with durations of 1, 2, 3, 6, and 24 h and return times of 2, 5, 10, 25, and 100 years. There were also mathematical correlations discovered between rainfall and recurrence interval.
Findings: Based on findings, the Gumbel approach produced the highest intensity values, whereas the other approaches produced values that were close to each other. The data indicates that 461.9 mm of rain fell during the monsoon season’s 301st week. However, it was found that the 29th week had the greatest average rainfall, 92.6 mm. With 952.6 mm on average, the monsoon season saw the highest rainfall. Calculations revealed that the yearly rainfall averaged 1171.1 mm. Using Weibull’s method, the study was subsequently expanded to examine rainfall distribution at different recurrence intervals of 2, 5, 10, and 25 years. Rainfall and recurrence interval mathematical correlations were also developed. Further regression analysis revealed that short wave irrigation, wind direction, wind speed, pressure, relative humidity, and temperature all had a substantial influence on rainfall.
Originality and value: The results of the rainfall IDF curves can provide useful information to policymakers in making appropriate decisions in managing and minimizing floods in the study area.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Applications of artificial Intelligence in Mechanical Engineering.pdfAtif Razi
Historically, mechanical engineering has relied heavily on human expertise and empirical methods to solve complex problems. With the introduction of computer-aided design (CAD) and finite element analysis (FEA), the field took its first steps towards digitization. These tools allowed engineers to simulate and analyze mechanical systems with greater accuracy and efficiency. However, the sheer volume of data generated by modern engineering systems and the increasing complexity of these systems have necessitated more advanced analytical tools, paving the way for AI.
AI offers the capability to process vast amounts of data, identify patterns, and make predictions with a level of speed and accuracy unattainable by traditional methods. This has profound implications for mechanical engineering, enabling more efficient design processes, predictive maintenance strategies, and optimized manufacturing operations. AI-driven tools can learn from historical data, adapt to new information, and continuously improve their performance, making them invaluable in tackling the multifaceted challenges of modern mechanical engineering.
Build the Next Generation of Apps with the Einstein 1 Platform.
Rejoignez Philippe Ozil pour une session de workshops qui vous guidera à travers les détails de la plateforme Einstein 1, l'importance des données pour la création d'applications d'intelligence artificielle et les différents outils et technologies que Salesforce propose pour vous apporter tous les bénéfices de l'IA.
Discover the latest insights on Data Driven Maintenance with our comprehensive webinar presentation. Learn about traditional maintenance challenges, the right approach to utilizing data, and the benefits of adopting a Data Driven Maintenance strategy. Explore real-world examples, industry best practices, and innovative solutions like FMECA and the D3M model. This presentation, led by expert Jules Oudmans, is essential for asset owners looking to optimize their maintenance processes and leverage digital technologies for improved efficiency and performance. Download now to stay ahead in the evolving maintenance landscape.
Design and optimization of ion propulsion dronebjmsejournal
Electric propulsion technology is widely used in many kinds of vehicles in recent years, and aircrafts are no exception. Technically, UAVs are electrically propelled but tend to produce a significant amount of noise and vibrations. Ion propulsion technology for drones is a potential solution to this problem. Ion propulsion technology is proven to be feasible in the earth’s atmosphere. The study presented in this article shows the design of EHD thrusters and power supply for ion propulsion drones along with performance optimization of high-voltage power supply for endurance in earth’s atmosphere.
1. Abstract—This paper presents a 5-level three-phase cascaded
hybrid multilevel inverter that consists of a standard 3-leg (one
leg for each phase) and H-bridge in series with each inverter leg
with separate DC voltage sources, 24V and 48V. The control
signals for this hybrid multilevel inverter are implemented by a
FPGA controller using PWM signal modulated technique and
digital technique. A 5-level three-phase cascaded hybrid
multilevel inverter model based on PSCAD/EMTDC is
presented in this paper. The proposed hybrid multilevel
inverter is described in detail that it is verified experimentally
in three types of load; 18W fluorescent lamp-ballast, RL, and
1HP 3-phase induction motor; without filtering. Results of the
experiment; the output waveform of line-line and phase
voltages has 5 levels that percent of THD is between 15.6% and
18.3%, the output waveform of phase current is close to
sinusoidal that percent of THD is between 2.7% and 4.2%.
Index Terms—Hybrid multilevel inverter, PSCAD/EMTDC,
FPGA controller, h-bridge.
I. INTRODUCTION
A multilevel inverter is a power electronic converter built
to synthesize a desired AC voltage from several levels of DC
voltages which the DC levels were considered to be identical
in that all of them were batteries, solar cells, capacitors, etc.
The multilevel inverter has gained much attention in recent
years due to its advantages in lower switching loss better
electromagnetic compatibility, higher voltage capability, and
lower harmonics [1]-[3]. Several topologies for multilevel
inverters have been proposed; the most popular being the
diode-clamped [4], [5], flying capacitor [6], and cascade H-
bridge [7] structures. Besides the three basic multilevel
inverter topologies; other multilevel converter topologies
have been proposed, most of these are hybrid circuits that are
combinations of two of the basic multilevel topologies. The
schemes of multilevel inverters are classified in to two types
the multicarrier sub-harmonic pulse width modulation (MC-
SH PWM) and the multicarrier switching frequency optimal
pulse width modulation (MC-SFO PWM) [8], [9]. The
MC-SH PWM cascaded multilevel inverter strategy reduced
total harmonic distortion and the MC-SFO PWM cascade
multilevel inverter strategy enhances the fundamental output
voltage [10].
The THD will be decreased by increasing the number of
levels. It is obvious that an output voltage with low THD is
Manuscript received August 4, 2011; revised September 31, 2011.This
work was supported by the Department of Electrical Engineering, Faculty of
Engineering at Si Racha, Kasetsart University Si Racha Campus, and
Thailand.
P. Thongprasri is with the Department of Electrical Engineering, Faculty
of Engineering at Si Racha, Kasetsart University Si Racha Campus,
Chonburi, Thailand (e-mail: sfengprt@ src.ku.ac.th).
desirable, but increasing the number of levels needs more
hardware, also the control will be more complicated. It is a
tradeoff between price, weight, complexity and a very good
output voltage with lower THD. Fig. 1 shows single phase
topology of the diode Clamped, flying capacitor, a cascaded
H-bridge, and cascade hybrid multilevel inverter that they
have the number of switches, diodes, and capacitors as shown
in table I (a 5- level multilevel inverter).
dcV
1S
2S
3S
4S
5S
6S
7S
8S
oV
1C
2C
3C
4C
dcV
1S
2S
3S
4S
5S
6S
7S
8S
1C
2C
3C
4C
5C
6C
7C
8C
9C
10C oV
(a) Diode Clamped (b) Flying capacitor
multilevel inverter multilevel inverter
dcV
dcV
1S 2S
3S 4S
5S 6S
7S 8S
oV
2
dcV
dcV
1S 2S
3S 4S
5S
oV
6S
1C
2C
(c) Cascaded H-bridge (d) Cascaded Hybrid
multilevel inverter multilevel inverter
Fig. 1. One phase of a 5-level multilevel inverter.
TABLE I: COMPONENTS OF ONE PHASE OF A-5 LEVEL
MULTILEVEL INVERTER
Types of multilevel
inverter
Number of
switches
Number of
diodes
Number of
capacitors
Diode Clamped 8 12 4
Flying capacitor 8 - 10
Cascaded H-bridge 8 - -
Cascade hybrid 6 - 2
In this paper, the proposed a 5-level three-phase cascaded
hybrid multilevel inverter includes a standard 3-leg inverter
(one leg for each phase) and H-bridge in series with each
inverter leg as shown in Fig. 2. To develop the model of a
5-level cascaded hybrid multilevel inverter, a simulation is
done based on PSCAD/EMTDC. All signals for controlling
the hybrid multilevel inverter are created by a FPGA
controller using PWM signal modulated technique and digital
technique. The prototype is tested with 3 types of load; a 18W
fluorescent lamp-ballast, RL (R is 265 Ω , L is 0.125 H ),
and a 1HP 3-phase induction motor (no load); without
filtering.
A 5-Level Three-Phase Cascaded Hybrid
Multilevel Inverter
P. Thongprasri
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
789
2. II. OPERATION PRINCIPLE OF
THE HYBRID MULTILEVEL INVERTER
1aS
2aS
3aS
4aS
1bS
2bS
3bS
4bS
1cS
2cS
3cS
4cS
LOAD
aV
bV
cV
dcV 1S
2S
3S
4S
5S
6S
2
dcV
2
dcV
2
dcV
Fig. 2. Topology of a 5-level three-phase cascaded hybrid
multilevel inverter.
Fig. 2 shows the topology of the proposed a 5-level
3-phase cascaded hybrid multilevel inverter. Single phase
topology of the hybrid multilevel inverter is shown in Fig. 3;
the bottom is one leg of a standard 3-leg inverter with a dc
power source ( dcV ), the top is a hybrid in series with each
standard inverter leg that the H-bridge inverter can use a
separate dc power source ( 2/dcV ). Considering the output
voltage 1v of this leg is either 2/dcV+ when 1S closed or
2/dcV− when 2S closed. This leg is connected in series with
a full H-bridge inverter, then the output voltage 2v of the
H-bridge inverter is either 2/dcV+ when 41, aa SS closed, 0
when 31, aa SS or 42, aa SS closed, or 2/dcV− when 32, aa SS
closed. An example output waveform that this topology can
achieve as shown in the Fig. 4, when the output voltage
21 vvv += is required to be zero, one can either set
2/1 dcvv += and 2/2 dcvv −= or 2/1 dcvv −= , and 2/2 dcvv += .
In [11], several different two-level multilevel carrier-based
PWM techniques have been extend for controlling the active
devices in a multilevel converter, the most popular and
easiest technique to implement uses several triangle carrier
signals and one reference, or modulation, signal per phase. In
order to achieve better dc link utilization at high modulation
indices, the sinusoidal reference signal can be injected by a
third harmonic with a magnitude equal to 25% of
fundamental.
Fig. 5 shows MC-SH PWM of a 5-level inverter, m-1
carriers with the same frequency cf and the same amplitude
cA are dispose such that the bands they occupy are
contiguous, The reference waveform has peak-to-peak
amplitude mA , a frequency mf , and its zero centered in the
middle of the carrier set, The reference is continuously
compared with each of the carrier signals. If the reference is
greater than a carrier signal, then the active device
corresponding to that carrier is switched on, and if the
reference is less than a carrier signal, then the active device
corresponding to that carrier is switched off.
2
dcV
1aS
2aS
3aS
4aS
dcV
1S
2S
1v
2v
i
v
Fig. 3. Single phase topology of the hybrid multilevel inverter.
21 vvv +=
i
dcv+
dcv−
2/dcv+
π π2
2/dcv−
Fig. 4. Output waveform of the hybrid multilevel inverter.
Fig. 6 shows the relationship between the sinusoidal
reference signal and the triangular signal which used to create
the PWM signal; the output of the PWM signal is either 1,
when trictrl VV > or 0 when, trictrl VV < , and the PWM signal
width can be written as equation (1).
10; ≤≤⋅= ctrltrictrlPWM ATAT (1)
Nomenclature:
PWMT Width of the PWM signal.
ctrlA Height of the control signal.
triT Period of the triangular signal.
ctrlV Output voltage of the control signal.
triV Output voltage of the triangular signal.
0
1
2
2−
1−
Fig. 5. MC-SH PWM of a 5-level inverter.
Fig. 6. The relationship between the sinusoidal referencesignal and the
triangular signal.
0
controlV triV
trictrl VV >
PWM
rA
triT
ctrlT
0
1
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
790
3. 2/dcV+
2/dcV−
0
0 6/π 6/5π π
2/dcV+
2/dcV−
0
π26/7π 6/10π
2/dcV+
2/dcV−
0
dcV+
dcV−
inverterbridgeHforSignals −
inverterphaseforSignals −3
inverterhybridofwaveformOutput
Fig. 7. Output waveform of the 5-level hybrid multilevel inverter.
0
6
π
6
5π π
6
7π
6
10π π2
PWM
0
0
1
1v
2v
dcV−
dcV
0
1
0
1
0
1
.Mod
Output
)( 3v
Fig. 8. Signals for controlling the hybrid multilevel inverter.
Fig. 7 shows output waveform of the 5-level cascaded
hybrid multilevel inverter that it is used to be the pattern to
create the control signal for hybrid multilevel inverter. PWM
),( 3v ,1v and 2v signals shown in Fig. 8 are the parameters
in digital process to create all control signals that they are
shown in table II. Modulated signal is created as equation (2)
and (3), amplitude modulation index am can be found at the
following equation (4); am in this paper is 0.8.
⎪
⎩
⎪
⎨
⎧
≤<
<≤
−=
πω
π
π
ω
ω
t
t
tTmT triaPWM
6
5
6
0
;))sin(21( (2)
6
5
6
;)1)sin(2(
π
ω
π
ω ≤≤−= ttTmT triaPWM (3)
tri
ctrl
a
V
V
m = (4)
TABLE II: DIGITAL PROCESS OF THE CONTROL SIGNALS.
Electronic switch devices Digital process
1s 1v
2s 1v
1as ))()(( 21213 vvvvv ⋅+⋅⋅
2as ))()(( 21213 vvvvv ⋅+⋅⋅
3as ))()(( 21213 vvvvv ⋅+⋅⋅
4as ))()(( 21213 vvvvv ⋅+⋅⋅
III. SIMULATION RESULTS
The simulation model based on PSCAD/EMTDC is shown
in appendix; dcV are 24V and 48V, RL load (R is 265 Ω , L
is 0.125 H ), sinusoidal reference signal frequency is 50Hz,
carrier signal frequency is 2,500Hz, and am is 0.8.
.Mod
PWM
2v
1v
)( 3v
Fig. 9. Simulation result of ,1v ,2v ,3v and modulated signal.
Results of the simulation; Fig. 9 shows modulated signal, ,1v
2v , and PWM )( 3v signals. Fig. 10 shows all control signals
for the power electronic switches. Fig. 11 shows the output
waveform of phase voltage and phase current.
1S
2S
1aS
2aS
3aS
4aS
Fig. 10. Simulation result of all control signals for electronic switch
devices (IGBTs).
aV
bV
cV
ai bi ci
Fig. 11. Simulation result of phase voltage and phase current when load is
RL (R is 265 Ω , L is 0.125 H ).
IV. EXPERIMENTAL RESULTS
Fig. 12 shows the topology of the hybrid multilevel
inverter with separate DC voltage sources ;24V and 48V; that
the IGBTs (GT60M303) are used to be power electronic
switches in the H-bridge inverter, and the IGBT modules
(CM75DU-12H) are used to be power electronic switches in
the 3-phase inverter. The output voltage of the hybrid
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
791
4. multilevel inverter is connected to a 3-phase step up
transformer (55/380V/50Hz, Y-Y) rated 1.5kW. Prototype of
the 1kW 5-level three-phase cascaded hybrid multilevel
inverter as shown in Fig. 13 has been built in order to verify
the proposed hybrid multilevel inverter. The control signals
in this paper are created by the field programmable gate array
(FPGA, discovery–III XC3S200 model) controller. Fig. 14
shows three signals; PWM )( 3v , 1v , and 2v ; for the hybrid
multilevel inverter, modulation index is 0.8.
1aS
2aS
3aS
4aS
1bS
2bS
3bS
4bS
1cS
2cS
3cS
4cS
V
YY
380/55
−
aV
bV
cV
1S
2S
3S
4S
5S
6S
V24 V12 V12
V48
inverterphase−3
inverterbridgeH −
R
s
T
N
rtransformeupstep
Fig. 12. Topology of the hybrid multilevel inverter with separate DC voltage
sources; 24V and 48V.
inverterbridgeH −
inverterphase−3FPGA
dc
rtransformeupstepphase
andsourcesdc
−3
Fig. 13. Prototype of the 5-level 3-phase cascaded hybrid multilevel inverter.
Fig. 15 shows prototype of the 1kW 5-level three-phase
cascaded hybrid multilevel inverter with a 18W fluorescent
lamp-ballast load. Fig. 16 shows the experimental results
including phase voltage and phase current; the output phase
voltage waveform has 5 levels that its rms voltage is 225V,
and the phase current waveform is close to sinusoidal that its
rms current is 360mA. Fig. 17 shows the experimental result
including output waveform of line-line voltage and line-line
that voltage THD is 17.4%, 16.6%, and 18%.
Fig. 18 shows prototype of the 1kW 5-level three-phase
cascaded hybrid multilevel inverter with RL load (R is 265
,Ω L is 0.125 H ). Fig. 19 shows the experimental results
including phase voltage and phase current; the output phase
voltage waveform has 5 levels that its rms voltage is 195V,
and the phase current waveform is close to sinusoidal that its
rms current is 708mA. Fig. 20 shows the experimental result
including the phase voltage THD of 17% and phase current
THD of 2.7%. Fig. 21 shows the experimental result
including output waveform of line-line voltage that line-line
voltage THD is 17.9%, 17.4%, and 18.3%.
1v
2v
3v
Fig. 14. The control signals for hybrid multilevel inverter are created by
FPGA ( am =0.8).
Fig. 15. Prototype of the 1kW 5-level three-phase cascaded hybrid multilevel
inverter with 3 fluorescent lamp-ballast loads.
Fig. 22 shows prototype of the 1kW 5-level three-phase
cascaded hybrid multilevel inverter with a 3-phase induction
motor load (no load). Fig. 23 shows the experimental results
including phase voltage and phase current; the output phase
voltage waveform has 5 levels that its rms voltage is 206V,
and the phase current waveform is close to sinusoidal that its
rms current is 786mA, and the output frequency is 50Hz. Fig.
24 shows the experimental result including the phase voltage
THD of 16%, and phase current THD of 4.2%. Fig. 25 shows
the experimental result including output waveform of
line-line voltage that line-line voltage THD is 16.2%, 15.6%,
16.7%, and the output frequency is 50 Hz.
Fig. 16. The output waveform of phase voltage and phase current (The top is
phase voltage that its rms voltage is 225V, the bottom is phase current that its
rms current is 360mA).
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
792
5. Fig. 17. The output waveform of line-line voltage that line-line voltage THD
is 17.4%, 16.6%, and 18%. The output frequency is 50Hz.
Fig. 18. Prototype of the 1kW 5-level three-phase cascaded hybrid multilevel
inverter with RL load (R is 265 Ω , L is 0.125 H ).
Fig. 19. The output waveform of phase voltage and phase current (The top is
phase voltage that its rms voltage is 195V, the bottom is phase current that its
rms current is 708mA).
Fig. 20. Phase voltage THD of 17%, phase current THD of 2.7%, the output
frequency is 50 Hz. (RL load, R is 265 Ω , L is 0.125 H ).
Fig. 21. The output waveform of line-line voltage that line-line voltage THD
is 17.9%, 17.4%, and 18.3%. The output frequency is 50Hz.
Fig. 22. Prototype of the 1kW 5-level three-phase cascaded hybrid multilevel
inverter with a 3-phase induction motor rated 1HP load (no load).
Fig. 23 . The output waveform of phase voltage and phase current (The top is
phase voltage that its rms voltage is 206V, the bottom is phase current that its
rms current is 786mA).
Fig. 24. The output waveform of phase voltage THD of 16%, phase current
THD of 4.2%. The output frequency is 50 Hz.
Fig. 25. The output waveform of line-line voltage that line-line voltage THD
is 16.2%, 15.6%, 16.7%. The output frequency is 50Hz.
V. CONCLUSION
Prototype of the 5-level three-phase cascaded hybrid
multilevel inverter consists of a 3-phase inverter and 3
H-bridge inverters that it uses separate dc power sources;
24V and 48V. The control signals for power electronic
switches are created by FPGA controller using PWM signal
modulated technique and digital technique. The prototype is
tested with three types of load; 18W fluorescent ballast-lamp,
RL, and 3-phase induction motor rated 1HP; without filtering.
Results of the test; the output line-line and phase voltages has
5 levels that its THD voltage is between 15.6% and 18.3%,
the output waveform of phase current is close to sinusoidal
that its THD current is between 2.7% and 4.2%.
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
793
6. APPENDIX
Fig. 26. The simulation model of a 5-level three- phase cascaded
multilevel inverter based on pscad/emtdc (single phase).
ACKNOWLEDGMENT
The author would like to thank the Faculty of
Engineering at Si Racha, Kasetsart University Si Racha
Campus, THAILAND, for instrument support on this
research.
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P. Thongprasri was born in Suphanburi,
Thailand, on June 19, 1971. He received the
B.Eng. degree in electronic engineering and
M.Eng. degree in electrical Engineering from
King Mongkut Institute of Technology
Ladkrabang, Thailand, in 1995 and 2005,
respectively. He is currently lecturer at the
Department of Electrical Engineering, Faculty of Engineering at Si Racha,
Kasetsart University Si Racha Campus, Thailand. His research interests
are Power Converters, Power Electronics, Robotics, Applications of
Microcontroller and FPGA controller.
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
794