This presentation discusses the details of FPGA architecture, its design flow, applications etc

1. FPGA: Architecture and
Applications
Sudhanshu Janwadkar
SV National Institute of Technology, Surat
May 3rd, 2020

2. What are FPGAs?
 FPGA : Field Programmable Gate Array.
 It is a type of programmable chip.
 FPGAs contain programmable logic blocks and
interconnection circuits.
 These can be programmed or reprogrammed to the
required functionality after manufacturing.

3. What are FPGAs?
 Field-programmable gate arrays (FPGAs) act as the
boundary between hardware and software.
 Microcontrollers program the chip with a series of
instructions. However, FPGA creates logic
structures built from gates inside the chip, in
accordance with the logic to be implemented.
 Therefore, they are customizable circuits
- i.e. They can be updated by designers after
manufacturing or deployment in the field.

4. FPGA Boards
 FPGAs are available as part of circuit boards which
contain multiple optional other peripherals such as
switches, LEDs, 7-segment displays, ADCs and
DACs, VGA, etc.
 Examples:
Name: Nexys- A7 Mimas A7 Zynq-700
Manufacturer: Digilent Inc. Numato Lab Digilent
Inc.
FPGAs

5. FPGAs versus ASICs
 The major advantage of FPGAs over ASIC is its
programmability feature and low time to market.
 ASICs takes months to manufacture and are
not flexible in terms of functionality.
 The total design cost of ASIC is higher than FPGA,
however, FPGA have a higher per unit cost than
ASICs.
 Once designed and verified, ASICs can be
produced in huge quantities at very low costs,
almost 100 times cheaper than FPGAs.
 FPGAs consume more area and are many folds
power hungry than ASICs.
 Despite all, FPGA serve as most popular platform for
Rapid prototyping of FPGAs.

6. FPGA Architecture
 The FPGA Architecture consists of three major
components:
1. Configurable Logic Blocks, which implement logic
functions
2. Programmable interconnects
3. IO blocks, which are used to make off-chip connections
IO blocks
Configurable Logic Blocks
Programmable Interconnects

7. Configurable Logic Blocks
 Basic computation (and storage) elements inside FPGA.
 Contains LUTs (Look-up Tables) which compute the logic output,
Flip-flops and Multiplexers.
 LUT implements the combinational logical functions; the MUX is
used for selection logic, and D flip flop stores the output of the LUT.
 The basic building block of the FPGA is the Look Up Table based
function generator. The number of inputs to the LUT vary from 4 to 6
or even more.

8.  Modern FPGAs contain a heterogeneous mixture of
different blocks like dedicated memory blocks,
multiplexers.
 Configuration memory is used throughout the logic blocks
to control the specific function of each element.
 Present FPGA consists of about hundreds or thousands
of configurable logic blocks.
 For configuring the FPGA, software such as Xilinx ISE
are used. These software generate a bitstream file, which
then configures the logic blocks (LUTs) and the
interconnects.

9. Programmable Interconnects
 Interconnects establish the connection between
configurable logic blocks and Input / Output blocks to
complete a user-defined design unit.
 It consists of multiplexers, pass transistors and tri-
state buffers.
 Pass transistors and multiplexers are used in a logic
cluster to connect the logic elements.

10. IO Blocks
 Used to interface the logic blocks and routing
architecture to the external components.
 The I/O pad and the surrounding logic circuit form as
an I/O cell.
 These cells consume a large portion of the FPGA’s
area.

11.  With advancement, the basic FPGA Architecture has
developed through the addition of more specialized
programmable function blocks.
 The special functional blocks like ALUs, block RAM,
multiplexers, DSP-48, and microprocessors have been
added to the FPGA, due to the frequency of the need for
such resources for applications.

12. FPGA Design Flow
FPGA design comprises of :
1. design entry
2. design synthesis
3. design implementation
4. device programming and
5. design verification.
Design verification includes:
1. functional verification and
2. timing verification

13. Design Entry
 The design entry is done in different techniques like:
1. schematic based
2. hardware description language (HDL)
3. combination of both etc.
 If the designer wants to deal with hardware, then the
schematic entry is a good choice.
 If the designer thinks the design in an algorithmic
way, then the HDL is the better choice.

14. Design Synthesis
 This process translates VHDL code into a device
netlist format, i.e., a complete circuit with logical
elements.
 The design synthesis process will check the code
syntax and analyze the hierarchy of the design
architecture.
 This ensures the design optimized for the design
architecture.
 The netlist is saved as Native Generic Circuit (NGC)
file.

15. Design Implementation
 The implementation process consists of
1. Translate
 This process combines all the input netlists to the logic design
file which is saved as NGD (Native Generic Database) file.
Here the ports are assigned to the physical elements like pins,
switches in the design. This is stored in a file called User
Constraints File (UCF).
2. Map
 Mapping divides the circuit into sub-blocks such that they can
be fit into the FPGA logic blocks. Thus this process fits the
logic defined by NGD into the combinational Logic Blocks,
Input-Output Blocks and then generates an NCD file, which
represents the design mapped to the components of FPGA.
3. Routing
 The routing process places the sub-blocks from the mapping
process into the logic block according to the constraints and
then connects the logic blocks.

16. Device Programming
 The routed design must be loaded into the FPGA.
 This design must be converted into a format
supported by the FPGA.
 The routed NCD file is given to the BITGEN
program, which generates the BIT file.
 This BIT file is configured to the FPGA.

17. Design Verification
Design Verification is done at various stages.
1. Functional Simulation
 Functional simulation is performed post-translation
simulation. It gives the information about the logical
operation of the circuit.
2. Static Timing Simulation
 This is done post mapping. Post map timing report
gives the signal path delays. After place and route,
timing report takes the timing delay information. This
provides a complete timing summary of the design.

18. FPGA Applications
 Application domains:

19. FPGA Applications
 Emulation of entire large hardware systems via the
use of many interconnected FPGAs.
 ASIC prototyping or SoC prototyping
- method to prototype SoC and ASICs on FPGAs
for hardware verification and early software
development.
 Parallel Computing to meet requirements in machine
learning, computer vision, video surveillance etc.
 FPGAs provide a unique combination of highly
parallel custom computation and low-cost
computation.