1. An ISO 21001:2018
certified institution
S. S. Education Trust’s CET Code: E-175 (UG)/T-942 (PG)
S. G. BALEKUNDRI INSTITUTE OF TECHNOLOGY
Shivabasavanagar, Belagavi- 590 010, Karnataka- India
• Approved by AICTE New Delhi • Recognised by Govt. of Karnataka • Affiliated to V T U, Belagavi
Department of Electronics & Communication Engineering
Email: hod-ec@sgbit.edu.in, Dept. Extn.: 520
Accredited by NBA, New Delhi
Project Phase – 1/2 Presentation
On
“Design And Implementation of Low Power
PLL Using CMOS 45nm Technology"
Group
No. 16
Name of the Student University SeatNumber
Chintamani Khemalapure 2BU19EC018
Harshita Hiremath 2BU19EC023
Niha Jadhav 2BU19EC039
Under the Guidance of
Prof. Narayan A.B.
AssistantProfessor, Dept. of E&CE
S. G. Balekundri Institute of Technology, Belagavi-10
12/11/2022 1
2. Introduction
Literature Survey
Problem Statement
Objectives
Proposed Methodology
Advantages & Disadvantages
Applications
Conclusion & Future Scope
References
12/11/2022 Design And Implementation of Low Power PLL Using CMOS 45nm Technology 2
Contents
3. • PLL is closed loop control system.
• Compares output phase with input phase
• Maintains phase and frequency constant.
• PLL Contains 4 Blocks .
• Phase/Frequency Detector, Charge Pump, LPF, CSVCO.
• Comparison Process is performed by PFD
• Cadence virtuoso is used to implement
Design And Implementation of Low Power PLL Using CMOS 45nm Technology
12/11/2022 3
Introduction
4. S.
No
Authors Title of Paper Methodology Limitations Year
01 Pooja
Thool,
Dr.J. D
Dhande,
Prof. Y. A.
Sadawarte,
“A Review on Design
and Analysis of Low
Power PLL for Digital
Application and Multiple
Clocking Circuits”
CMOS circuit is
converted into
physical layout. After
cascading the layout
of each element, final
layout is obtained.
Required
more area
due to
multiple
freq. output
design
April
2022
02 Pawan
Srivastava,
Dr. Ram
Chandra
Singh
Chauhan,
“Design of Power
Efficient Phase
Frequency Detector and
Voltage Controlled
Oscillator for PLL
Applications in 45 nm
CMOS Technology”
A proposed phase
frequency detector is
given with 16T which
Has low power
consumption
Low speed
and Area
required is
more due to
16T PFD.
Nov
2021
12/11/2022 Design And Implementation of Low Power PLL Using CMOS 45nm Technology 4
Literature Survey
5. Design And Implementation of Low Power PLL Using CMOS 45nm Technology
12/11/2022 5
S.
N
o
Authors Title of Paper Methodology Limitations Year
03 Govind S
Patel,
Suman L
Tripathi,
“Design and
Analysis of Power
an Efficient Hybrid
PLL For
Communication
System”
Xlinx tool is used
to simulate and
FPGA for
implementation
Charge pump is
not used.
Aug
2019
04 Prashant
Thane Patil,
Dr. Mrs.
Vaishali
Ingale,
"Design of a Low
Power PLL in 90nm
CMOS Technology"
The Cadence
Virtuoso tool
using GPDK 90nm
CMOS
Technology
Area Required
and slow
compared to
45nm Technology
March
2019
5
Literature Survey
6. “In the wireless communication and RF
applications we need synchronized and high frequency signal.
But the reference signal is stable and has low frequency. we
need low Power consumption, high speed, Less area device
.To over come these problem the PLL can be designed and
implemented.”
Design And Implementation of Low Power PLL Using CMOS 45nm Technology
12/11/2022 6
Problem Statement
7. • The main objective of this project is to produce high
frequency and synchronized signal with a reference signal .
• Design high speed, Low power consumption PLL.
• To reduce the area of PLL in Virtuoso Layout.
• To compare the Simulation Result of PLL Design for
different Technology.
• Use the new MGDI(modified gate diffusion input)
Technology to design PLL.
Design And Implementation of Low Power PLL Using CMOS 45nm Technology
12/11/2022 7
Objectives
8. 12/11/2022 Design And Implementation of Low Power PLL Using CMOS 45nm Technology 8
Proposed Methodology
Out
Down
Up
Reference
signal Phase/Frequency
Detector
Charge
Pump
Low pass
filter
Current starved
VCO
Frequency
Divider
9. Advantages:
• It produce synchronized and high frequency signal
• High reliability, Stability and easy Adjustment
• Provide Different options for clock configurations to
developer.
• High speed and low power consumption
Disadvantages:
• Noise sensitive
• High cost due to the complexity of the circuitry.
Design And Implementation of Low Power PLL Using CMOS 45nm Technology
12/11/2022 9
Advantages & Disadvantages
10. 1. Synchronization and Demodulation circuits.
2. Clock Recovery
3. Noise and Jitter reduction
4. Frequency synthesizer
5. Microprocessors(clock multiplier and Clock distribution)
Design And Implementation of Low Power PLL Using CMOS 45nm Technology
12/11/2022 10
Applications
11. Conclusion:
The Phase detector, Charge Pump , LPF,
CSVCO can be designed using MGDI technique and All these
circuits are simulated using Cadence Virtuoso GPDK45nm
CMOS technology with supply voltage 1V.With this technique
The area and power consumption can be reduced.
Future scope:
• By using different designing technology, Area and Power
consumption can reduced more.
• We can use lower technology than GPDK 45nm.
Design And Implementation of Low Power PLL Using CMOS 45nm Technology
12/11/2022 11
Conclusion & Future Scope
12. 1. Pooja Thool, Dr. J. D Dhande, Prof. Y. A. Sadawarte, “A Review on Design and Analysis of
Low Power PLL for Digital Application and Multiple Clocking Circuits”, IJRASET Wardha,
Volume 10 Issue IV April 2022
2. Pawan Srivastava, Dr. Ram Chandra Singh Chauhan, “Design of Power Efficient Phase
Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS
Technology”, Journal of University of Shanghai for Science and Technology, Volume 23,
Issue 11, November - 2021
3. Prashant Thane Patil, Dr. Mrs. Vaishali Ingale, "Design of a Low Power PLL in 90nm CMOS
Technology", IEEE- 2019 5th International Conference for Convergence in Technology (I2CT)
Pune, India. Mar 29-31, 2019
4. Dr. D. R. V. A. Sharath Kumar1, Mr. J. Nageswara Reddy2, Mr. A. Dileep, “Design of PLL
Using CSVCO in 45N m Technology’’, International Journal of Research in Signal Processing,
Computing & Communication System Design, volume 2, Issue 1 & 2,2018.
5. Govind S Patel, Suman L Tripathi, Sanjeet K Sinha and Sobhit Saxena, ''Design and Analysis
of Power an Efficient Hybrid PLL For Communication System, THINK INDIA Journal, Vol-
22-Issue-16-August-2019
6. Nabihah Ahmad et al., " Charge Pump and Loop Filter for Low Power PLL Using 130nm
CMOS Technology", J. Phys.: Conf. Ser. 1049 012060, 2018.
Design And Implementation of Low Power PLL Using CMOS 45nm Technology
12/11/2022 12
References
