This document presents a VLSI design and implementation of a two-dimensional FIR filter architecture using Canonic Signed Digit (CSD) representation. The objectives are to design an efficient symmetry FIR filter using McClellan transform, represent filter coefficients in CSD format to reduce adders, and implement an area-delay-power efficient direct form VLSI architecture. This will help design 2D FIR filters more efficiently by reducing area, delay, and power consumption through a multiplier-less design approach using CSD. The methodology involves producing filter coefficients in MATLAB, converting them to binary using CSD codes, designing the architecture, generating Verilog code, and obtaining area-power reports using CAD tools.

1. K.L.E SOCIETY’S
K.L.E INSTITUTE OF TECHNOLOGY
HUBBALLI-580027
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
(NBA ACCREDITED)
PRESENTED BY:
Kavita S Bagewadi : 2KE20EC042
Namrata P Bistannavar : 2KE20EC052
G Nikitha : 2KE20EC030
Keerti Katti : 2KE20EC043
GUIDED BY : Mrs. Anusha Reddy
DATE:03-11-2023
VLSI Design and Implementation of Two Dimensional
FIR filter architectures using CSD.

2. CONTENT OF THE PRESENTATION
SL.NO CONTENT
01. ABSTRACT
02. PROBLEM DEFINATION
03. OBJECTIVE
04. SCOPE
05. LITERATURE SURVEY
06. BIBILOGRAPHY
2

3. INTRODUCTION
• The FIR filter is commonly used in many applications such as signal
processing, communication, and multimedia applications.
• With the use of less multipliers, adders and subtractors the FIR filter can be
implemented in less area and its consumes less power.
• To reduce the number of multipliers, the symmetry is incorporated in the filter
coefficients while designing the filter.
• To optimize the filter architecture, the Canonic Signed Digit (CSD) number
format is considered to represent the filter coefficients.
3

4. CONT..
• The Canonic Signed Digit representsation minimizes the number of adders and
multiplier operations leading to a more hardware-efficient implementation.
• The VLSI architecture of symmetry FIR filter is implemented using Direct form.
4

5. PROBLEM DEFINITION
• In the existing 2D FIR filters, multipliers are being used.
• The physical multiplier block is large in size and thus occupies more area on the
chip.
• Especially for long filter lengths or high filter orders, hardware complexity
increases as the no. filters implementation increases.
• So eventually area, processing delays(affects real time applications) and power
consumption of the chip increases.
5

6. LITERATURE SURVEY
Name Year Proposed Methods Proposed Drawbacks
Pei and Shyu 2004 Introduced the eigen filter
based technique to design
2D FIR filter that computes
the optimal parameters of
McClellan transformation
This method may not
provide the optimal solution
for specific filter design
requirements and users may
need to employ additional
techniques to meet their
design specifications.
Mohanty, B. K., Meher, P.
K., Al - Maadeed & Amira.
2013 The memory-efficient 2D
FIR filters in-separable and
non-separable structures.
Multipliers are complex
blocks and occupies more
area and consumes large
power.
Bindima and Elias 2016,2017,2019 Low complexity circular and
fan type 2D FIR filter
design.
Focused on the design of
higher-order filters and the
design required a huge
number of multipliers.
6

7. OBJECTIVES
• To design an efficient symmetry FIR filter using Kth-McClellan Transform
technique.
• To represent the filter coefficients in CSD format to replace the conventional
multiplication process and to reduce the number of adders.
• To design area-delay-power efficient VLSI architecture in the Direct form.
• To implement low power and memory-efficient block-based 2-D FIR filter
architecture using high-speed multipliers and high-speed adders to reduce the
area, delay, and power consumption.
7

8. SCOPE
• The scope of our work will help in designing 2D FIR filters efficiently.
• Our work will help researches on FIR filters and CSD technique and optimization
of the filter can be done efficiently.
• Multiplier less design is achieved so that area, delay and power consumption will
be reduced.
8

9. 9
Band edge
Delay magnitude values
Ripple in each band
Sampling frequency
MATLAB
Filter co-efficients are
produced
Converted into
binary values using
CSD code
Filter architecture is
designed for these
binary values
VERILOG
CODE using
XILLINX
Architecture
cascaded is
generated using
delay
Using CADENCE
or SYNOPSIS tool
Netlist will be generated and
area-power report will be
generated
METHODOLOGY

10. ADVANTAGES
• Reduced hardware complexity
• Require less area for implementation
• Less power consumption
• Faster execution
• Minimized processing delays
• Lower resource utilization
• High precision
10

11. BIBILOGRAPHY :
• R. Mersereau, W. Mecklenbrauker, and T. Quatieri, "McClellan transformations
for two-dimensional digital filtering-Part I: Design." IEEE Transactions on
Circuits and Systems, Vol. 23, no.7, pp. 405-414, 1976.
• K. S. Yeung, and S.C. Chan “Design and implementation of multiplierless tunable
2D FIR filters using McClellan transformation” IEEE international symposium
on circuits and systems (ISCAS 2002), Vol. 5, pp. 761–764, 2002
• A. Chandra, and S. Chattopadhyay, “A new strategy of image denoising using
multiplier-less FIR filter designed with the aid of differential evolution
algorithm” Multimedia Tools and Applications, Vol. 75, no. 2, pp. 1079-1098,
2016. 11

12. 12
THANK YOU