Introduction to VHDL

1. Goals-The intent of this work is to introduce VHDL to engineers who will
be using the language to describe circuits for implementation in
programmable logic or ASICs. To this end, we will avoid prolonged
discussions that are appropriate only for developers of simulation models
and system-level simulations, and concentrate instead on those aspects of
the language that are most useful for circuit synthesis. We will give you
enough information to quickly get started using VHDL, and will suggest
coding styles that are appropriate using a wide variety of available synthesis
and simulation tools.
Learning Outcomes-Write synthesisable verilog.
Write a verilog testbench to test verilog modules.
Analyse code coverage of a verilog testbench..
Target a verilog design to an FPGA board.
Analyse and debug verilog modules.

2. Introduction To VHDL
Mr.S.S.Gurav
SITCOE,Yadrav

3. VHDL
What is VHDL?
V H I S C  Very High Speed Integrated Circuit
Hardware
Description
Language

4. History of VHDL
• Designed by IBM, Texas Instruments, and Intermetrics as part of the
DoD funded VHSIC program
• Standardized by the IEEE in 1987: IEEE 1076-1987
• Enhanced version of the language defined in 1993: IEEE 1076-1993
• Additional standardized packages provide definitions of data types and
expressions of timing data
– IEEE 1164 (data types)
– IEEE 1076.3 (numeric)
– IEEE 1076.4 (timing)

5. Traditional vs. Hardware Description
Languages
• Procedural programming languages provide the how or recipes
– for computation
– for data manipulation
– for execution on a specific hardware model
• Hardware description languages describe a system
– Systems can be described from many different points of view
• Behavior: what does it do?
• Structure: what is it composed of?
• Functional properties: how do I interface to it?
• Physical properties: how fast is it?

6. Why do we Describe Systems?
• Design Specification
– unambiguous definition of components and
interfaces in a large design
• Design Simulation
– verify system/subsystem/chip performance
prior to design implementation
• Design Synthesis
– automated generation of a hardware design

7. Digital System Design Flow
Requirements
Functional Design
Register Transfer
Level Design
Logic Design
Circuit Design
Physical Design
Description for Manufacture
Behavioral Simulation
RTL Simulation
Validation
Logic Simulation
Verification
Timing Simulation
Circuit Analysis
Design Rule Checking
Fault Simulation
• Design flows operate at multiple
levels of abstraction
• Need a uniform description to
translate between levels
• Increasing costs of design and
fabrication necessitate greater
reliance on automation via CAD
tools
– $5M - $100M to design new
chips
– Increasing time to market
pressures

8. A Synthesis Design Flow
Requirements
Functional Design
Register Transfer
Level Design
Synthesis
Place and Route
Timing Extraction
VHDL Model
(VHDL)
VHDL Model
Logic Simulation
Behavioral Simulation
• Automation of design refinement steps
• Feedback for accurate simulation
• Example targets: ASICs, FPGAs

9. Domains and Levels of Modeling
high level of
abstraction
FunctionalStructural
Geometric “Y-chart” due to
Gajski & Kahn
low level of
abstraction

10. Domains and Levels of Modeling
FunctionalStructural
Geometric “Y-chart” due to
Gajski & Kahn
Algorithm
(behavioral)
Register-Transfer
Language
Boolean Equation
Differential Equation

11. Domains and Levels of Modeling
FunctionalStructural
Geometric “Y-chart” due to
Gajski & Kahn
Processor-Memory
Switch
Register-Transfer
Gate
Transistor

12. Domains and Levels of Modeling
FunctionalStructural
Geometric “Y-chart” due to
Gajski & Kahn
Polygons
Sticks
Standard Cells
Floor Plan

13. Basic VHDL Concepts
• Interfaces
• Modeling (Behavior, Dataflow, Structure)
• Test Benches
• Analysis, elaboration, simulation
• Synthesis

14. • ENTITY Declarations
The primary purpose of the entity is to declare the signals in the
component's interface. All signals to be interfaced are listed in the PORT
clause. In some respect ENTITY is similar to the SYMBOL in a schematic
entry tool.
• PORT Clause
PORT clause declares the interface signals of the object to the outside
world. There are three parts to a PORT clause- Name, Mode, Data Type.
There are 5 PORT modes available:
• IN –
Indicates that the only signal driver is outside this block being declared.
• OUT –
Indicates that the only signal driver is within the component.
• BUFFER – I
Indicates there may be signal drivers both inside and outside of the
block. However only one may drive this signal at one time
• INOUT -- indicates there may be signal drivers both inside and outside of
the block. Many may drive this signal at one time, but a bus resolution
function is required to determine what values the signal will assume.

15. Basic Structure of a VHDL File
• Entity
– Entity declaration:
interface to outside
world; defines input
and output signals
– Architecture: describes
the entity, contains
processes, components
operating concurrently

16. Entity Declaration
entity NAME_OF_ENTITY is
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [NAME_OF_ENTITY] ;
• NAME_OF_ENTITY: user defined
• signal_names: list of signals (both input and
output)
• mode: in, out, buffer, inout
• type: boolean, integer, character, std_logic

17. Entity Examples …
entity half_adder is
port(
A,B: in std_logic;
sum, carry: out std_logic);
end half_adder;
Half ADDER
A
B
SUM
CARRY

18. Modeling Styles
• There are three modeling styles:
• Behavioral (Sequential)
• Structural
• Data flow

19. Behavioral (Sequential)
• Behavior Modeling Style shows that how our system performs
according to current input values.
• In behavor Modeling, we defines that what value we get at the
output corresponding to input values.
• We Defines the function / Behavior of our Digital Systems in
Behavior Modeling Style.
• Behavior Modeling Style works on Sequential Execution.

20. • 4 to 1 multiplexer using if else.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity multiplexer_4_1 is
port( din : in STD_LOGIC_VECTOR(3
downto 0);
sel : in STD_LOGIC_VECTOR(1
downto 0);
dout : out STD_LOGIC);
end multiplexer_4_1;
• architecture multiplexer4_1_arc
of multiplexer_4_1 is
begin
mux : process (din,sel) is
begin
if (sel="00") then
dout <= din(0);
elsif (sel="01") then
dout <= din(1);
elsif (sel="10") then
dout <= din(2);
else
dout <= din(3);
end if;
end process mux;
end multiplexer4_1_arc;

21. • 1 to 4 demultilexer using
case.vhd
library IEEE;
use
IEEE.STD_LOGIC_1164.all;
entity demultiplexer_case is
port(
din : in STD_LOGIC;
sel : in
STD_LOGIC_VECTOR(1downto 0);
dout : out
STD_LOGIC_VECTOR(3down to 0)
);
end demultiplexer_case;
• architecture demultiplexer_case_arc of
demultiplexer_case is
begin
demux : process (din,sel) is
begin
case sel is
when "00" => dout <= din & "00";
when "01" => dout <= '0' & din & "01";
• when "10" => dout <= "01" & din &
‘10';
when others => dout <= “10" & din;
end case;
end process demux;
end demultiplexer_case_arc;

22. Structural
• Structural Modeling Style shows the Graphical
Representation of modules/ instances / components with
their Interconnection.
• In Structural Modeling Style We defines that how our
Components / Registers / Modules are Connected to each
other using Nets/ Wires.
• Structural Modeling Style is based on Net-List Language.
• Structural Modeling Style works on Concurrent Execution.

23. • Design of 2 to 1 multiplexer
using Structural Modeling
Style.vhd
library IEEE;
use
IEEE.STD_LOGIC_1164.all;
entity multiplexer2_1 is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
sel : in STD_LOGIC;
dout : out STD_LOGIC
);
end multiplexer2_1;
• architecture multiplexer2_1_arc of
multiplexer2_1 is
component and2 is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
dout : out STD_LOGIC
);
end component and2;
component or2 is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
dout : out STD_LOGIC
);
end component or2;
component not1 is
port (a : in STD_LOGIC;
dout : out STD_LOGIC
);
end component not1;

24. Data flow
• Data Flow Modeling Style Shows that how the data /
signal flows from input to ouput threw the registers /
Components. Data Flow Modeling Style works on
Concurrent Execution

25. • entity Half_Adder is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end Half_Adder;
architecture Half_Adder_arc of
Half_Adder is
begin
sum <= a xor b;
carry <= a and b;
end Half_Adder_arc;
• entity multiplexer_4_1 is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
x : in STD_LOGIC;
y : in STD_LOGIC;
dout : out STD_LOGIC );
end multiplexer_4_1;
architecture multiplexer_4_1_arc of
multiplexer_4_1 is
begin
dout <= ((not x) and (not y) and a) or
((not x) and y and b) or
(x and (not y) and c) or
(x and y and d);
end multiplexer_4_1_arc;

26. Half Adder
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port(
x,y: in std_logic;
sum, carry: out std_logic);
end half_adder;
architecture myadd of half_adder is
begin
sum <= x xor y;
carry <= x and y;
end myadd;

27. Architecture Examples: Behavioral Description
• Entity FULLADDER is
port ( A, B, C: in std_logic;
SUM, CARRY: in std_logic);
end FULLADDER;
• Architecture CONCURRENT of FULLADDER is
begin
SUM <= A xor B xor C after 5 ns;
CARRY <= (A and B) or (B and C) or (A and C) after 3
ns;
end CONCURRENT;

28. Architecture Examples: Structural Description …
• architecture STRUCTURAL of FULLADDER is
signal S1, C1, C2 : bit;
component HA
port (I1, I2 : in bit; S, C : out bit);
end component;
component OR
port (I1, I2 : in bit; X : out bit);
end component;
begin
INST_HA1 : HA port map (I1 => B, I2 => C, S => S1, C => C1);
INST_HA2 : HA port map (I1 => A, I2 => S1, S => SUM, C => C2);
INST_OR : OR port map (I1 => C2, I2 => C1, X => CARRY);
end STRUCTURAL;
I1 S
HA
I2 C
I1 S
HA
I2 C I1
OR
I2 x
A
C
B
CARRY
SUM
S1
C1
C2

29. Data Objects
• There are three types of data objects:
• Signals
• Can be considered as wires in a schematic.
• Can have current value and future values.
• Variables and Constants
• Used to model the behavior of a circuit.
• Used in processes, procedures and functions.

30. Data Types
• Integer
• Integer
• Minimum range for any implementation as defined by standard: -
2,147,483,647 to 2,147,483,647
• Integer assignment example

31. • Array
• Array
• Used to collect one or more elements of a similar type in a single
construct.
• Elements can be any VHDL data type.

32. Predefined Operators
• Logical operators
• Arithmetic operators
• Comparison (relational) operators
• Shift operators
• Matching comparison operators

33. Logical operators
• Logical Operators Used to perform logical operations. The data must be
of type BIT, STD_LOGIC, or STD_ULOGIC (or, obviously, their
respective extensions, BIT_VECTOR, STD_LOGIC_VECTOR, or
STD_ULOGIC_VECTOR). The logical operators are:
• NOT
• AND
• OR
• NAND
• NOR
• XOR
• XNOR
•• Examples:
• y <= NOT a AND b; -- (a'.b)
• y <= NOT (a AND b); -- (a.b)'
• y <= a NAND b; -- (a.b)'

34. Arithmetic Operators
• The arithmetic operators are:
• Addition (+)
• Subtraction (-)
• Multiplication (*)
• Division (/)
• Exponentiation (**)

35. Comparison Operators
• Also called relational operators, the comparison operators are:
• Equal to (=
• Not equal to (/=)
• Less than (<)
• Greater than (>)
• 4 Less than or equal to (<=)
• Greater than or equal to (>=)

36. Shift Operators
• Introduced in VHDL93,
• shift operators are used for shifting data vectors. They are:
• Shift left logic (SLL): Positions on the right are filled with '0's.
Shift right logic
• (SRL): Positions on the left are filled with '0's. Shift left
arithmetic
• (SLA): Rightmost bit is replicated on the right. Shift right
arithmetic
• (SRA): Leftmost bit is replicated on the left. Rotate left (ROL):
Circular shift to the left. Rotate right (ROR): Circular shift to
the right.