The document outlines Preetham Kumar Duggishetti's Masters projects in electrical engineering focusing on circuit design, including projects developing a Phase Locked Loop at 1.6GHz, a low power 32-bit ALU, an oversampling Sigma Delta ADC for WLAN systems, and more. The projects involved designing circuits in Cadence and developing behavioral models in VerilogA and MATLAB to meet various power, speed, and dynamic range requirements. Preetham's work demonstrates expertise in analog and mixed-signal circuit design.

1. Project Works Preetham Kumar Duggishetti Masters in Electrical Engineering Electronics and Mixed Signal Circuit Design Arizona State University pduggish@asu.edu preetham463@gmail.com

3. Cadence (Spectre ) , VerilogA, MATLAB.

4. Generated 4 equally spaced clocks at 1.6GHz with CMOS full-swing (1.8V), achieved 300ns lock time for 1.6GHz oscillation.

6. Cadence (Spectre, Virtuso)

7. Requirement : Power consumption to be least with a delay constraint of 10 nS, output transition time lower than 200pS with a load of 30 fF at the -10%Vdd and Slow-Slow Design corner.

8. Understood various design techniques for Low Power and procedures to choose the right logic style.

10. Cadence (Spectre ) , MATLAB/SIMULINK, VerilogA .

12. Cadence (Spectre )

13. Dc gain > 50dB, Ft = 70MHz with CL = 1pF, Tail current source < 110uA.

15. Cadence (Spectre ) .

16. Understood IC biasing circuits and their variations with supply and temperature.

18. Cadence (Spectre , Virtuso Layout Editor )

19. High gain, UGF of 25 MHz with 15pF capacitive load, input referred noise of 10nV/sqHz, Quiescent Power dissipation of 1.2mW, Slew rate of 10V/usec with 5pF cap load, PSRR and CMRR of 55dB at 10 KHz and Phase margin of 60 degrees with 5pF capacitive load.

21. Matlab/Simulink tools were used and a resolution of 14 bit and 12 bit respectively were achieved.