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CCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete Record
Low power and area-efficient shift register using pulsed latches
1. Logic Mind Technologies
Vijayangar (Near Maruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Low-Power and Area-Efficient Shift Register
Using Pulsed Latches
Abstract—This paper proposes a low-power and area-efficient shift register using
pulsed latches. The area and power consumption are reduced by replacing flip-
flops with pulsed latches. This method solves the timing problem between pulsed
latches through the use of multiple non-overlap delayed pulsed clock signals
instead of the conventional single pulsed clock signal. The shift register uses a
small number of the pulsed clock signals by grouping the latches to several sub
shifter registers and using additional temporary storage latches. A 256-bit shift
register using pulsed latches was fabricated using a 0.18 CMOS process with . The
core area is . The power consumption is 1.2 mW at a 100 MHz clock frequency.
The proposed shift register saves 37% area and 44% power compared to the
conventional shift register with flip-flops.
2. SOFTWARE REQUIREMENT:
ModelSim6.4c.
Xilinx 9.1/13.2.
HARDWARE REQUIREMENT:
FPGA Spartan 3.
PROJECT FLOW:
First Review:
Literature Survey
Paper Explanation
Design of Project
Project Enhancement explanation
Second Review:
Implementing 40% of Base Paper
Third Review
Implementing Remaining 60% of Base Paper with Future Enhancement (Modification)
For More Details please contact
Logic Mind Technologies
Vijayangar (NearMaruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Mail: logicmindtech@gmail.com
