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Ovonic Unified Memory(Ppt)

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One of the next generation memory that has unlimited read cycles..

Ovonic Unified Memory(Ppt)

  1. 1. OVONIC UNIFIED MEMORY<br />PratikRathod<br />8thSem E.C.<br />
  2. 2. Semiconductors form the fundamental building blocks of the modern electronic world providing the brains and the memory of products all around us from washing machines to super computers.<br />Current memory technologies have a lot of limitations<br />One of the fundamental approaches to manage challenge is using new materials to build the next generation transistors.<br />The new memory technologies have got all the good attributes for an ideal memory.<br />Introduction<br />Introduction<br />
  3. 3. PRESENT MEMORY TECHNOLOGY SCENARIO<br />PRESENT MEMORY TECHNOLOGY SCENARIO<br />
  4. 4. Many new memory technologies were introduced when it is understood that semiconductor memory technology has to be replaced, or updated by its successor since scaling with semiconductor memory reached its material limit.<br />So, next generation memories are trying tradeoffs between size and cost.<br />These make them good possibilities for development. <br />PRESENT MEMORY TECHNOLOGY SCENARIO<br />
  5. 5. ‘Next Generation Memories”<br />The fundamental idea of all these technologies is the bistable nature possible for of the selected material.<br />Emerging memories<br />Emerging memories<br />
  6. 6. Emerging memories<br />
  7. 7. Most Promising One.<br />Material Used is called CHALCOGENIED.<br />The Group VI elements of the periodic table.<br />Refers to alloys containing at least one of these elements such as the alloy of Germanium, Antimony, and Tellurium<br />OUM – Ovonic unified memory<br />OUM – Ovonic unified memory<br />
  8. 8. Phase change technology uses a thermally Activated, Rapid, Reversible change in the structure of the alloy to store data.<br />The two structural states are Amorphous State and Polycrystalline State. <br />OUM – Ovonic unified memory<br />
  9. 9. Resistive heating is used to change the phase of the chalcogenide material.<br />Amorphous State - by taking temp above melting point.(Tm)<br />Polycrystalline State - holding temp at a lower temp for slightly longer period of time.(Tx)<br /> The time needed to program either state is = 400ns<br />OUM – Ovonic unified memory<br />
  10. 10. OUM – Ovonic unified memory<br />
  11. 11. Once programmed, the memory state of the cell is determined by reading its resistance.<br />Expected to be impervious to ionizing radiation effects.<br />One billion Write cycles between these two States were demonstrated. Reading the state of the device is nondestructive and has no impact on device wear out<br />So it has Unlimited Read cycles.<br />OUM – Ovonic unified memory<br />
  12. 12. OUM ARCHITECTURE<br /><ul><li>The base of the heater is connected to a diode.
  13. 13. Thermal insulators are also attached to the memorystructure in order toavoid data lose due to destruction of material at hightemperatures.
  14. 14. To write- heated past its melting point and then rapidly cooled to make it amorphous.</li></ul>OUM ARCHITECTURE<br />
  15. 15. The initial goal of CMOS integration was to develop the processes necessary to connect the memory element to CMOS transistors and metal wiring, without degrading the operation of either memory elements or the transistors.<br />Access Device Test Chip (ADTC) <br />CMOS Integration<br />CMOS Integration<br />
  16. 16. We are placing the memory element above the CMOS transister and below 1st level metal.<br />CMOS Integration<br />CMOS Integration<br />
  17. 17. <ul><li>Short loop (partial flow) experiments
  18. 18. full flow experiment
  19. 19. 1T1R</li></ul>CMOS Integration<br />CMOS Integration<br />
  20. 20. The voltage is applied to one of the two terminals of the chalcogenide resistor, and the access transistor (biased on) is between the other resistor terminal and ground.<br />V – I characteristics<br />V-I Characteristics<br />
  21. 21. V – I characteristics<br />V-I Characteristics<br />
  22. 22. Figure shows the operation of a 1T1R memory, again with the access transistor biased on.<br />
  23. 23. <ul><li>CTCV – Chalcogenide Technology Chararecterization Vehicle.
  24. 24. It contains memory with different architecture, circuit and layout variation.
  25. 25. Key goals of CTCV are</li></ul> 1. to make the read and write circuits robust wrt potential variations in cell electrical charecteristics.<br /> 2. to test the effect of the memory cell layout on performance.<br /> 3. to maximize the amount of useful data obtained that could later be used for product design<br />Circuit demonstration<br />Circuit demonstration<br />
  26. 26. <ul><li>Single ended sense amplifier.
  27. 27. The differential amplifier.
  28. 28. Conservative Cell.
  29. 29. Aggressive Cells.
  30. 30. Process Monitoring.</li></ul>Circuit demonstration<br />Circuit demonstration<br />
  31. 31. <ul><li> no effect on measured CMOS transistor parametric
  32. 32. indicate full functionality of the 64 kbit memory arrays.
  33. 33. Companies working with Ovonic Unified memory have their ultimate goal to gather enough data to begin a product design targeting a 1–4 Mbit C-RAM device.</li></ul>Tests & Results<br />Tests & Results<br />
  34. 34. OUM uses a reversible structural phase change.<br />· Small active storage medium.<br />· Simple manufacturing process.<br />· Simple planar device structure.<br />· Low voltage single supply.<br />· Reduced assembly and test costs.<br />· Highly scalable- performance improves with scaling<br />· Multistate are demonstrated.<br />· High temperature resistance.<br />· Easy integration with CMOS.<br />· It makes no effect on measured CMOS transistor parametric.<br />· Total dose response of the base technology is not affected<br />advantages<br />Advantages<br />
  35. 35. THANK YOU<br />

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