These slides would give you glimpse of what VLSI Technology and fundamentals to be learnt by students B.Tech. electronics

1. Essentials ofEssentials of
VLSI DesignVLSI Design
Kishore Prabhala
Director, VLSI Design Centre
PSK Research Foundation
www.pskrf.com
MSEE, Georgia Institure of Technlogy, GA, USA-
1989
BSEE, Purdue University, IN, USA-1981

2. Industry Development Analogy (1D to
3D)• Transportation
Train (1D) => Automobile (2D) => Airplane (3D)
• Communication
Electricity (1D) => Telephone (2D) => Satellite (3D)
• Memory (IC)
Transistor (1D) => VLSI Chip (2D) => Stacking (3D)
2
Kishore Prabhala, Director, VSLI Design Centre PSKRF

3. Semiconductor Industry Growth
2002 ISSCC Keynote Speech by Dr. C. G. Hwang
SemiconductorConsumption
Server & WS
~1995 2000 2005 2010
Phase 1 Phase 3 Phase 4Phase 2
Server & WS Server & WS
Mobile
Server & WS
Consumer
Home Network
Internet Appl.
Consumer
Home Network
Internet Appl.
PC/Game PC/Game PC/Game
Mobile EraIT Infra Era
Phase 5
2015
Fusion Era
Communication,
Bio, Robotics
PC Era
Consumer
+ Mobile Era
Paradigm Shift:
Semiconductor
Consumption Divergence
Paradigm Shift:
Semiconductor
Consumption Divergence
Mobile
Server & WS
Consumer
Home Network
Internet Appl.
Consumer
Home Network
Internet Appl.
PC/Game
Mobile
3Kishore Prabhala, Director, VSLI Design Centre PSKRF

4. Semiconductor IC MarketMarketScale($B)
300
100
10
1
1975 1980 1985 1990 1995 2000 2005 2010
50
5
PC ‘Windows’
Y2K +
IT Bubble
2015
Mobile, Consumer
Internet, Bio, Robot
ipod
Birth
Source: WSTS 2005 & SEC
3
30
4
Kishore Prabhala, Director, VSLI Design Centre PSKRF

5. Moore’s Law and Technology Scaling
…the performance of an IC, including the number components on it, doubles
every 18-24 months with the same chip price ... - Gordon Moore - 1960
5Kishore Prabhala, Director, VSLI Design Centre PSKRF

6. 130,90 & 65 nm Designs
Digital Design
Error
Analog Design
Error
Feature
Change
Hard/
Technology IP
Timing Failure
Physical
Design
Areas of VLSI Technology
6Kishore Prabhala, Director, VSLI Design Centre PSKRF

7. Revenue
($M) 2007 2008 2009 2010 2011 2012 2013 CAGR
EDA 4,866.6 4,318.4 4,398.0 4,835.0 5,420.0 6,045.0 6,510.0 8.6%
CAE 2,545.2 2,214.1 2,285.0 2,575.0 2,960.0 3,390.0 3,685.0 10.7%
IC CAD 1,789.9 1,581.2 1,589.0 1,705.0 1,875.0 2,045.0 2,190.0 6.7%
PCB 531.5 523.1 524.0 555.0 585.0 610.0 635.0 4.0%
Electronic Design Automation (EDA)
Software Forecast
7Kishore Prabhala, Director, VSLI Design Centre PSKRF

8. ITRS Roadmap
H.P. – high performance microprocessor, μP – microprocessors
H.H. – hand-hold products, SoC – system-on-chip
8Kishore Prabhala, Director, VSLI Design Centre PSKRF

9. Silicon technology roadmap
low power SoC
high performance
MPU/SoC
2001 2004 2010 2001 2004 2010
gate length (nm) 130 90 45 90 53 25
supply voltage 1.2 1 0.6 1.1 1 0.6
transistor count (M) 3.3 8.3 40 276 553 2212
chip size (mm2
) 100 120 144 310 310 310
clock frequency (GHz) 0.15 0.3 0.6 1.7 2.4 4.7
wiring levels 6 7 9 7 8 10
max power (W) 0.1 0.1 0.1 130 160 218
• intrinsic capability of ICs (transistor count / gate delay)
grows with ~ 50% per year (Moore’s Law)
• power limits the performance
9Kishore Prabhala, Director, VSLI Design Centre PSKRF

10. Introduction - History
• First generation chips contained a few transistors.
• Today, silicon technology allows us to build chips consisting of
hundreds of millions of transistors (Intel Pentium IV: 0.09
micron). This technology has enabled new levels of system
integration onto a single chip.
• Mobile phones, portable computers and Internet appliances will
be built using a single chip.
• The demand for more powerful products and the huge capacity
of today’ s silicon technology have moved System-on-Chip (SoC)
designs from leading edge to mainstream design practice.
• “System on Chip” (SoC) technology will put the maximum
amount of technology into the smallest possible space.
10Kishore Prabhala, Director, VSLI Design Centre PSKRF

11. 1947 Invention of the Point Contact1947 Invention of the Point Contact
TransistorTransistor
A transistor uses an electrical current
few milliamps or a small amount of
voltage 0.7 Volts to control a larger
change in current or voltage.
In 1947, William Shockley, John
Bardeen, and Walter Brattain of Bell
Laboratories built first
Transistor.
The first transistor used germanium, a
semiconductive material, later
Silicon was used to building
transistors / ICs
First Point Contact Transistor and Testing
Apparatus (1947)
[Photo Courtesy of The Porticus Centre]
11Kishore Prabhala, Director, VSLI Design Centre PSKRF

12. 1958 Invention of Integrated Circuit1958 Invention of Integrated Circuit
 Before IC, Systems used with transistors to be
connected to wires & other electronics.
 An IC includes the transistors, resistors,
capacitors, and wires. Circuit or device became
smaller from few mm to um
 In 1958, Jack Kilby from Texas Instruments
built a "Solid Circuit“ on one germanium chip: 1
transistor, 3 resistors, and 1 capacitor - 9 mm2
 Robert Noyce, Fairchild Semiconductor made
the first "Unitary Circuit“ on a silicon chip, first
patent was awarded in 1961, later started INTEL
with Andrew Groove, Gordon Moore Texas Instrument's First Integrated Circuit
[Photos Courtesy of Texas Instruments]
12Kishore Prabhala, Director, VSLI Design Centre PSKRF

13. Kishore Prabhala, Director, VSLI Design Centre PSKRF 13
History
Bipolar logic
1960’s
Intel 4004
1971

14. Electronic systems
Systems on chip are everywhereSystems on chip are everywhere
Technology advances enable increasingly more complex designsTechnology advances enable increasingly more complex designs
Central Question:Central Question: how to exploit deep-how to exploit deep-
submicron technologies efficiently?submicron technologies efficiently?
14Kishore Prabhala, Director, VSLI Design Centre PSKRF

15. 15
1.3 VLSI Design Styles
IN OUT
0 1
1 0
1 0
1 1
OR INV NORNANDAND
IN1 IN2 OUT
0 0 0
1 0 0
0 1 0
1 1 1
IN1 IN2 OUT
0 0 0
1 0 1
0 1 1
1 1 1
IN1 IN2 OUT
0 0 1
1 0 0
0 1 0
1 1 0
IN1 IN2 OUT
0 0 1
1 0 1
0 1 1
1 1 0
Basic Logic Gates
15Kishore Prabhala, Director, VSLI Design Centre PSKRF

16. B
A
A B
F
VDDVDD
A B
A
B
F
VDD
A
A
F
1
2 2 2
2
2
1 1
4
4
Inverter 2-input NAND 2-input NOR
Basic Logic Gates: Inverter, NAND, NOR
16Kishore Prabhala, Director, VSLI Design Centre PSKRF

17. Propagation delay deteriorates rapidly as a function of fan-in –
quadratically in the worst case.
Kishore Prabhala, Director, VSLI Design Centre PSKRF 17
DCBA
D
C
B
A CL
C3
C2
C1
Distributed RC model
(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Delay in CMOS Gates–4 input NAND

18. Kishore Prabhala, Director, VSLI Design Centre PSKRF 18
Delay in CMOS Gates
Gates with a
fan-in greater
than 4 should
be avoided.
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
tpHL
quadratic
linear
tp
tp(psec)
fan-in

19. Kishore Prabhala, Director, VSLI Design Centre PSKRF 19
In
Out
VDD
GND
OutIn
VDD
M2
M1
A
Out
VDD
GND
BB
VDD
A
CMOS Inverter / NAND Layout-Cell

20. VLSI Design Flow
Kishore Prabhala, Director, VSLI Design Centre PSKRF 20
ENTITY test is
port a: in bit;
end ENTITY test;
DRC
LVS
ERC
Circuit Design
Functional Design
and Logic Design
Physical Design
Physical Verification
and Signoff
Fabrication
System Specification
Architectural Design
Chip
Packaging and Testing
Chip Planning
Placement
Signal Routing
Partitioning
Timing Closure
Clock Tree Synthesis
©2011SpringerVerlag

21. Architecture
design &
verification
Block design
& verification Chip design,
Integration &
Verification
Silicon
fabrication&
Test
System
Validation
Time in Weeks
System
spec
Application software design &
Verification
SiliconSiliconRequirementsRequirements HDDHDD Early RTLEarly RTL Final RTLFinal RTL
Concept Architecture Implementation Integration Fab Platform integration
TapeoutTapeout
System RTL/Gate prototype
Design
levels
Firmware design
& verification
VSLI Design Flow
21Kishore Prabhala, Director, VSLI Design Centre PSKRF

22. VLSI Design: ASICs/Standard/CellCustom
ASICs are logic chips designed by end customers to
perform a specific function for a desired application.
ASIC vendors supply libraries for each technology
they provide. In most cases, these libraries contain
predesigned and preverified logic circuits.
ASIC technologies are:
 gate array
 standard cell
 full custom
22Kishore Prabhala, Director, VSLI Design Centre PSKRF

23. Uncommited Cell
Kishore Prabhala, Director, VSLI Design Centre PSKRF 23
rows of
cells
routing
channel
uncommitted
VDD
GND
polysilicon
metal
possible
contact
In1 In2 In3 In4
Out
Committed
Cell
(4-input NOR)
VLSI Design: ASICs Gata Array

24. • Standard Cell Design / Layout
Kishore Prabhala, Director, VSLI Design Centre PSKRF 24
Routing channel
requirements are
reduced by presence
of more interconnect
layers
Functional
module
(RAM,
multiplier,
)
Routing
channel
Logic cellFeedthrough cell
Rows of
cells

25. Standard cell layout vs Macro Cells
Kishore Prabhala, Director, VSLI Design Centre PSKRF 25
A
GND
Feedthrough
Cell
Pad
Ground
Pad
Routing
Channel
Standard
Cells
Power
Pad
A’
VDD
VLSI Design: Standard Cell
Pad
GND
PLA
RAM
Standard Cell
Block
RAM
PLA
Routing Regions
VDD

26. Connecting between metal layers requires
one or more “vias”
Metal Layers have preferred routing
directions
 Metal 1 (Blue) Horizontal
 Metal 2 (Yellow) Vertical
 Metal 3 (Red) Horizontal
Kishore Prabhala, Director, VSLI Design Centre PSKRF 26
Routing between Cells

27. Behaviour Model to RTL to Netlist
Kishore Prabhala, Director, VSLI Design Centre PSKRF 27
EDA Tools for Chip Design

28. Chip Placement
Kishore Prabhala, Director, VSLI Design Centre PSKRF 28
EDA Tools for Chip Design

29. Delay Path Clock Tree Synthesis
Kishore Prabhala, Director, VSLI Design Centre PSKRF 29
EDA Tools for Chip Design

30. EDA Tools
Kishore Prabhala, Director, VSLI Design Centre PSKRF 30
Layer Palette
Mouse Buttons Bar
Layout Windows
Drawing Tools
Cell Browser
Status Bar
ToolbarMenu Bar
Text Windows
Locator
©2011Springer
EDA Tools for Chip Design

31. 1.3 VLSI Design Styles
Power (Vdd)-Rail
Ground (GND)-Rail
Contact
Vdd
GND
OUT
IN2
IN1
OUT
IN2
IN1
OUTIN1
Vdd
GND
IN2
Diffusion layer
p-type
transistor
n-type
transistor
Metal layer
Poly layer
31
Kishore Prabhala, Director, VSLI Design Centre PSKRF
EDA Tools for
Chip Design

32. Evolution of VSLI in 2014
Silicon Process Technology
• 􀂃 0.13μm CMOS
• 􀂃 ~100 millions of devices, 3 GHz internal Clock
32Kishore Prabhala, Director, VSLI Design Centre
PSKRF

33. Paradigm Shift in SoC Design
System on a board
System on a Chip
33Kishore Prabhala, Director, VSLI Design Centre PSKRF

34. Example of SoC Design
Levarage Internal Bandwidth vs External Bandwidth
34Kishore Prabhala, Director, VSLI
Design Centre PSKRF

35. Intellectual Property
Utilizing the predesigned modules
enables:
to avoid reinventing the wheel
for every new product,
to accelerate the development
of new products,
to assemble various blocks of a
large ASIC/SoC quite rapidly,
to reduce the possibility of
failure based on design and
verification of a block for the first
time.
These predesigned modules are commonly called
Intellectual Property (IP) cores or Virtual Components
(VC).
Resources vs. Number of Uses
35Kishore Prabhala, Director, VSLI
Design Centre PSKRF

36. Examples of IPs
36Kishore Prabhala, Director, VSLI
Design Centre PSKRF

37. Intellectual Property Categories
IP cores are classified into three distinct categories:
Hard IP cores consist of hard layouts using particular physical design
libraries and are deliverid in masked-level designed blocks (GDSII
format). The integration of hard IP cores is quite simple, but hard cores
are technology dependent and provide minimum flexibility and portability
in reconfiguration and integration.
Soft IP cores are delivered as RTL VHDL/Verilog code to provide
functional descriptions of IPs. These cores offer maximum flexibility and
reconfigurability to match the requirements of a specific design
application, but they must be synthesized, optimized, and verified by their
user before integration into designs.
Firm IP cores bring the best of both worlds and balance the high
performance and optimization properties of hard IPs with the flexibility of
soft IPs.These cores are delivered in form of targeted netlists to specific
physical libraries after going through synthesis without performing the
physical layout. 37Kishore Prabhala, Director, VSLI
Design Centre PSKRF

38. Large Memory Capacity & High Speed
Double Height
DDP
PKG Stack
CSP Stack
Module Stack
Single Height
3D
1D
38Kishore Prabhala, Director, VSLI
Design Centre PSKRF

39. Technology Projection in the 21st
Century
350Mbit/cm2
100~800MHz
0.2~1.25W
~20Gbit/cm2
~10GHz
0.5~1.0W
~500Tbit/cm2
~1THz
~0.5W
~5Tbit/cm2
~80GHz
~<1W
Thinking
Robot
Brain-ware
Smart Animal Robot
Virtual Brain
Hardware
Info. Bank System
Si-Money
Discrete
Digital
Era
>1Abit/cm2
~100THz
~0.2W
““Small” World
Small” World
39Kishore Prabhala, Director, VSLI
Design Centre PSKRF

40. Four vital areas of VLSI:
 Higher levels of abstraction
 IP and platform re-use
 IP creation – ASIPs,
interconnect and algorithm
 Earlier software development
and integration
• VLSI Design implements most or all of the function of a complete
electronic system.
Conclusions
40Kishore Prabhala, Director, VSLI Design Centre PSKRF

41. JOIN VLSI DESIGN CENTRE
PSK RESEARCH FOUNDATION
THANK YOU
info@pskrf.com
EDA Training 1 to 4 months
41Kishore Prabhala, Director, VSLI
Design Centre PSKRF