1. MANJEET SINGH LOWANSHI
IC Design Engineer (Broadcom Limited)
M.Tech. IIT Roorkee (VLSI & Microelectronic)
Contact no: 9663389260,7579482809
Email id:man2477@gmail.com
Area(s) of Interest: Digital circuit design/layout, Memory compiler
PROFILE SUMMARY
• Currently working in Broadcom limited as IC Design Engineer (1+ years).
• Worked at Dxcorr Hardware Technologies as Digital Design Engineer for 6 month.
• Successfully completed M.Tech. (Microelectronics and VLSI Design) from IIT, Roorkee in 2014.
• Gained practical knowledge of Digital Circuit Designs, Physical/Digital VLSI Design, Microelectronics
and VERILOG Programming through various project works.
• Technologies worked on -16FF, 22FDSOI, 28nm, 7nm(started).
• Well versed with different software packages such as Cadence Skill, C, VERILOG, SHELL
SCRIPTING, etc.
• Well versed with the knowledge of Fabrication Process as worked on Lithography, Sputtering, Vacuum
Coating etc. units at IIT Roorkee.
ACADEMIC & PROFESSIONAL PROJECTS
Title:M16PSP memcomp
Organization: Broadcom limited
Description: It is a Pipelined single port SRAM memory compiler based on 16nm. In this project worked as
layout designer from leaf cells to top level including placement and routing at top level using
skill code.
Title:M28LSP memcomp
Organization: Broadcom limited
Description: It’s a Low Power single port SRAM memory compiler in which I owned Grblk and did
placement and routing at top level.
Title: M16SP memcomp.
Organization: Broadcom limited.
Description: Designed sense amplifier layout which is more symmetric and reduced routing capacitance (got
appreciation for these work).
Title: Logic Verification Testchip for Global foundries 22FDSOI technology node.
Organization: DXCorr Design Inc.
Description: Overall Nebula chip is a Process Qualification Vehicle Testchip. Working with 22FDSOI
designed various ring oscillator test structures for characterizing FDSOI technology node. In
this chip I have designed test structure for Metal characterization, Clock to Q delay,
Setup/hold delay. Aim of this test structure is to correlate the measured data from test
structures after wafer probing with model predictions derived from circuit simulations i.e
provide input for building SPICE models for MOSFETs and other circuit elements.
Title: Full Custom Skalansky 64 bit adder for Fibonacci_2R1W memory chip design.
Organization: DXCorr Design Inc
Description: Designed full custom 64 bit Skalansky adder based on the concept of carry propogation with
Lind and Johnson technique for reduction of delay which is based on carry skip concept for
implementing 64 bit addition which is based on TSMC28hpm Process Design kit. Post layout

2. simulation had given worst case delay of 384ps.
Title: Fabrication and Characterization of GaAs MOSCAP (1 year)
Organization: IIT, Roorkee
Description: Till present scenario semiconductor industry achieved acceptable level of accuracy in silicon
technology, but when it comes to III-V semiconductor, the process used for fabrication of III-V
semiconductor based MOSFET are not up to the mark. Here I have worked to solve problemin
this area by growing good quality stable oxide over GaAs semiconductor and then studied
its characteristics. I have calculated interface trap density and permittivity of the oxide. Also
performed the temperature reliability of fabricated device and plotted Arrhenius plot for
calculating activation energy.
Title: A Verilog Simulation of USART (B.Tech Project)
Organization: Chattisgarh Swami Vivekanand Technical University
Description: In this project we study the basic structure and behavioural implementation of logic circuits
using Verilog codes. We selected one IC that is Universal synchronous and asynchronous
receiver transmitter (USART) and we implement a behavioural description for transmitter
section, receiver section and various logics sections in USART. Finally we simulated the
code with Xilinx tool .
ACADEMIC DETAILS
2014 M.Tech. (Microelectronics and VLSI Design) from IIT, Roorkee with CGPA of 6.833/10
2010 B.Tech. (Electronics & Communication Engineering) from CSVTU, chhattisgarh with 66%
2006 12
th
from B.S.P. Senior Secondary School with 58.2%
2004 10
th
from Little Flower H.S. School with 81%
OTHER COURSES
4 Month duration RF IC Design Course from IITR, MICROWAVE in 2013
4 Month duration Advanced Microwave Engineering from IITR institute, in 2013
3 Month duration Analog IC Design Course from IITR in 2013
4 Month duration VLSI Technology Course from IITR in 2012
6 month C programming course from NIIT.
A short course on nano-electronics organized by IEEE-EDS.
ACADEMIC ACCOLADES
• Cleared Graduate Aptitude Test in Engineering (GATE) score of 686/1000 with a 99.3percentile
IT SKILLS
Programming Languages: C, Cadence Skill, VERILOG, SHELL SCRIPTING
Software Packages: Cadence, XILINX, IC compiler, Sentaurus TCAD,TCAD, T-Spice,
CALIBRE, Ultraisim, Spectre,
EXTRACURRICULAR ACTIVITIES
• 7th National Science Olympiad (2004)
• Member of IEEE-EDS student chapter .
• PERSONAL DETAILS
Date of Birth: 1
st
December 1988
Languages Known: English, Hindi
Permanent Address: Qr. No.3/B, St.-37, Sector-4, Bhilai - 490001.
Present Address: 2
nd
Cross, 2
nd
Main, Pai Layout, Bangalore- 560016