Keywords- RF Design, Debug, Testing, Validation Language - Python, Embedded C/C++

1. NIKHIL ANAND MUTHYA
Email: nikhil.anand.m@gmail.com
Linkedin: www.linkedin.com/in/nikhilmanand/
7760 McCallum Blvd , Apt 20316
Dallas, TX 75252
Mob – (214)682-3107
EDUCATION Master of Science in Electrical Engineering GPA – 3.72/4
University of Texas, Dallas December, 2016
Bachelor of Engineering in Electronics and Communication GPA – 3.85/4
BNM Institute of Technology (Visvesvaraya Technological University) Bangalore, 2010
TECHNICAL
SKILLS
Tools: NI AWR Design Environment, LabVIEW, Allegro, Visual DSP (Analog Devices Inc.), Code
Composer Studio (Texas Instruments), MATLAB, C/C++ Compliers, Xilinx, Cadence OR-CAD design
tool, Microsoft word, Microsoft excel
Hardware: Spectrum analysers, Power meters, VNA’s, oscilloscopes, 3m and 5m Semi-Anechoic
chamber (calibration,testing), Schematics design, net-list generation and board fabrication process
cycle, RF down converter design and calibration, Receiver environment testing (Humidity,
temperature and vibration tests), Soldering
Programming Languages : C/C++, Assembly languages, Verilog, VHDL,Python
Processors: SHARC 213xx, Black fin 5xx and TMS320xx processors, Spartan 6
ACADEMIC PROJECTS
Resonator and Transmission Line Matching Spring -2015
 Implemented a Micro strip line Resonator and transmission line matching for some test circuits and analysed the
insertion loss and Z-parameters in AWR MWO.
Physical Layer Simulation of an LTE-OFDM System Spring -2015
 A simplified version of LTE – OFDM symbol was implemented in MATLAB considering LTE specification from the
LTE standards document. Performance evaluation was conducted in AWGN and Rayleigh channel. Estimated
spectral efficiency of the adaptive modulation scheme used in LTE.
Fading Simulator Spring- 2015
 Simulated a Rayleigh fading channel, built an estimator and estimated the speed of the vehicle using level crossing
rates.
Space Debris Detection using Ground based transmitter Fall - 2014
 Detecting Space debris using a RADAR and Satellite RF Transmitter and Receiver System. Involved in frequency
plan, up-conversion and down-conversion process, choosing passive and active components for low power
consumption and better noise figure. The entire system was designed in AWR MWO environment.
EXPERIENCE
Apple Inc. RF Regulatory Design Intern Aug 2015 – Jan 2016
 WiFi-802.11 a/b/g/n/ac, Bluetooth, BLE and NFC radiated testing at 3m and 5m Semi Anechoic Chamber and also
performed conducted testing on various Apple products.
 Parameters like Harmonics, Analog Front end spurs and Channel power of the on board Power Amplifiers were
measured to meet regulatory specifications for all MIMO and SISO devices during product cycle phase.
 S-parameters measurements of Conducted Racks for calibration, Validation of Automation against manual testing,
Calibration of Radiated 3m and 5m Semi-anechoic chambers, correlation analysis between chambers.
 Debugging of harmioncs, issues related to on-board radiations with design engineers and solving the issues.
Accord Software and Systems Pvt Ltd Senior Systems Engineer July 2010 – July 2014
Over 4 years of experience in design, development and testing of GNSS (GPS, GLONASS, and IRNSS) CDMA receivers
and RF down-converters for L5, L1 and S band frequencies.
IRNSS User Receiver Mar 2013 – July 2014
 Design, testing and integration of L5, L1 and S band antennas into a single module using a spiral patch antenna
with selective filters and a wideband LNA, with testing performed in an anechoic chamber.
 Implemented Dual frequency IRNSS positioning, Integrated GPS/GLONASS modules with IRNSS, multipath
mitigation modules, In-band Adaptive CWI mitigation in SPARTAN-6 FPGA using an IIR filter design.

2. IRNSS Reference Receiver Sept 2011 – Mar 2013
 Designed and tested RF four layer RF board down-converter for IRNSS frequency bands (1.176GHz & 2.492GHz)
analysed signal flow, chain gain and addressed the radiation problems on boards.
 Implementation of timing modules, PPS generation block, correlator logics and In-band DME Pulse Mitigation
using Digital Pulse Blanking algorithm in SPARTAN-6 and Control logic in SHARC DSP.
Two Channel High Sensitivity Data Link Receiver Dec 2010 – Aug 2011
 Implemented a FFT based correlator for fast acquisition and data bit demodulation for CDMA receiver. The data
rate was 9.6kbps and signal acquisition at -108 dBm was achieved within 5ms.
PUBLICATIONS “DME Interference Mitigation through Blanking”, Pranav P Ginde, Nikhil M Anand, Harish A H,
Ashwitha L S; NAVCOM-2012 on December; Organized by Defence Research and Development
Organisation (DRDO), Ministry of Defence, Govt. of India