1. CHINMAY PRASAD TIKHE
2656 Ellendale Place, #1, LA, CA 90007 | tikhe@usc.edu | 213-298-5073 | https://www.linkedin.com/in/chinmayprasadtikhe
EDUCATION
University of Southern California, Los Angeles, CA. May 2017
Master of Science in Electrical Engineering (Mixed Signal VLSI Design) (GPA: 3.48)
Vishwakarma Institute of Technology (VIT), Pune, Maharashtra, India. June 2014
Bachelor of Technology in Electronics & Tele-communication Engineering with Honors in VLSI Design. (CPI – 9.02/10)
SKILLS
 Software Languages: C, Verilog & PERL basics. Some basic knowledge of C++ & SQL.
 Tools: Cadence Virtuoso, Eagle CAD, LTSPICE, MATLAB, Diptrace, Arduino, Keil & ELDO SPICE Simulator.
EXPERIENCE
Cereble Robotics LLP, Pune, Maharashtra, India. May 2016 – August 2016
Hardware Design Intern
 Safe Load Indicators (SLI) in Cranes.
- Designed Safe Load Indicator schematic and performed PCB Layout Verification using Eagle CAD.
- SLI comprised of a micro-controller(AtMega2560) which processed & monitored the input signals received
from sensors like Load, Length, Angle, ATB & Bypass mounted on crane. The signals were transmitted
either by a wired media or via ZIGBEE. Based on processed data, status was conveyed to the crane operator.
 Fuel Trackers
- Designed Calibration Flowcharts for pressure sensors in fuel trackers used in Fuel Dispensers.
- Designed schematic to interface Micro-SD card & Real Time Clock module with micro-controller.
PROJECTS
Design of Operational Transconductance Amplifier (OTA) for M-DAC December 2016
 Designed an OTA for M-DAC in 45 nm Technology using Cadence Virtuoso.
 Gain of 63 dB, Unity Gain Bandwidth (UGBW) of 54 GHz and Output Voltage Swing of 995 mV was achieved.
 OTA comprised of two amplifiers connected in parallel to achieve the functionality of large gain and high UGBW.
One among the two had high gain and moderate bandwidth while other had low gain and large bandwidth.
 Simulating above OTA in M-DAC provided SNR of 22dB.
Fully Differential Gain-Boosted Telescopic Amplifier Tape-out December 2016
 Designed fully differential gain boosted telescopic amplifier in 130nm CMOS Technology.
 Schematic and Layout of the amplifier with ESD protection were designed using Cadence Virtuoso.
 Gain of 54 dB, UGBW of 200 MHz and Output Voltage Swing of 1.295 Vp-p was achieved.
 All the corner cases i.e. 'ss', 'tt', and 'ff' were tested and verified.
General Purpose Microprocessor May 2016
 Microprocessor’s Schematic and Layout were designed in collaboration with two other members using Cadence
Virtuoso in 180 nm technology.
 A 5-stage pipeline was implemented. The I.F. stage & I.D. stage of the pipeline were implemented using Perl.
 EX stage comprised of Carry Skip Adder, 8-bit 2's Complement Multiplier, AND gate & OR gate.
 Memory Stage comprised of 1-Kbit SRAM Array. SRAM Array comprised of 6-T SRAM cell as a basic cell.
 The Instruction set comprised instructions like LOAD & STORE, arithmetic instructions like Signed Addition,
Signed Multiplication, Min-Max number between two and logical instruction like AND, OR & XOR.
Design of Low Noise Amplifier (LNA) May 2016
 Collaboratively designed LNA with two other members in 100 nm technology using AWR Microwave Office.
 Power Gain of 11.61 dB was achieved in frequency range 3.3 GHz to 3.4 GHz with Noise Figure of 1.8 dB.
 A good matching was observed as Voltage Standing Wave Ratio at Input & Output was 1.15 & 1.04 respectively.
Folded Cascode Operational Amplifier December 2015
 Designed Folded Cascode Op-amp in 45nm technology using LTSPICE with an Open Loop Gain of 90dB
 Supply Independent Current Source was designed to bias the Op-amp which had a supply sensitivity of 0.01.
 Settling time less than 5ns and CMRR of 112 dB was achieved.
Swarm Robotics May 2014
 Designed miniature sized client robots using Diptrace which easily fit in the palm of the hand.
 A 2-D Schematic of pattern was sent to server via Bluetooth. The Server computed the optimal path and
distributed the work among client robots, which followed line tracing algorithm to collaboratively construct given
schematic in least possible time. The communication media between server & client robots was ZIGBEE.
 Best Project Award for Swarm Robotics awarded to my team in Intra-College event Prakalp in VIT.
ACHIEVEMENTS
 Completed training program in VLSI Design & Embedded Systems at I2
IT Pune.
 Cumulative Performance Index (CPI) of 10/10 in VLSI Honors for 3 consecutive semesters.