it contains all initilisation command words

1. WELCOM
E

2. 8259A
It is programmable interrupt controller.
Able to handle a number of interrupts at a time.
Takes care of a number of simultaneously
appearing interrupt requests along with their types
and priorities.
Compatible with 8-bit as well as 16-bit processors.

3. NEED FOR 8259A
 8085 Processor has only 5 hardware
interrupts.
 Consider an application where a number of I/O
devices connected with CPU desire to transfer
data using interrupt driven data transfer mode.
In this process more number of interrupt pins
are required.
 In these multiple interrupt systems the
processor will have to take care of priorities.

4. ICWS OF 8258A
Before start functioning, 8259 must
be initialized by writing two to four
command words into their respective
command word registers.

5. TYPES OF ICWS
 There are four types of
initialization command words.
1.ICW1
2.ICW2
3.ICW3
4.ICW4

6. 8259A PIC- COMMAND WORDS
 Whenever a command is issued with
A0=0 and D4=1 this is interpreted as initialization
command word1 (ICW1) icw starts the
initialization sequence during which the
following automatically occur.

7. 8259A PIC- ICW1
The following initialization procedure Carried out internally
when ICW1 is loaded.
a) The edge sense circuit is reset i.e. by default 8259A
interrupts are edge sensitive.
b) IMR is cleared.
c) IR7 input is assigned lowest priority.
d) Slave mode address is set to 7.
e) Special mask mode is cleared and status read is set
to IRR.
f) If IC4=0, all functions of ICW4 are set to Zero.
Master/slave bit in ICW4 bit is used in buffered mode
only.

8. INITIALIZATION SEQUENCE OF 8259A
ICW1 & ICW2 are
Compulsory command
Words in the initialization
sequence.
ICW3 & ICW4 are
Optional.
ICW3 is read only when
More than one 8259 used in the
system ( SNGL bit in
ICW1 is 0).

9. ADI=1 for 8086 based system
For 8086 Don’t Care
p

10. For 8085 system they are filled by A15-A11 of the interrupt vector address and
Least significant 3 bits are same as the respective bits of the vector address.
For 8086 system they are filled by most significant 5 bits of interrupt type and
the least significant 3 bits are 0, pointing to IR0.

12. If BUF=0,M/S is to be neglected.

13. THANK
S