Microprocessor presentation

WELCOME
RESPECTED TEACHERS
&
DEAR FELLOWS

SYSTEM CLOCK & BUS CYCLE

GROUP MEMBERS

SYED WASI SHAH

SYED MOHSIN SHAH

M.SAMI-UL-HAQ HASHMI

MUHAMMAD UMER FAROOQ

PRESENTATION LAYOUT

(a). SYSTEM CLOCK OR CLOCK (b). BUS CYCLE AND
GENERATOR TIME STATES
1. Definition 1. Definition
2. Clock signal 2. Applications
3. Applications
4. Block Diagram (8284A) 3. Four Time States
5. Exp of Block Diagram 4. Idle State
6. CLK voltage timing 5. Wait State
characteristics for a 5MHZ 6. How to read a timing diagram
processor
7. Pin Diagram (8284A) 7. Example of bus cycle
8. Explain Pin Configuration
9. Connecting the 8284 to the 8088
10. Relationship between CLK and
PCLK

(a) SYSTEM CLOCK OR
CLOCK GENERATOR
1. Definition (1) DEFINITION:
A clock generator or system clock is
2. Clock signal a circuit that produces a timing
3. Applications signal (known as a clock signal and
behaves as such) for use in
4. Block Diagram (8284A) synchronizing a circuit's operation.
5. Exp of Block Diagram 1. A clock signal of some frequency
generated by system clock,
6. CLK voltage timing operates the microprocessor on
characteristics for a 5MHZ that frequency.
processor 2. The standard 8088 operates at 5
MHz and the 8088-2 operates at 8
7. Pin Diagram (8284A) MHz
8. Explain Pin Configuration 3. The 8086 is manufactured in three
speeds: 5-MHz 8086, 8-MHz 8086-
9. Connecting the 8284 to the 8088 2, and the 10-MHz 8086-1
10. Relationship between CLK and 4. The CLK is externally generated by
PCLK the 8284 clock generator and driver
IC.

(a) SYSTEM CLOCK OR
CLOCK GENERATOR
1. Definition (2) CLOCK SIGNAL:
2. Clock signal
Clock signal 1. A clock signal is a particular
3. Applications type of signal that oscillates
4. Block Diagram (8284A) between a high and a low state.
5. Exp of Block Diagram 2. To find frequency(f) of clock
signal. f=1/p(period)
6. CLK voltage timing
characteristics for a 5MHZ
processor
7. Pin Diagram (8284A)
PCLK

(a) SYSTEM CLOCK OR
CLOCK GENERATOR
1. Definition (3) APPLICATIONS:
1. The time base for synchronization
2. Clock signal of the internal and external
3.
3. Application
Applications operations of the microprocessor in
a microcomputer system is
4. Block Diagram (8284A) provided by the clock (CLK) input
5. Exp of Block Diagram signal.
2. The clock signal in a
6. CLK voltage timing microprocessor allows
characteristics for a 5MHZ synchronization of several
processor components of the microprocessor.
The correctness of the computation
7. Pin Diagram (8284A) of the microprocessor depends
8. Explain Pin Configuration upon efficient and balanced
distribution of the clock signal.
9. Connecting the 8284 to the 8088 The clock generator generates the
clock signal.
3. also provides the READY signal
PCLK for the insertion of wait states into
the CPU bus cycle.

(a) SYSTEM CLOCK OR
CLOCK GENERATOR
1. Definition (4) Block Diagram (8284A):
2. Clock signal
3. Application
4. Block Diagram (8284A)
5. Exp of Block Diagram
processor
PCLK

(a) SYSTEM CLOCK OR
CLOCK GENERATOR
1. Definition (5) Exp Block Diagram:
2. Clock signal
3. Application
Exp of Block Diagram
processor
1. Crystal Oscillator
2. +3 and +2 sync
8. Buffer Pin Configuration
3. Explain
4. Connecting the 8284
9. Latches and Flip Flop to the 8088
PCLK

(5) EXPLAINATION OF BLOCK DIAGRAM (8284A):

1. XTAL OSCILLATOR:
8284 is used with the 8088
is to connect either a
15MHZ or 24MHZ crystal
between its X1 and X2
inputs.
2. A series capacitor CL is
also required. Its typical
value when used with the
15MHZ crystal is 12pF.
3. The CLK output of the
8284 can be directly
connected to the CLK
input of the 8088.The 8284
connects to the 8086 in
exactly the same way.


3. The fundamental crystal frequency
is divided by 3 within the 8284 to
give either a 5 or 8MHZ clock
signal. This signal is internally
buffered and output at CLK. For
PCLK +2 sync(CLK frequency
divided into 2).
4. A buffer is a means of isolating a
signal source circuit from the
loading circuit. They are generally
needed when the signal source does
not have sufficient capacity to
deliver the current demanded by the
load circuit. If buffers are not used, a
problem called input loading results
and this may cause the circuit to
malfunction or to become damaged.
5. In digital circuits, the buffers
reproduce the sequence of 1's and 0's
received from one circuit and make
them available to another circuit at a
higher power level. A buffer is like a
non-inverting amplifier with a gain
of unity.

(a) SYSTEM CLOCK OR
CLOCK GENERATOR
1. Definition (6) CLK voltage and timing
2. Clock signal characteristics for a 5MHZ
3. Application processor:
processor
PCLK

(6) CLK voltage and timing characteristics for a 5MHZ:

1. The signal is specified at metal
oxide semiconductor (MOS)-
compatible voltage levels and
not TTL levels.
2. Its mini and max low logic
levels are VLmin= -0.5V and
VLmax= 0.6V, respectively .
3. Its mini and max high logic
levels are VHmin= 3.9V and
VHmax= Vcc +1V.

(6) CLK voltage and timing characteristics for a 5MHZ:

4. The period of the clock signal of
a 5MHZ 8088 can range from a
minimum of 200ns to a
maximum of 500ns.
5. The maximum rise and fall
times of its edges equal 10ns.
6. Duration of high and low logics
are 68.66ns min and 118.33ns
min resp.

(a) SYSTEM CLOCK OR
CLOCK GENERATOR
1. Definition (7) PIN DIAGRAM (8284A):
2. Clock signal
3. Application
processor
Pin Diagram (8284A)
PCLK

(a) SYSTEM CLOCK OR
CLOCK GENERATOR
1. Definition (8)Exp PIN DIAGRAM (8284A):
2. Clock signal
3. Application
processor
Exp Pin Diagram (8284A)
Pins are divided into three category:
1.Power Supply Pins
PCLK 2.Input Pins
3.Output Pins

(8) EXPLAIN PIN CONFIGURATION (8284A):

1. Power supply pins:
a) Vcc…..(18# pin)
Used for supply power. e.g
+12vcc or +5vcc.
b) GND…..(9# pin)
Used for connecting the ic to lower
potential or ground.

(8) EXPLAIN PIN CONFIGURATION (8284A):

2. Input pins:
a).Reset in …..(11 # pin )
b).X1 and X2 (crystal in)…..(17# and
16# pins) resp.
c).F/C (frequency/clock select)…..(13
#pin).
d).EFI(external freq in)…..(14# pin).
e).CSYNC(clock synchronization)…..(1#
pin)
f).RDY1 and AEN1(ready1 and address
enable1)…..(4# and 3# pins) resp.
g).RDY2 and AEN2(ready2 and address
enable2)…..(6# and 7# pins) resp.
h).ASYNC(synchronization
select)…..(15# pin).

(8) EXPLAIN PIN CONFIGURATION (8284A)
INPUT PINS:

RES(RESET IN):
1. This is an input active-low signal
to generate RESET.
2. It is connected to the power-good
signal from the power supply.
3. When the power switch is turned
on, assuming that the power
supply is good.
4. a low signal is provided to this
pin,
5. and the 8284 in turn will activate
the RESET pin.
6. forcing the 8088/86 to reset; then
the microprocessor takes over.
This is called a cold boot.

INPUT PINS:

X1 and X2 (crystal in):
1. XI and X2 are the pins to which
a crystal is attached.
2. The crystal frequency must be 3
times the desired frequency for
the microprocessor.
3. The maximum crystal for the
8284A is 24 MHz and 30MHz
for the 8284A-1.
4. The IBM PC is connected to a
crystal of 14.31818 MHz.
5. For some turbo compatibles,
it is 24 MHz.

INPUT PINS:

F/C (frequency/clock select):
1. This pin provides an option for
the way the clock is generated.
2. If connected to low, the clock is
generated by the 8284 with the
help of a crystal oscillator.
3. If it is connected to high, it
expects to receive clocks at
the EFI pin.
4. Since the IBM PC uses a
crystal, this pin is connected
to low.

INPUT PINS:

EFI (external frequency in):
1. External frequency is connected
to this pin if F/C
has been connected to high.
2. In the IBM PC this is not
connected since a crystal is
used instead of an external
frequency generator.
3. In some cases (such as the
Turbo PC), this pin is used to
provide clock frequency in place
of XI and X2.

EFI (external frequency in):
Example

1. EFI - changed from earth to the
OSC input from other 8284A
(EFI=external frequency input)
2. F/C' - changed from earth to Vcc
(5v) because now the chip is
using F(frequency) input instead
of C(crystal) input
3. Both X1 & X2 - grounded

INPUT PINS:

CSYNC(clock synchronization):
1. This active-high signal is used to
allow several 8284 chips to be
connected together and
synchronized.
2. The IBM PC only uses one
8284; therefore, this pin is
connected to low.

INPUT PINS:

RDY1 and AEN1:
1. RDY1 is active high and AEN1
(address enable) is active low.
2. They are used together to
provide a ready signal to the
microprocessor, which will insert
a WAIT state to the CPU
read/write cycle.
3. In the IBM PC, RDY1 is
connected to DMAWAIT and
AEN1 is connected to
RDY/WAIT.
4. They allow the wait state to be
inserted either by the CPU or by
DMA.

INPUT PINS:

RDY2 and AEN2:
1. These function exactly like RDY1 and
AEN1.
2. These extra RDY and AEN signals are
provided to allow for a
multiprocessing system.
3. It allows other general-purpose CPUs
such as the 8088/86 to gain control
over the buses.
4. In the IBM PC, RDY2 is connected to
low, AEN2 is connected to high, which
permanently disables this
function since there is only one
8088/86 microprocessor in the
system.
5. In cases of multiprocessor
systems, these signals are used
to coordinate access over the
buses by different CPUs

INPUT PINS:

ASYNC(READY
SYNCHRONIZATION
SELECT):
1. This is called ready
synchronization select.
2. An active low is used for devices
that are not able to
adhere to the very strict RDY
setup time requirement.
3. In the IBM PC this is
connected to low, making
the timing design of the
system easier with slower
logic gates.

OUTPUT SIGNALS:

3. OUTPUT SIGNALS:
a).Reset …..(10# pin).
b). OSC(Oscillator)…..(12# pin).
c).CLK(clock)…..(8# pin).
d).PCLK(peripheral clock)…..(2#
pin).
e).Ready…..(5# pin).

OUTPUT SIGNALS:

Reset:
1. This is an active-high signal that
provides a RESET signal to the
8088/86 microprocessor.
2. It is activated by the RES
input signal discussed
earlier.

OUTPUT SIGNALS:

Oscillator(OSC):
1. This provides a clock
frequency equal to the crystal
oscillator and it is TTL
compatible.
2. Since the IBM crystal
oscillator is 14.31818 MHz,

OUTPUT SIGNALS:

Clock(CLK):
1. This is an output clock frequency
equal to one-third of the crystal
oscillator, or EFI input frequency, with
a duty cycle of 33%. This is connected
to the clock input of
the 8088/86 and all other devices
that must be synchronized with
the CPU.
2. In the IBM PC it is connected to
pin 19 of the 8088 microprocessor.
3. This frequency, 4.772776 MHz
(14.31818 divided by 3), is the
processor frequency on which
all of the timing calculations of
the memory and I/O cycle are
based.

OUTPUT SIGNALS:

Peripheral Clock(PCLK):
1. This frequency is one-half of
CLK (or one-sixth of the crystal)
with a duty cycle of
50% and is TTL compatible.
2. In the IBM PC this 2.386383
MHz is provided to the 8253 or
8254 timer to be used to generate
speaker tones, and other
functions.Also provided to 8279
keyboard/display interfacing ic.

OUTPUT SIGNALS:

Ready:
1. This signal is connected to
READY of the CPU.
2. In the IBM PC it is used to
signal the 8088 to indicate if the
CPU needs to insert a wait state
due to the slowness of the
devices that
the CPU is trying to contact.
3. At low logic, cpu is at wait state.

(a) SYSTEM CLOCK OR
CLOCK GENERATOR
1. Definition (9) CONNECTING THE 8284 TO
2. Clock signal 8088/8086:
3. Application
processor
Connecting the 8284 to 8088
PCLK

(9) CONNECTING THE 8284 TO 8088/8086:

1. 8284 CLK connected to 8086 CLK to
give it synchronized clocks.
2. 8284 Reset connected to 8086 Reset to
forcing the 8088/86 to reset; then the
microprocessor takes over. This is
called a cold boot.
3. Ready pin is used to
signal the 8088 to indicate if the CPU
needs to insert a wait state due to the
slowness of the devices that
the CPU is trying to contact.

(a) SYSTEM CLOCK OR
CLOCK GENERATOR
1. Definition (10) RELATIONSHIP BETWEEN
2. Clock signal CLK AND PCLK:
3. Application
processor
Relationship between CLK and
PCLK

(10) RELATIONSHIP BETWEEN CLK AND PCLK:

Two clocks outputs on the 8284.
1. PCLK(Peripheral clock)
2. OSC CLK( oscillator clock)
a). These signals are provided to driver
peripheral IC’s .
b). The clock signal output at PCLK is half the
frequency of CLK.
c). For instance, if an 8088 is operated at
5MHZ, PCLK is 2.5MHZ .
d). Also it is at TTL compatible levels rather
than MOS levels.
CLK = 33% crystal/EFI = 0.33 (15Mhz) =5 Mhz
e). Osc output is at the crystal frequency , which PCLK = 50% crystal/EFI = 0.5 (15Mhz) =7.5Mhz
is three times that of CLK.

PRESENTATION LAYOUT

(a) SYSTEM CLOCK OR CLOCK (b) BUS CYCLE AND
GENERATOR TIME STATES
1. Definition 1. Definition
2. Clock signal 2. Applications
3. Applications
4. Block Diagram (8284A) 3. Four Time States
5. Exp of Block Diagram 4. Idle State
6. CLK voltage timing 5. Wait State
characteristics for a 5MHZ 6. How to read a timing diagram
processor
7. Pin Diagram (8284A) 7. Example of bus cycle
PCLK

(b) BUS CYCLE AND
TIME STATES

1. Definition
Definition (1) DEFINITION:
2. Applications A single transaction between the
3. Four Time States main memory and the CPU.
4. Idle State 1. A bus cycle corresponds to a
5. Wait State sequence of events that start with
6. How to read a timing diagram an address being output on the
7. Example of bus cycle system bus followed by a read or
write data transfer.
2. During these operations, the
MPU produces a series of control
signals to control the direction
and timing of the bus.

(b) BUS CYCLE AND
TIME STATES

1. Definition (2) APPLICATIONS:
2. Application
Applications 1. A bus cycle defines the basic
3. Four Time States operation that a microprocessor
4. Idle State performs to communicate with
external devices.
5. Wait State
2. Bus cycle helps to manage data
6. How to read a timing diagram on bus.
7. Example of bus cycle

(b) BUS CYCLE AND
TIME STATES

1. Definition (3) FOUR TIME STATES:
2. Application 1. The bus cycle of the 8088 &
3. Four Time States
Four Time States 8086 microprocessor consists of
4. Idle State at least four clock periods. These
four time states are called…
5. Wait State
a) T1 State
6. How to read a timing diagram
b) T2 State
c) T3 State
d) T4 State

(3) FOUR TIME STATES:

READ WRITE
a). T1 State:(Address Out State) a) T1 State:(Address Out State)
CPU Drives Valid Address on Address CPU Drives Valid Address on Address
Bus. Bus.

b) T2 State:(Transaction Type) b) T2 State:(Transaction Type)
IOR or MEMR go Active. IOW or MEMW and Data Bus go
Active.
c) T3 State:(Memory or I/ORespond)
CPU “waits” for Memory (or I/O) to c) T3 State:(Memory or I/ORespond)
drive data bus. CPU Continues to Drive Data Bus.

d) T4 State:(Data Latch State) d) T4 State:(Data Latch State)
CPU Latches Data Bus Signals into CPU Drives Data Until End of T4
register. Allowing Memory (or I/O) to Latch
Data Bus Signals in.
These four clock states gives a
bus cycle duration of
125ns*4=500ns in an 8MHZ
8088 system.

(b) BUS CYCLE AND
TIME STATES

1. Definition (4) IDLE STATE:
2. Application 1. If no bus cycles are required, the
3. Four Time States microprocessor performs what
4. Idle State are known as idle states.
Idle State
5. Wait State 2. During these states, no bus
activity takes place. Each idle
6. How to read a timing diagram state is one clock period long,
7. Example of bus cycle and any number of them can be
inserted between bus cycles.
3. Idle states are performed if the
instruction queue inside the
microprocessor is full and it does
not need to read or write
operands from memory.

(b) BUS CYCLE AND
TIME STATES

1. Definition (5) WAIT STATE:
2. Application 1. Wait states can also be inserted into a bus
cycle.
3. Four Time States
2. This done in response to a request by an
4. Idle State event in external hardware instead of an
5. Wait State internal event such as a full queue.
5. Wait State
3. Ready input in 8284 of the MPU is
provided specifically for this purpose.
7. Example of bus cycle 4. Logic zero at this input indicates that the
current bus cycle should not be
completed.
5. As long as, Ready is held at the 0 level,
wait states are inserted between states T3
and T4 of the current bus cycle.

(b) BUS CYCLE AND
TIME STATES

1. Definition (6) HOW TO READ A TIMING
2. Application DIAGRAM:
3. Four Time States Definition:
4. Idle State A timing diagram is a
5. Wait State representation of a set of signals in
How to read a timing diagram the time domain.
7. Example of bus cycle Here we discuss about,
how to read timing diagram of bus
cycle.

(6) HOW TO READ A TIMING DIAGRAM:

(b) BUS CYCLE AND
TIME STATES

1. Definition (7) EXAMPLE OF BUS CYCLE:
2. Application 1. Memory Read Bus Cycle
3. Four Time States 2. Memory Write Bus Cycle
4. Idle State
5. Wait State
Example of bus cycle

1. Memory Read Bus Cycle

During period T1
1. The 8086 outputs the 20-bit
address of the memory
location to be accessed on its
multiplexed address/data bus.
BHE is also output along
with the address during T1.
2. At the same time a pulse is
also produced at ALE. The
trailing edge or the high level
of this pulse is used to latch
the address in external
circuitry.
3. Signal M/IO is set to logic 1
and signal DT/R is set to the
0 logic level and both are
maintained throughout all
four periods of the bus cycle.


Beginning with period T2
1. Status bits S3 through S6
are output on the upper four
address bus lines.
2. This status information is
maintained through periods
T3 and T4.
3. On the other hand,
address/data bus lines AD0
through AD7 are put in the
high-Z state during T2.
4. Late in period T2, RD is
switched to logic 0. This
indicates to the memory
subsystem that a read cycle
is in progress.
5. DEN is switched to logic 0
to enable external circuitry
to allow the data to move
from memory onto the
microprocessor's data bus.


During period T3
1. The memory must provide
valid data during T3 and
maintain it until after the
processor terminates the
read operation.
2. The data read by the 8086
microprocessor can be
carried over all 16 data bus
lines.
During T4
1. The 8086 switches RD to
the inactive 1 logic level to
terminate the read
operation.
2. DEN returns to its inactive
logic level late during T4 to
disable the external
circuitry.

2. Memory Write Bus Cycle

During period T1
1. The address along with
BHE are output and
latched with the ALE
pulse.
2. M/IO is set to logic 1 to
indicate a memory cycle.
3. However, this time DT/R
is switched to logic 1.
This signals external
circuits that the 8086 is
going to transmit data
over the bus.

2. Memory Write Bus Cycle

Beginning with period
T2
1. WR is switched to logic
0 telling the memory
subsystem that a write
operation is to follow.
2. The 8086 puts the data
on the bus late in T2 and
maintains the data valid
through T4.
3. Data will be carried over
all 16 data bus lines.
4. DEN enables the
external circuitry to
provide a path for data
from the processor to the
memory.

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Microprocessor presentation

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