Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP

1. Level-Accurate
Peak Activity Estimation in
Combinational Circuits
Using BILP
VDAT 2013
Jaynarayan Tudu, IISc Bangalore
Deepak Malani, IIT Bombay
Virendra Singh, IIT Bombay
malani.deepak (at) gmail.com

2. Outline
Introduction and Motivation
– Power Estimation
Previous Work
ILP based formulation of combinational logic
– Constraints
– Optimization Function
– Partition Level
Performance on ISCAS Benchmarks
08/01/132

3. Introduction
08/01/133
CL* Vdd * Ptransition * fclock
2
Power dissipation
Static Power
Vdd * Istatic
Dynamic Power

4. Motivation
Estimation of peak-power dissipation
determines
– Maximum current demand
– VDD droop (due to IR-drop)
– Design of power delivery network (PDN)
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IR-dropVDD
Clock

5. Power Estimation Approaches
Vector-less
– Probabilistic
Wang et al, VLSID-1996; Wu et al., CAD-2001
Vector-based
– Input pattern generation
– Pseudo Boolean SAT (PBS)
F. Aloul et al, Elsevier-2007; Mangassarian et al, DATE 2007
– Integer Linear Program (ILP)
VDAT-2012
08/01/135

6. Mathematical Expressions for logic
gates
*CNF: Conjunctive Normal Form
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GATE Type Boolean
Expression
Algebraic
Expression
SAT* Expression
x z z= x z = 1 - x (x+z).(x+z)
x z
y
z = x.y z = 1 – x.y (x+z).(y+z).
(x+y+z)

7. Boolean Satisfiability based
technique (SAT)
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Using SAT-based techniques in power estimation, F. Aloul et al, Elsevier, 2007

8. ILP Based Approach
Steps
1) Variable definition
2) Constraints
3) Optimization function
4) Solver (iterative)
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ILP Based Approach for IVC Toggle Maximization in Combinational Circuits,VDAT-2012
ILP Formulation:

9. ILP Formulation
2a) I/O Constraints
– INV : y = 1 - x
– NAND2 : y = 1 – x1* x2
– NOR2 : y = 1 – (x1 + x2) + x1* x2
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10. ILP Formulation
2b) Product Linearization Constraint
– z = 1 – x* y
– Define: p = x* y s.t.
z = 1 – p
p ≤ x
p ≤ y
x + y – p ≤ 1
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11. Example: y = 1 – x1* x2
p = x1* x2 s.t.
y = 1 – p
p ≤ x1
p ≤ x2
x1 + x2 – p ≤ 1
z = 1 - y* x3
q = y* x3 s.t.
z = 1 – q
q ≤ y
q ≤ x3
y + x3 – q ≤ 1
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x1
x2
x3
y
z
ILP Formulation

12. ILP Formulation
2c) Toggle variable
– For each net five variables are defined
– x1 and x2 successive logic values of net ‘x’
tgate_x = x1.x2 + x1.x2
3) Optimization function
– Maximize ∑ (tgate_i)
i = 1:N
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13. ILP Formulation - Summary
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Variable
definition
Constraints
I/O Linearization Toggle
Optimization function
Toggle Maximization
Solver
Generate successive pair of
primary input vectors

14. Limitations
Whole circuit simulation
– Assumption: All nets toggle simultaneously
– Zero delay
– Not realistic
Simulation time is large for big benchmarks
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15. Proposed Solution
Partition the logic into levels
Apply ILP to each level independently to compute peak
activity
Maximum of peak power over all levels is the worst case
peak activity
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16. Level-BILP
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Level Objective Function:
l = 1 to Level
i = 1 to number of nets
in l
Constraints are defined for gates upto Level-i only
Maximum Peak Activity:

17. Performance Analysis
ISCAS-85 benchmarks
Machine
– Dual Core AMD Opteron, @1GHz
ILP Solvers
– GLPK, CPLEX
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18. Peak Activity Comparison:
Whole circuit - Level partitioned
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ISCAS’ 85 Benchmark Circuits
TotalToggleCount
Whole Circuit: ILP Based Approach for IVC Toggle Maximization, VDAT-2012

19. Run Times:
Whole circuit - Level partitioned
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*Re-convergent fan-out
Circuits Whole Circuit(sec) Proposed (sec)
C432 8.86 9.25
C499* 3406 34.45
C880 21.55 22.34
C1355* 3616 44.92
C1908 2371 269.2
C2670 559 545
Whole Circuit: ILP Based Approach for IVC Toggle Maximization, VDAT-12

20. Conclusion
Toggles are not simultaneous
Occurrence of transitions in a combination
logic follows the order of gates at a level
Logic partitioning into Levels is more realistic
Simulation time is reduced by a factor of 10 in
a few circuits, by level partitioning
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21. Further Work
Fanout consideration (weighted function)
Consider: Glitches and Actual gate delays
Extension of ILP formulation to sequential
circuits, by unfolding
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22. Level-Accurate
Peak Activity Estimation in
Combinational Circuits
Using BILP
VDAT 2013
Jaynarayan Tudu, IISc Bangalore
Deepak Malani, IIT Bombay
Virendra Singh, IIT Bombay