vlsi lecture

1. CMOS Delay
Dr. Ahmed Youssef
COE 360
Principles of VLSI
Design

2. Definitions

3. Delay Definitions
• tpdr: rising propagation delay
– From input to rising output crossing VDD/2
• tpdf: falling propagation delay
– From input to falling output crossing VDD/2
• tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
• tr: rise time
– From output crossing 0.2 VDD to 0.8 VDD
• tf: fall time
– From output crossing 0.8 VDD to 0.2 VDD

4. Delay Definitions
• tcdr: rising contamination delay
– From input to rising output crossing VDD/2
• tcdf: falling contamination delay
– From input to falling output crossing VDD/2
• tcd: average contamination delay
– tpd = (tcdr + tcdf)/2

5. Definitions
Propagation Delay – Time from last input
change until last output change.
Contamination Delay – Time from first input
change until first output change.
Best-case (contamination) delay can be substantially
less than propagation delay.

6. Definitions
• A timing analyzer computes the arrival times, i.e.,
the latest time at which each node in a block of
logic will switch.
• The nodes are classified as inputs, outputs, and
internal nodes.

7. Definitions
• The arrival time ai at internal node i depends on
the propagation delay of the gate driving i and the
arrival times of the inputs to the gate:

8. Definitions
• The slack is the difference between the required and
arrival times.
• Positive slack means that the circuit meets timing.
• Negative slack means that the circuit is not fast enough.

9. Example
• Nodes annotated with arrival times. If the outputs
are all required at 200 ps, the circuit has 60 ps of
slack.
9

10. Delay Estimation

11. 11
11
11
Delay Calculation for CMOS Gate
In order to calculate the delay of the CMOS gate, we find an
equivalent inverter (with equivalent pull-up and pull-down
resistances) and calculate TD=0.5 CL(RP+RN) = (Tr + Tf)

12. Delay Calculation for CMOS Gate
Where Tr and Tf of the equivalent
inverter = worst case Tr and Tf of the
gate
Worst case Tr occur when the O/P is
charged (or pulled-up) through the
longest chain of series PMOS
transistors: e.g. for the PU block
below
Worst case charging is when B = D
= H = 1 And A = C = E = 0 i.e.
charging through A,C, & E

13. Delay Calculation for CMOS Gate
Similarly, worst case Tf occurs when discharging the output
through the longest discharging path
For the PD block below, Worst case : 1,4,6 are ON or 2,4,6 or
3,4,6 while every other transistor is off

14. Delay Calculation for CMOS Gate
𝑅𝑃𝑒𝑓𝑓
=
𝑉𝐷𝐷 − 𝑉𝑡𝑝
2𝐼𝑆𝐷𝑠𝑎𝑡
∗ 𝑊
𝑝𝑒𝑓𝑓
𝑅𝑁𝑒𝑓𝑓
=
𝑉𝐷𝐷 − 𝑉𝑡𝑛
2𝐼𝐷𝑆𝑠𝑎𝑡
∗ 𝑊
𝑛𝑒𝑓𝑓
Req1 + Req2 + Req 3 = Reff 
(VDD – Vth / 2.IDsat ).( 1/W1 + 1/W2 + 1/W3 )
= (VDD – Vth / 2.IDsat. Weff )
 1/Weff = 1/W1 + 1/W2 + 1/W3 …..
W1
W2
W3
Weff
If W1 = W2 = W3 = WN  Weff = WN/3

15. Example 1
Calculate the maximum frequency of operation of an
AOI 222 CMOS gate with a 100 fF load, assuming
that all NMOS transistor are 9 μm wide and 1 μm
long. All PMOS transistors are 10/1 μm use the 1 μm
technology ISDsat = 200 μA/μm , VtN = | VtP | = 0.8V ,
VDD = 5V

16. Example 1

17. TD avg = 0.5 CL ( RP + RN )
RP eff = (VDD - | VtP | ) / ( 2 IDsat . WP eff) ,
WP eff = WP / 3 = 10/3 = 3.33 μm
RP eff = 4.2 / ( 400x10-6 x 3.33) = 3.15 KΩ
RN eff = ( VDD - VtN ) / ( 2 IDsat . WN eff) , WN eff = WN/2 = 2.5 μm
RN eff = 4.2 / (400x10-6 x 2.5) = 4.2 KΩ
TD avg = 0.5 CL ( RP + RN ) = 0.5 * ( 100x10-15*(3.15+4.2)x103) = 36.75 nS
Fmax = 1/TD avg = 27.2 MHz
Example 1

18. Example 2
Calculate the maximum frequency
of operation given that: the load is
200fF, using 1μm technology, ISDsat
= 300 μA/μm, VtN = | VtP | = 0.5V,
VDD = 10V (Hint: the width of
NMOS and PMOS transistors is
indicated on the figure)

19. Example 3
Calculate the maximum frequency
of operation given that: the load is
150fF, using 0.5μm technology,
ISDsat = 250 μA/μm, VtN = | VtP | =
0.3V, VDD = 15V, (W/L)N=6 and
(W/L)P= 12