Ceng232 Decoder Multiplexer Adder

Decoders, Multiplexers and Programmable Logic

Decoders ,[object Object],[object Object],[object Object],[object Object],[object Object]

What is a decoder ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

What a decoder does ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

How can you build a 2-to-4 decoder? ,[object Object],[object Object],Q0 = S1’ S0’ Q1 = S1’ S0 Q2 = S1 S0’ Q3 = S1 S0

Enable inputs ,[object Object],[object Object],[object Object],[object Object],[object Object]

An aside: abbreviated truth tables ,[object Object],[object Object]

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Blocks and abstraction Q0 = S1’ S0’ Q1 = S1’ S0 Q2 = S1 S0’ Q3 = S1 S0

A 3-to-8 decoder ,[object Object],[object Object],[object Object],[object Object],[object Object],Q0 = S2’ S1’ S0’ Q1 = S2’ S1’ S0 Q2 = S2’ S1 S0’ Q3 = S2’ S1 S0 Q4 = S2 S1’ S0’ Q5 = S2 S1’ S0 Q6 = S2 S1 S0’ Q7 = S2 S1 S0

So what good is a decoder? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Q0 = S1’ S0’ Q1 = S1’ S0 Q2 = S1 S0’ Q3 = S1 S0

Design example: addition ,[object Object],[object Object],[object Object],1 + 1 + 1 = 11 0 + 1 + 1 = 10 C(X,Y,Z) =  m(3,5,6,7)‏ S(X,Y,Z) =  m(1,2,4,7)‏

[object Object],Decoder-based adder C(X,Y,Z) =  m(3,5,6,7)‏ S(X,Y,Z) =  m(1,2,4,7)‏

Using just one decoder ,[object Object],C(X,Y,Z) =  m(3,5,6,7)‏ S(X,Y,Z) =  m(1,2,4,7)‏

Building a 3-to-8 decoder ,[object Object],[object Object],[object Object],[object Object],[object Object],Q0 = S2’ S1’ S0’ = m 0 Q1 = S2’ S1’ S0 = m 1 Q2 = S2’ S1 S0’ = m 2 Q3 = S2’ S1 S0 = m 3 Q4 = S2 S1’ S0’ = m 4 Q5 = S2 S1’ S0 = m 5 Q6 = S2 S1 S0’ = m 6 Q7 = S2 S1 S0 = m 7

Decoder expansion ,[object Object]

Modularity ,[object Object],[object Object],[object Object]

A variation of the standard decoder ,[object Object],[object Object]

Separated at birth? ,[object Object],[object Object],[object Object],Q3 = S1 S0 Q2 = S1 S0’ Q1 = S1’ S0 Q0 = S1’ S0’ Q3’ = (S1 S0)’ = S1’ + S0’ Q2’ = (S1 S0’)’ = S1’ + S0 Q1’ = (S1’ S0)’ = S1 + S0’ Q0’ = (S1’ S0’)’ = S1 + S0

Product of maxterms form ,[object Object],[object Object],[object Object],[object Object],f = M 4 M 5 M 7 =  M(4,5,7)‏ = (x’ + y + z)(x’ + y + z’)(x’ + y’ + z’)‏ f’ = M 0 M 1 M 2 M 3 M 6 =  M(0,1,2,3,6)‏ = (x + y + z)(x + y + z’)(x + y’ + z)‏ (x + y’ + z’)(x’ + y’ + z)‏ f’ contains all the maxterms not in f.

Active-low decoder example ,[object Object],[object Object],[object Object],[object Object]

Converting between standard forms ,[object Object],[object Object],[object Object],f =  m(0,1,2,3,6)‏ f’ =  m(4,5,7) -- f’ contains all the minterms not in f = m 4 + m 5 + m 7 (f’)’ = (m 4 + m 5 + m 7 )’ -- complementing both sides f = m 4 ’ m 5 ’ m 7 ’ -- DeMorgan’s law = M 4 M 5 M 7 -- from the previous page =  M(4,5,7)‏ f =  m(0,1,2,3,6)‏ =  M(4,5,7)‏

Summary ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Multiplexers/demultiplexers PLD components Acknowledgment: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.

In the good old times ,[object Object],[object Object]

Multiplexers ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Q = S’ D0 + S D1

More truth table abbreviations ,[object Object],[object Object],[object Object],[object Object],[object Object],Q = S’ D0 + S D1

A 4-to-1 multiplexer ,[object Object],Q = S1’ S0’ D0 + S1’ S0 D1 + S1 S0’ D2 + S1 S0 D3

Implementing functions with multiplexers ,[object Object],[object Object],[object Object],[object Object],[object Object]

A more efficient way ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Example: multiplexer-based adder ,[object Object],[object Object],[object Object],With S1=X and S0=Y, then Q=X’Y’D0 + X’YD1 + XY’D2 + XYD3 Equation for the multiplexer

Multiplexer-based carry ,[object Object],C = X’ Y’ D0 + X’ Y D1 + X Y’ D2 + X Y D3 = X’ Y’ 0 + X’ Y Z + X Y’ Z + X Y 1 = X’ Y Z + X Y’ Z + XY =  m(3,5,6,7)‏ When XY=00, C=0 When XY=01, C=Z When XY=10, C=Z When XY=11, C=1

Multiplexer-based sum ,[object Object],S = X’ Y’ D0 + X’ Y D1 + X Y’ D2 + X Y D3 = X’ Y’ Z + X’ Y Z’ + X Y’ Z’ + X Y Z =  m(1,2,4,7)‏ When XY=00, S=Z When XY=01, S=Z’ When XY=10, S=Z’ When XY=11, S=Z

Summary ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

The following slides are adapted from David Culler’s slides used at Electrical Engineering and Computer Sciences, University of California, Berkeley

Binary Addition: Half Adder Ai 0 0 1 1 Bi 0 1 0 1 Sum 0 1 1 0 Carry 0 0 0 1 Ai Bi 0 1 0 1 0 1 1 0 Sum = Ai Bi + Ai Bi = Ai + Bi Ai Bi 0 1 0 1 0 0 1 0 Carry = Ai Bi Half-adder Schematic

Full-Adder S = CI xor A xor B CO = B CI + A CI + A B = CI (A + B) + A B 0 0 1 1 + 0 0 1 0 0 1 0 1 1 A B S Cin Co

Full Adder from Half Adders A B + CI (A xor B) = A B + B CI + A CI Half Adder A B Half Adder A + B CI A + B + CI S S CO CO CI (A + B)‏ A B S CO

Delay in the Ripple Carry Adder Critical delay: the propagation of carry from low to high order stages late arriving signal two gate delays to compute CO 4 stage adder final sum and carry

Ripple Carry Timing Critical delay: the propagation of carry from low to high order stages 1111 + 0001 worst case addition T0: Inputs to the adder are valid T2: Stage 0 carry out (C1)‏ T4: Stage 1 carry out (C2)‏ T6: Stage 2 carry out (C3)‏ T8: Stage 3 carry out (C4)‏ 2 delays to compute sum but last carry not ready until 6 delays later

What really happens with the carries ,[object Object],[object Object],[object Object],[object Object],[object Object],Carry action kill Propagate propagate generate Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here All generates and propagates in parallel at first stage. No ripple . Ai Bi Gi Ai Bi Pi

Carry Look Ahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here Si = Ai xor Bi xor Ci = Pi xor Ci Ci+1 = Ai Bi + Ai Ci + Bi Ci = Ai Bi + Ci (Ai + Bi)‏ = Ai Bi + Ci (Ai xor Bi)‏ = Gi + Ci Pi Sum and Carry can be reexpressed in terms of generate/propagate: Gi Ci Pi Ci Pi Si Ci+1

All Carries in Parallel Reexpress the carry logic for each of the bits: C1 = G0 + P0 C0 C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0 Each of the carry equations can be implemented in a two-level logic network Variables are the adder inputs and carry in to stage 0!

Ceng232 Decoder Multiplexer Adder

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Viewers also liked

Viewers also liked (18)

Similar to Ceng232 Decoder Multiplexer Adder

Similar to Ceng232 Decoder Multiplexer Adder (20)

Recently uploaded

Recently uploaded (20)

Ceng232 Decoder Multiplexer Adder