Signal and power integrity challenges in VLSI circuits and strategies for their mitigation

Signal and power integrity challenges in
VLSI circuits and strategies for their
mitigation
Independent Study Report (EES837)
Under the guidance of:
Dr. Kaushik Saha
By
Pushpak Dagade
Department of Electrical Engineering
Indian Institute of Technology, Delhi

Contents
List of Figures v
List of Tables vii
1 Introduction 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization of this Book . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Interconnect: Modeling and Impacts 5
2.1 Interconnect Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.2.1 Resistance . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2.2 Capacitance . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2.3 Inductance . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Interconnect Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Crosstalk: Effects and Mitigation Techniques 15
3.1 Effects of Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1 Crosstalk delay . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1.1 A switches and B does not . . . . . . . . . . . . . . . 16
3.1.1.2 A and B switch in same direction . . . . . . . . . . . 16
3.1.1.3 A and B switch in opposite directions . . . . . . . . 16
3.1.2 Crosstalk noise . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2.1 The victim is floating . . . . . . . . . . . . . . . . . 18
3.1.2.2 The victim is being driven . . . . . . . . . . . . . . . 18
3.2 Crosstalk Mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 Intelligent Engineering . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1.1 Increase spacing to adjacent interconnects . . . . . . 19
i

3.2.1.2 Different switching times for neighbouring interconnects 20
3.2.2 Shielding interconnects . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2.1 Passive Shields . . . . . . . . . . . . . . . . . . . . . 20
3.2.2.2 Active Shields . . . . . . . . . . . . . . . . . . . . . . 21
3.2.3 Crosstalk cancellation techniques . . . . . . . . . . . . . . . . 21
3.2.3.1 Staggered repeaters . . . . . . . . . . . . . . . . . . . 21
3.2.3.2 Charge compensation . . . . . . . . . . . . . . . . . 23
3.2.3.3 Twisted differential signalling . . . . . . . . . . . . . 23
4 Supply Bounce: Causes, Effects and Mitigation Techniques 25
4.1 L di/dt Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.1 Understanding L di/dt Noise . . . . . . . . . . . . . . . . . . . 26
4.1.2 Causes for L di/dt Noise . . . . . . . . . . . . . . . . . . . . . 28
4.1.2.1 Number of switching simultaneously outputs (SSO) . 28
4.1.2.2 Output Load . . . . . . . . . . . . . . . . . . . . . . 29
4.1.2.3 Location of output pins . . . . . . . . . . . . . . . . 31
4.1.2.4 Power supply voltage (VDD) . . . . . . . . . . . . . 31
4.2 Effects of L di/dt noise . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.1 Noise Margin Reduction . . . . . . . . . . . . . . . . . . . . . 32
4.2.2 Propagation Delay Degradation . . . . . . . . . . . . . . . . . 33
4.2.3 Other issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3 Mitigation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.1 Intelligent Engineering . . . . . . . . . . . . . . . . . . . . . . 34
4.3.1.1 Staggered switching of SSO buffers . . . . . . . . . . 34
4.3.1.2 Increase number of supply pins . . . . . . . . . . . . 35
4.3.1.3 Output pin positioning . . . . . . . . . . . . . . . . . 35
4.3.1.4 Separate supply pins for Analog and Digital circuits 36
4.3.1.5 Slew rate control . . . . . . . . . . . . . . . . . . . . 36
4.3.2 Guard Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.2.1 Passive guard rings . . . . . . . . . . . . . . . . . . . 36
4.3.2.2 Active guard rings . . . . . . . . . . . . . . . . . . . 36
4.3.3 On chip decoupling or bypass capacitors (decap) . . . . . . . . 36
5 Electromagnetic emission and interference in VLSI circuits 39
5.1 EMC subcomponents . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.1 Conducted Emission . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.1.1 Through ground and power supply lines . . . . . . . 41
5.3.1.2 Through I/O . . . . . . . . . . . . . . . . . . . . . . 41
5.3.1.3 Radiated emissions from current loops . . . . . . . . 41
5.3.2 Radiated Emission . . . . . . . . . . . . . . . . . . . . . . . . 41
ii

5.3.2.1 Common mode radiation . . . . . . . . . . . . . . . . 41
5.3.2.2 Diﬀerential mode radiation . . . . . . . . . . . . . . 42
5.4 Factors aﬀecting EMC . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.4.0.3 Supply voltage . . . . . . . . . . . . . . . . . . . . . 42
5.4.0.4 Frequency . . . . . . . . . . . . . . . . . . . . . . . . 42
5.4.0.5 Grounding . . . . . . . . . . . . . . . . . . . . . . . 42
5.5 EMC reduction techniques . . . . . . . . . . . . . . . . . . . . . . . . 42
5.5.0.6 Device level noise reduction . . . . . . . . . . . . . . 42
5.5.0.7 Routing noise reduction . . . . . . . . . . . . . . . . 43
References 45
iii

List of Figures
1.1.1 Interconnect Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1.1 Interconnect Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 SEM image of wire cross-sections in Intel’s 45nm process [2] . . . . . 6
2.1.3 Lumped RC Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.4 Distributed RC Model . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.5 Transmission Line Model . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.6 Effect of fringing fields on capacitance . . . . . . . . . . . . . . . . . 9
2.1.7 Multilayer capacitance model of an interconnect. The shaded inter-
connect in the centre is the interconnect of concern for which the total
capacitance is being calculated. . . . . . . . . . . . . . . . . . . . . . 10
2.1.8 Effect of fringing fields on capacitance . . . . . . . . . . . . . . . . . 11
2.2.1 Crosstalk noise on interconnect B (victim) due to interconnect A (ag-
gressor) due to coupling capacitor C . . . . . . . . . . . . . . . . . . . 12
2.2.2 Graphical illustration of 1st
, 2nd
and 3rd
order crosstalk . . . . . . . . 12
3.0.1 Cross sectional view of 2 interconnects A and B with the relevant
capacitances shown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1 A typical scenario where interconnect A switches but B does not . . 16
3.1.2 A best case scenario where both interconnects A and B switch in the
same direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.3 A worst case scenario where interconnects A and B switch in the
opposite direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.4 Propagation delay for the 3 cases summarized in Table 3.1. Delay noise
is the difference between delays for the best and worst case scenarios. 17
3.1.5 Coupling to floating victim . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.6 Coupling to driven victim . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.7 Waveforms of coupling noise . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 Different passive shielding topologies with shields on one or both sides 20
3.2.1 Interleaving bit lines of buses A and B to avoid crosstalk delay effects 20
3.2.3 Active shielding topology. . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.4 Staggered repeaters crosstalk control technique . . . . . . . . . . . . . 22
3.2.5 Charge compensation crosstalk control technique . . . . . . . . . . . 22
v

3.2.6 Twisted Differential Signalling crosstalk control technique. a and a are
aggressor and its compliment. v and v are victim and its compliment
(which is also a victim.) . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.0.1 A cutaway view of dual-in-line package showing the chip-to-package
connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.0.2 Chip package interface parasitics . . . . . . . . . . . . . . . . . . . . 26
4.1.1 Model to understand ground bounce . . . . . . . . . . . . . . . . . . 27
4.1.2 V vs. time for a step input to model in Figure 4.1.1 . . . . . . . . . . 27
4.1.3 I vs. time t for a step input to model in Figure 4.1.1 . . . . . . . . . 27
4.1.4 VGB vs. time t for a step input to model in Figure 4.1.1 . . . . . . . . 27
4.1.5 Ground and VDD bounce output waveforms in Figure 4.1.1 . . . . . . 28
4.1.6 Schematic of 16 output buffers switching simultaneously . . . . . . . 29
4.1.7 Ground bounce waveforms for varying number of outputs switching
simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.8 Ground bounce amplitude vs. capacitive loading (on all outputs) . . . 30
4.1.9 Ground bounce amplitude vs. capacitive loading (only on active outputs) 30
4.1.10Ground bounce amplitude vs. capacitive loading (only on quiet outputs) 30
4.1.11Ground bounce waveform for pin farthest to the device ground (worst
case output pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.12Ground bounce waveform for pin closest to the device ground (best
case output pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.13Ground bounce amplitude vs. VDD for varying load capacitances . . . 32
4.2.1 Noise margin for an inverter with and without ground and power
bounce issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.2 Degradation of propagation delay due to supply bounce . . . . . . . . 34
4.2.3 Layout and schematic of buffers with multiple fingers . . . . . . . . . 34
4.3.1 Ground bounce with and without staggering of SSO . . . . . . . . . . 35
4.3.2 Schematic of chip package interface with multiple ground supply pins 35
4.3.3 Simultaneous switching noise (SSN) vs. number of drivers for varying
number of supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3.4 Passive guard ring configuration . . . . . . . . . . . . . . . . . . . . . 36
4.3.5 Active guard ring configuration . . . . . . . . . . . . . . . . . . . . . 37
4.3.6 On chip decoupling capacitor . . . . . . . . . . . . . . . . . . . . . . 37
5.1.1 EMC: Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.2 EMC: Radiated Susceptibility . . . . . . . . . . . . . . . . . . . . . . 40
5.1.3 EMC: Conducted Emissions . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.4 EMC: Conducted Susceptibility . . . . . . . . . . . . . . . . . . . . . 40
5.2.1 Schematic of radiated electric field from an antenna . . . . . . . . . . 41
5.4.1 Grounding Topologies depending on frequency . . . . . . . . . . . . . 43
vi

List of Tables
1.1 ITRS 2007 Predictions [1] . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Eﬀect of scaling on interconnect parameters . . . . . . . . . . . . . . 2
2.1 Intel 45nm metal stack . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Bulk resistivity of some pure metals (at 22 °C) . . . . . . . . . . . . . 8
3.1 Eﬀective capacitances for various switching cases . . . . . . . . . . . 17
vii

Chapter 1
Introduction
1.1 Introduction
As transistors become smaller in size, they switch faster, dissipate lesser power and
are cheaper to manufacture. The feature size of transistors has been reducing ap-
proximately by 30% every 2-3 years. This has been the trend since 1995 and is still
ongoing. An International Technology Roadmap for Semiconductors is prepared and
maintained by the Semiconductor Industry Association for predicting future scaling
[1]. The ITRS 2007 predictions have been shown in Table 1.1
Figure 1.1.1: Interconnect Geometry
Along with transistors, interconnects
are also scaled accordingly. During the
LSI & beginning of VLSI phase, transis-
tors were much slower as compared to
interconnect delays. Interconnects were
wide and thick and thus had negligible
resistance. They could be simply mod-
eled as ideal equipotential nodes. How-
ever, in modern VLSI, the transistors
switch faster and the interconnects are becoming slower, to the point that in many
cases, the interconnect RC delay is more than the gate delay.
Year 2012 2012 2015 2018 2021 Trend
Feature size (nm) 34 24 17 12 8.4 ↓
Lgate (nm) 20 14 10 7 5 ↓
VDD (V) 1.0 0.9 0.8 0.7 0.65 ↓
Transistors/die (in billions) 1.5 3.1 6.2 12.4 24.7 ↑
Wiring levels 12 12 13 14 15 ↑
Table 1.1: ITRS 2007 Predictions [1]
1

1.1. Introduction 2
Parameters Formula Scale factor
Width w 1/S
Spacing s 1/S
Thickness t 1/S
Interlayer oxide height h 1/S
Die size - Dc
Resistance/length (Rw) 1/wt S2
Fringing plate capacitance/length (Cwf ) t/s 1
Parallel plate capacitance/length (Cwp) w/h 1
Total wire capacitance/length (Cw) Cwf + Cwp 1
RC delay/length2
(twu) RwCw S2
Crosstalk noise w/h 1
Parameters (local/semiglobal interconnect) Formula Scale Factor
Length ll 1/S
Unrepeated RC delay l2
l twu 1
Parameters (global interconnect) Formula Scale Factor
Length lg Dc
Unrepeated RC delay l2
gtwu S2
D2
c
Table 1.2: Effect of scaling on interconnect parameters
Schematic of a pair of interconnects is shown in Figure 1.1.1. Assuming that
transistors scale by a dimensionless factor S (> 1), the effect of scaling on various
interconnect parameters are summarized in Table 1.2.
Interconnects can be categorized as local, semiglobal and global. Local intercon-
nects are used to connect individual functional units. They use the bottom most
layers of metals. Semiglobal interconnects connects higher level blocks or modules
and typically use middle layers of metals. Both these interconnects scale with the
feature size (i.e. become smaller). Global interconnects, as the name suggests, run
across the entire chip. They use the top metal levels. Global interconnects do not
scale with the feature size, but infact increase, since the die size is increasing. In
other words, global interconnects scale with the die size (DC).
Most local interconnects are very small. So, their resistances can be ignored.
Their RC delay is also remaining constant. So, scaling is not affecting performance
of local interconnects. Semiglobal interconnects may have larger lengths so repeaters
will be required, as technology scales, to speed them up. This is a minor problem.
Global interconnects are the slowest ones, since their lengths are increasing. Even
with optimal repeaters, the time required for a signal in the global interconnects to

1.2. Organization of this Book 3
cross the chip can be comparable to a few clock cycles. This is a major problem.
Moreover, interconnects are also packed very closer to each other in modern VLSI.
Thus a significant fraction of their total capacitance is to their neighbours. As a
consequence, when one switches, it affects the other through capacitive coupling.
This effect is called as crosstalk and is an important concern. On chip interconnect
inductance is usually assumed as negligible, but is an important concern for closely
packed buses. Wires also account for a significant portion of switching energy on the
chip.
Power signal integrity is also an important concern in modern VLSI due to scaling
down of interconnects. The faster clock speeds and switching of large number of
devices results in a type of noise, called inductive or L di/dt noise, which results in
the chip seeing bouncing in ground and power supply voltages. This phenomenon
can have a serious impact on the performance of a chip if not handled properly.
1.2 Organization of this Book
Since scaling down of interconnects have lots of consequences, Chapter 2 begins with
the modelling of interconnects in order to understand their behaviour. Using the
model it then discusses the impacts interconnects can have in modern VLSI.
Chapter 3 discusses an important consequence of scaling down interconnect spac-
ing, crosstalk. It first examines the impacts of crosstalk and later on discusses various
techniques which can be used to avoid or reduce crosstalk.
Chapter 4 discusses ground and power supply bounce noise in great detail. It
begins with a simplistic model to develop a fundamental understanding for the cause
of this type of noise. It later on discusses the impacts of this type of noise and
techniques that can be used to avoid or reduce it in detail.

1.2. Organization of this Book 4

Chapter 2
Interconnect: Modeling and
Impacts
2.1 Interconnect Modeling
In order to better understand the problems arising due to scaling of interconnects,
as mentioned in section 1.1, and to find effective mitigation techniques for the same,
it is necessary to model the interconnects. This is done in this section.
2.1.1 Geometry
Figure 2.1.1: Interconnect Geometry
The interconnect geometry for a pair of
interconnects is shown again in Figure
2.1.1 for convenience. The interconnects
have w width, l length, t thickness, s
interconnect-spacing and are h distance
away from the conducting layer below.
The material in this region acts as a di-
electric. Aspect ratio is defined as t/w
& pitch is defined as w + s.
Earlier CMOS processes had only a couple of metal layers, but with time it became
more economical to manufacture many metal layers. Aluminium (Al) interconnects
used in older processes were replaced by copper (Cu) around the 180nm - 130 nm
node to reduce resistance. Also, the SiO2 insulator between wires was replaced with
materials having lower dielectric constants (low-k) to reduce capacitance. A 45nm
process typically has 8-10 metal layers. To get an idea of the typical interconnect ge-
ometry parameter values, Table 2.1 shows the various interconnect parameter values
for an Intel 45nm stack shown in Figure 2.1.2 [2].
5

2.1. Interconnect Modeling 6
Figure 2.1.2: SEM image of wire cross-sections in Intel’s 45nm process [2]
Layer t (nm) w (nm) s (nm) pitch (nm) aspect ratio (nm)
M9 7000 17500 13000 30500 0.4
M8 720 400 410 810 1.8
M7 504 280 280 560 1.8
M6 324 180 180 360 1.8
M5 252 140 140 280 1.8
M4 216 120 120 240 1.8
M3 144 80 80 160 1.8
M2 144 80 80 160 1.8
M1 144 80 80 160 1.8
Table 2.1: Intel 45nm metal stack
2.1.2 Model
Interconnects cannot be modelled as ideal wires anymore, since their propagation
delays have now become comparable to the switching speeds of transistors. They
need to modelled using passive components like resistors, capacitors and/or inductors.
They can be represented using various models -
ˆ Lumped RC model (Figure 2.1.3)
ˆ Distributed RC model (Figure 2.1.4)
ˆ Transmission line model (Figure 2.1.5)
Of these, the most commonly used is the lumped RC model since it is mathemat-
ically simple and easy to use for rough calculation. The lumped RC and distributed
RC models model the interconnect using resistors and capacitors. The transmission

Figure 2.1.3: Lumped RC Model
Figure 2.1.4: Distributed RC Model
Figure 2.1.5: Transmission Line Model
line model uses all the 3 passive components - resistors, capacitors and inductors - to
model the interconnects. I have used the lumped RC model throughout this report
to represent interconnects.
The following sections brieﬂy explain how to compute the equivalent resistance,
capacitance and inductance for an interconnect.
2.1.2.1 Resistance
By deﬁnition, the resistance of the single interconnect for the pair of interconnects
shown in Figure 2.1.1 is given as
R =
ρ
t
l
w
(2.1.1)
where, ρ is the resistivity of the material and l, w and t are as shown in Figure
2.1.1. Since the resistivity ρ and thickness t are controlled by the process technology
and thus not in the hands of the designer, the resistance of interconnects are more
commonly represented in terms of sheet resistance R = ρ/t, as

R = R
l
w
(2.1.2)
Table 2.2 shows the resistivity of commonly used metals at 22 ‰.
Metal Resistivity (µΩ.cm)
Silver (Ag) 1.6
Copper (Cu) 1.7
Gold (Au) 2.2
Aluminium (Al) 2.8
Tungsten (W) 5.3
Molybdenum (Mo) 5.3
Titanium (Ti) 43.0
Table 2.2: Bulk resistivity of some pure metals (at 22 °C)
2.1.2.2 Capacitance
An isolated interconnect over a substrate can be modeled as a conductor over ground.
This capacitance has 2 major components -
ˆ A parallel plate capacitance formed between the bottom of the interconnect
and the ground
ˆ A fringing capacitance due to the fringing electric field lines from the edge of
the interconnect to the substrate
These have been shown graphically in Figure 2.1.6
The parallel plate capacitance is defined as
Cpp =
ox
h
wl (2.1.3)
It is not easy to compute the fringing field capacitance and various approximations
for the same have been proposed. A commonly used formula is
Cfringe =
2π ox
log(h/l)
l (2.1.4)
Therefore, we can write total capacitance for an interconnect as -
Cinterconnect = Cpp + Cfringe (2.1.5)

Figure 2.1.6: Effect of fringing fields on capacitance
All this so far has been discussed for an isolated interconnect over substrate. Ca-
pacitance interactions with neighbouring interconnects become important in modern
CMOS processes since the interconnects and metal lines are very closely spaced. A
simplified schematic of a commonly occurring scenario in modern CMOS processes
is shown in Figure 2.1.7
The total capacitance of the interconnect of interest (the one which is shaded) is
sum of capacitances to the top layer, the bottom layer and adjacent interconnects.
Ctotal = Cbot + Ctop + 2Cadj (2.1.6)
Theoretically, interconnects will have capacitances to every other conductor in the
chip, but they would be extremely small and can be ignored, since most electric field
lines terminate at the immediate neighbours. (The effect of switching of neighbours
on Ctotal is discussed later in Chapter 3)
Depending upon feature size, either capacitance may dominate as shown in Figure
2.1.8. Interwire capacitances start to dominate in multilayer interconnect structures
with decreasing feature sizes.
2.1.2.3 Inductance
The inductance of a conductor (shown in Figure 1.1.1) can be defined approximately
as
L = l
µ0
2π
ln(
8h
w
+
w
4h
) (2.1.7)

2.2. Interconnect Impact 10
Figure 2.1.7: Multilayer capacitance model of an interconnect. The shaded intercon-
nect in the centre is the interconnect of concern for which the total capacitance is
being calculated.
Inductance is difficult to extract and model since inductances are highly dependent
on the 3-dimensional interconnect geometry. We usually try to model the circuit in
terms of resistances and capacitances such that the effect of inductances is negligible.
Inductances however cannot be ignored in high speed designs for power and clock
buses.
2.2 Interconnect Impact
Since interconnects are no more ideal equipotential wires in modern VLSI circuits,
their presence affects the circuits in various aspects. These have been discussed briefly
below using the lumped RC model defined in Section 2.1.2.
2.2.1 Delay
Interconnects increase the circuit delay since it adds its own resistance as well as
loads the gate with its own capacitance (as the lumped RC model of Figure 2.1.3
indicates) thus contributing to the overall RC delay. This delay is more pronounced
for long interconnects which have significant resistance and capacitance which scale
with interconnect length.
Inorder to reduce delay, wider and thicker wires can be used (for the upper level
interconnects, which are most affected by interconnect delay) made up of low resis-
tivity materials like copper to help reduce the interconnect resistance. Using lower
dielectric constant materials will help reduce interconnect capacitance and thus the
delay. These are however not always effective, since there is a limit to the extent at
which these parameters can be tweaked. Appropriate repeaters (buffers made using

Figure 2.1.8: Effect of fringing fields on capacitance
inverters) can be used to break a long interconnect into smaller lengths of intercon-
nect such that the overall delay can become a linear function of interconnect length
(as against to a quadratic function of length which comes if a single long interconnect
is used).
2.2.2 Crosstalk
As shown in Figure 2.1.7, interconnects have capacitances to both ground and neigh-
bouring interconnects. As the interconnect switches, it tries to bring its neighbours
along with it due to the capacitive coupling (Cadj) between the 2 interconnects. This
phenomenon is known as crosstalk. If the neighbouring interconnect is also supposed
to switch at the same time, then, due to crosstalk, the switching delay of both the
interconnects may either increase or decrease. On the other hand, if the neighbour
is not supposed to switch, then crosstalk will cause noise on the neighbour. This is
shown graphically in Figure 2.2.1.
The type of crosstalk mentioned above with reference to Figure 2.1.7 is called as 1st
order crosstalk, since it concerns with the switching of only the immediate neighbour-
ing interconnects. If we consider both the first and second immediate neighbouring
interconnects, this is called as 2nd
order crosstalk and so on. Figure 2.2.2 illustrates
graphically 1st
, 2nd
and 3rd
order crosstalk. Higher order crosstalk effect is usually
very small and can be neglected in most cases.
Crosstalk is discussed in detail in Chapter 3 along with mitigation techniques for

Figure 2.2.1: Crosstalk noise on interconnect B (victim) due to interconnect A (ag-
gressor) due to coupling capacitor C
Figure 2.2.2: Graphical illustration of 1st
, 2nd
and 3rd
order crosstalk

the same.
2.2.3 Power
Switching power consumption is dependent on the capacitance at the switching node.
Since interconnects add to the gate capacitance, more power is required to switch the
nodes at the same frequency (as compared to the case if the wire is treated as ideal).

Chapter 3
Crosstalk: Effects and Mitigation
Techniques
Figure 3.0.1: Cross sectional view of 2 in-
terconnects A and B with the relevant ca-
pacitances shown
Crosstalk was discussed briefly in Sec-
tion 2.2.2 where a scenario involving
multilayer capacitances to an intercon-
nect was shown in Figure 2.1.7. It was
also discussed that crosstalk may cause
delay effects or noise effects or both.
These effects are discussed in detail in
the next section (Section 3.1).
In this chapter, only 1st order
crosstalk is considered. Cross sectional
view of a simplified scenario involving
2 neighbouring interconnects A and B
coupled capacitively is shown in Figure 3.0.1. This figure will be used frequently for
discussion in the next section.
3.1 Effects of Crosstalk
3.1.1 Crosstalk delay
The relative directions of switching of interconnects A and B affects the amount of
charge that must be delivered to the coupling capacitor Cadj and thus the delay. The
more the charge required, the more is the delay involved. The charge delivered is
given by
Qrequired = Cadj∆V (3.1.1)
where ∆V is the difference in voltages of A and B. We also define the Miller Coupling
Factor (MCF) which is the ratio of effective adjacent capacitance to Cadj. Deviation of
15

3.1. Effects of Crosstalk 16
this factor from 1 helps in getting an idea of how much crosstalk affects the switching
delay of interconnects.
Three distinct cases are possible depending upon the relative directions of switch-
ing of interconnects A and B for which ∆V is different [9]. These have been discussed
below.
3.1.1.1 A switches and B does not
Figure 3.1.1: A typical scenario where interconnect A switches but B does not
This is a typical case delay scenario as shown in Figure 3.1.1. In this case,
∆V = VDD and accordingly Equation 3.1.1 becomes Q = Cadj∆V . Thus, the to-
tal capacitance seen by A is Cgnd + Cadj. The MCF in this case is 1.
3.1.1.2 A and B switch in same direction
Figure 3.1.2: A best case scenario where both interconnects A and B switch in the
same direction
This is a best case delay scenario as shown in Figure 3.1.2. In this case, ∆V = 0
and accordingly Equation 3.1.1 becomes Q = 0. Thus, the total capacitance seen by
A is simply Cgnd which is the least possible capacitance. The MCF in this case is 0
(minimum possible).
3.1.1.3 A and B switch in opposite directions
This is a worst case delay scenario as shown in Figure 3.1.3. In this case, ∆V = 2VDD
and accordingly Equation 3.1.1 becomes Q = 2CadjVDD. Thus, the total capacitance

Figure 3.1.3: A worst case scenario where interconnects A and B switch in the
opposite direction
Switching Direction of B Qreq Ceff (A) MCF Relative Delay
Not switching (Typical case) CadjVDD Cgnd + Cadj 1 1
Same as A (Best case) 0 Cgnd 0 ↓
Opposite to A (Worst case) 2CadjVDD Cgnd + 2Cadj 2 ↑
Table 3.1: Effective capacitances for various switching cases
seen by A is Cgnd + 2Cadj. The MCF in this case is 2 (maximum).
The above discussion has been summarized in Table 3.1 and is shown graphically
in Figure 3.1.4.
Figure 3.1.4: Propagation delay for the 3 cases summarized in Table 3.1. Delay noise
is the difference between delays for the best and worst case scenarios.
3.1.2 Crosstalk noise
In the typical case we discussed in Section 3.1.1.1, when interconnect A switches and
interconnect B remains constant, noise is induced on B as it tries to switch partially.
This si known as interconnect noise. In this case, A is called as the aggressor or
perpetrator and B is called as the victim of crosstalk noise. 2 distinct cases are
possible in this case -

3.1.2.1 The victim is floating
Figure 3.1.5: Coupling to floating victim
The victim can be modelled as shown in
Figure 3.1.5. The victim noise in this
case can be obtained easily since it is just
a capacitive voltage divider circuit. The
victim noise is given by
∆Vvictim =
Cadj
Cgnd−v + Cadj
∆Vaggressor
(3.1.2)
where ∆Vaggressor is the change in volt-
age of the aggressor due to switching. It
is usually equal to VDD. Note that since
the victim is floating, the noise will re-
main indefinitely.
3.1.2.2 The victim is being driven
Figure 3.1.6: Coupling to driven victim
The victim in this case can be modeled as
shown in Figure 3.1.6 where the resistors
represent the drivers. Since the victim is
being driven, its driver will provide the
necessary current to oppose and reduce
the victim noise. So, the noise won’t re-
main indefinitely in this case. It would
rise to a peak and then go down to 0
again. The peak noise in this case can
be given as [4]
∆Vvictim =
Cadj
Cgnd−v + Cadj
1
1 + k
∆Vaggressor (3.1.3)
where
k =
τaggressor
τvictim
=
Raggressor(Cgnd−a + Cadj)
Rvictim(Cgnd−v + Cadj)
(3.1.4)
From Equation 3.1.3 it is clear that the faster the victim driver (ie smaller Rvictim),
smaller is the crosstalk noise induced on the victim, which is expected. Equation 3.1.3
reduces to Equation 3.1.2 when the victim is floating ie when Rvictim → ∞, which is
also as expected.
Figure 3.1.7 illustrates all the above discussed cases graphically (for Cadj =
Cgnd−a = Cgnd−v).
Equations 3.1.2 and 3.1.3 indicate that the effect of crosstalk depends on the
ratio of Cadj to Ctotal. Since the load capacitance is included in the total capacitance,

3.2. Crosstalk Mitigation 19
Figure 3.1.7: Waveforms of coupling noise
crosstalk is unimportant for short interconnects (since they have smaller capacitances)
with large loads. The load capacitance dominates in this case. Accordingly, crosstalk
is very important for long interconnects.
3.2 Crosstalk Mitigation
In modern VLSI, as interconnects scale down, coupling capacitors can account for
a significant percent of the total capacitance and can thus (as per Equations 3.1.2
and 3.1.3) create large amounts of noise and data dependent delay variations. It is
therefore necessary to adopt crosstalk mitigation techniques. Some of the commonly
used effective techniques have been discussed below.
3.2.1 Intelligent Engineering
These are the simplest techniques that require no additional circuitry. They simply
exploit the existing scenario cleverly to avoid or reduce crosstalk.
3.2.1.1 Increase spacing to adjacent interconnects
This is the easiest approach to fix a minor crosstalk. Increasing the distance between
interconnects decreases coupling capacitance (Equation 2.1.4) and thus decreases
crosstalk noise (Equation 3.1.3). This method, however, cannot be used for fixing

Figure 3.2.2: Different passive shielding topologies with shields on one or both sides
severe crosstalk issues since in that case the spacing may have to be increased signif-
icantly, which is not acceptable in modern VLSI as area is an important concern. In
such cases we need to resort to other methods.
3.2.1.2 Different switching times for neighbouring interconnects
Figure 3.2.1: Interleaving bit lines
of buses A and B to avoid
crosstalk delay effects
If we have prior knowledge about the timings of
signals in 2 interconnects, they may be arranged
in such a manner so as to guarantee different
switching times for neighbouring interconnects.
As an example, consider 2 buses A and B such
that bus A switches only on rising edge of clock
and bus B switches on falling edges only. If we
interleave the individual bit lines of the 2 buses,
as shown in Figure 3.2.1, we can guarantee that
for every interconnect, while it switches, its 2
immediate neighbours remain constant. Thus,
this can avoid the delay impact of crosstalk (Sec-
tion 3.1.1). However, we must ensure that the
crosstalk noise is within the acceptable noise mar-
gins.
3.2.2 Shielding interconnects
Another scheme of techniques to avoid crosstalk is to shield interconnects on one or
both sides so as to avoid direct coupling with the immediate neighbouring intercon-
nects and thus prevent crosstalk noise.
3.2.2.1 Passive Shields
In this technique, as shown in Figure 3.2.2 [9], power and ground supplies are used
as shields on one or both sides. Critical signals like clock can be shielded even on top

Figure 3.2.3: Active shielding topology.
and bottom so that the switching activity of the neighbours do not affect the delay
of the clock wire and introduce clock jitter.
3.2.2.2 Active Shields
In this technique, as shown in Figure 3.2.3 [6], every interconnect is divided into 3
interconnects, which are in parallel. The central interconnect is made wide. The
two interconnects on the either side of the central one are floating and have smaller
widths. They themselves act as shields for the central interconnect.
3.2.3 Crosstalk cancellation techniques
These techniques try to create equal amounts of positive and negative impact of
crosstalk on the victim. These impacts cancel each other and effectively no net
crosstalk impact is produced on the victim. These techniques may require additional
circuitry and may thus result in additional power dissipation and area consumption.
3.2.3.1 Staggered repeaters
Figure 3.2.4 shows two interconnects with staggered repeaters (inverters) [3]. Due to
the staggered arrangement of inverters, each segment of the victim interconnect sees
one half of a rising aggressor segment and one half of a falling aggressor segment,
as indicated in Figure 3.2.4. Both these aggressor half-segments almost cancel each
other’s noise on the victim. This is a very effective technique for crosstalk noise
cancellation. Note that this technique does not require extra circuitry, since inverters
(buffers) are usually used to break up a long interconnect into smaller segments for
reducing the interconnect delay. This technique just proposes a clever arrangement
of these inverters.

Figure 3.2.4: Staggered repeaters crosstalk control technique
Figure 3.2.5: Charge compensation crosstalk control technique
Figure 3.2.6: Twisted Diﬀerential Signalling crosstalk control technique. a and a are
aggressor and its compliment. v and v are victim and its compliment (which is also
a victim.)

3.2.3.2 Charge compensation
This technique is shown schematically in Figure 3.2.5 [3]. An extra circuitry consist-
ing of a transistor and an inverter is needed between the aggressor and the victim
interconnects for this technique. The transistor’s source, drain and body terminals
are tied together and it thus behaves as a capacitor (with a capacitance of Cgs +Cgd).
When the aggressor tries to rise, it tries to pull the victim upwards along with it. At
the same time the extra added inverter tries to fall and tries to pull the victim down-
wards. By appropriately choosing the compensation transistor, most of the noise
induced on the victim can be cancelled. This is also a very effective technique with
the only disadvantage being the extra area and power required for the circuitry.
3.2.3.3 Twisted differential signalling
This technique is illustrated in Figure 3.2.6 [3]. In this technique the signal intercon-
nects are routed in differential (complimentary) pairs and in a twisted fashion. As a
result, the victim and its compliment each are affected equally by the aggressor and
its compliment, resulting in no net noise on either of them. This technique is used
circuits such as memory, where signals naturally occur in differential (complimen-
tary) fashion. If used otherwise, it would prove to be costly in terms of the wiring
resources.

Chapter 4
Supply Bounce: Causes, Effects
and Mitigation Techniques
Figure 4.0.1: A cutaway view of dual-in-
line package showing the chip-to-package
connections
Figure 4.0.1 shows a cutaway view of a
dual-in line package showing the chip-to-
package connections. The chip (die) is
connected to the package through bond
wires bonded to metal pads on the chip
pad frame. These bond wires connect to
a metal lead frame in the package which
provides I/O connections to the chip.
One of the important things we ex-
pect from an ideal chip package is to pro-
vide connections between chip and board
with little delay and distortion. How-
ever, practically, this does not happen.
The bond wires and lead frame introduce
parasitics between the chip (die) and the
package. Figure 4.0.2 shows schemati-
cally the parasitics introduced between
the chip and package I/O pins [9]. Notably, the VDD and GND wires have induc-
tance from both the bond wires and lead frame as shown in the figure. The non-zero
resistance also is important, especially for chips drawing large amounts of currents.
These parasitics cause signal integrity problems, which is a major concern in
modern VLSI.
When large currents with large slew rates flow through the bonding wires and
package pins, the ground and VDD supply voltages seen by the chip are not the actual
ground and VDD supply voltages. They experience fluctuations due to the presence
of the chip-to-package interface parasitics shown in Figure 4.0.2. This bouncing is
even more enhanced if multiple drivers switch simultaneously. These fluctuations
25

4.1. L di/dt Noise 26
Figure 4.0.2: Chip package interface parasitics
in ground and VDD supply voltages are called as Ground Bounce and VDD Bounce
respectively. These ﬂuctuations are caused due to two reasons, the IR drop primarily
due to lead frame and bond wire resistances and the L di/dt noise due to lead frame,
bond wire, etc. inductances.
Of these, the L di/di noise is a major component of circuit noise in modern VLSI
and its causes have been discussed in detail in the next section.
4.1 L di/dt Noise
This is also called as Simultaneous Switching Noise since this is most pronounced in
the case of a large number of I/O drivers switching simultaneously.
4.1.1 Understanding L di/dt Noise
Figure 4.1.1 shows a simple model to understand ground bounce [8]. The inverter
represents a driver in the lead frame of the package driving a load CL. The inductances
L1, L2, L3 represent the intrinsic inductances in the ground lead, power lead and
output lead of the package receptively. R1 represents the output impedance of the
driver. Note that ideally we would want inductances L1, L2, L3 to be absent.
The driver is now given a rising step input, so that its output falls gradually.
Figures 4.1.2, 4.1.3 and 4.1.4 show output waveforms for V , I and VGB against time
(symbols are marked in Figure 4.1.1). The output voltage V slew rate is dependent
on CL, L3, L1 and the pull down transistor. For simplicity, the output voltage V
is shown to fall at a constant rate in Figure 4.1.2. As the output voltage V falls,

Figure 4.1.1: Model to understand ground bounce
Figure 4.1.2: V vs. time
for a step input to model
in Figure 4.1.1
Figure 4.1.3: I vs. time t
for a step input to model
in Figure 4.1.1
Figure 4.1.4: VGB vs.
time t for a step input to
model in Figure 4.1.1

the capacitor starts to discharge and generates a current I as shown in Figure 4.1.3.
This discharging current goes to the ground through the inductances L3 and L1. The
voltage waveform across the ground lead inductance VGB is shown in Figure 4.1.4.
Figure 4.1.5: Ground and VDD bounce out-
put waveforms in Figure 4.1.1
Figure 4.1.4 clearly shows that the
internal device ground is not same as
the external system ground at all times
or in other words, the internal device
ground bounces. A very similar analy-
sis can be done to illustrate VDD Bounce
where, instead of a rising step input, a
falling step input would be given. In this
case the power lead inductance L2 would
come into picture instead of the ground
lead inductance L1. The output wave-
forms of V and VGB for ground and VDD
bounce have been summarized in Figure
4.1.5. VDD bounce is simply the inverse
of ground bounce. Henceforth, all the analysis in this chapter would be done for
ground bounce which would be equally applicable for VDD bounce.
All the analysis done in this section were for ideal conditions. Practically, there
would be 2nd
and higher order effects as well due to which we would not get such
perfectly linear output waveforms. Infact, ground bounce is generated not just on
high to low transitions of output voltage V , but also on low to high transitions due to
the large gate capacitance of the output transistors on the die, which was neglected
here. Nevertheless, the purpose of this section was just to illustrate the fundamental
origin of ground and VDD bounce.
4.1.2 Causes for L di/dt Noise
There can be several reasons for ground bounce, some of which have been explained
below.
4.1.2.1 Number of switching simultaneously outputs (SSO)
The number of simultaneously switching outputs significantly affects the ground
bounce amplitude [8]. As an example, consider a commonly occurring scenario in-
volving a 16 bit bus as shown in Figure 4.1.6. Suppose that all the 16 drivers switch
at the same time. Let the effective parasitic inductance between the chip and the
system ground be 10nH, which is reasonable, and the rate of change of current dI/dt
be 5mA/nsec which is also reasonable. If we calculate the peak value of ground

Figure 4.1.6: Schematic of 16 out-
put buffers switching simultane-
ously
Figure 4.1.7: Ground bounce
waveforms for varying number of
outputs switching simultaneously
bounce roughly using
VGB = NL
dI
dt
(4.1.1)
we get a peak bounce of 0.8V , which is very high for modern VLSI systems where
the power supply voltage itself is 1.2V or less.
Figure 4.1.7 shows the output waveforms of ground bounce (ie of VGB defined
in Figure 4.1.1) for varying number of outputs switching simultaneously. It is clear,
from Equation 4.1.1 given above and waveforms in Figure 4.1.7, that as the number
of outputs switching simultaneously increases, the amplitude and duration of ground
bounce increases.
4.1.2.2 Output Load
The amplitude of ground bounce is significantly affected by the type and value of
output load [8].
Figure 4.1.8 shows ground bounce amplitude for varying output load capacitances
on all the outputs. It is seen that initially the amplitude peaks, but then falls down
as the capacitance is increased. This fall down is caused by the filtering action of
large capacitors.
Figure 4.1.9 shows ground bounce amplitude for varying the output load capaci-
tances only on the active outputs, keeping the load on the quiet outputs as constant.
It can be seen that as the capacitive load increases the ground bounce increases.

Figure 4.1.8: Ground bounce am-
plitude vs. capacitive loading (on
all outputs)
Figure 4.1.9: Ground bounce am-
plitude vs. capacitive loading
(only on active outputs)
amplitude vs. capacitive loading
(only on quiet outputs)

Figure 4.1.10 shows ground bounce amplitude for varying the output load capaci-
tances only on the quiet outputs, keeping the load on the active outputs as constant.
It can be seen that as the capacitive load increases the ground bounce decreases.
This is due to the filtering effect of the load capacitances.
All these figures also indicate that as the value of VDD increases, the ground
bounce increases. This is explained in Section 4.1.2.4.
4.1.2.3 Location of output pins
Ground bounce amplitude also depends on the location of the output pins with respect
to the device ground [8]. The closer is the pin, the smaller is the ground bounce noise.
Figures 4.1.11 and 4.1.12 depict the waveforms of ground bounce for the pin farthest
and closest from the device ground respectively. As the figure indicates, by choosing
outputs closer to the device ground, the ground bounce noise may be reduced by
nearly 50%.
waveform for pin farthest to the
device ground (worst case output
pin)
waveform for pin closest to the de-
vice ground (best case output pin)
4.1.2.4 Power supply voltage (VDD)
The amplitude of ground bounce is also affected by the power supply voltage VDD.
[8] Reducing the value of VDD reduces both the output voltage swing and the current
delivering ability of the driver. Both the factors contribute positively towards the

4.2. Effects of L di/dt noise 32
Figure 4.1.13: Ground bounce amplitude vs. VDD for varying load capacitances
reduction of ground bounce noise. Thus reducing the power supply voltage VDD
reduces ground bounce noise.
This is illustrated in Figure 4.1.13 for different load capacitances. This phe-
nomenon was also observed previously in Section 4.1.2.2 (Figures 4.1.8, 4.1.10 and
4.1.9).
4.2 Effects of L di/dt noise
Some of the important consequences of L di/dt noise have been discussed briefly in
this section.
4.2.1 Noise Margin Reduction
This is an important consequence of L di/dt noise [6]. The ground and power supply
seen by the chip may be either more and less than the expected values. Since for
noise margin calculation we consider the worst case scenarios (which in this case
is a smaller VDD supply and larger ground supply) the noise margin reduces. The
definition of noise margins can be modified to take into account ground and power
supply bounce as follows -
NML = (VOH − VLDD
) − VIH (4.2.1)

4.2. Effects of L di/dt noise 33
Figure 4.2.1: Noise margin for an inverter with and without ground and power bounce
issue
NMH = VIL − (VOL + VLSS
) (4.2.2)
This has been shown graphically in Figure 4.2.1.
An immediate consequence of reduction in noise margin can be alteration in states
of digital circuits.
4.2.2 Propagation Delay Degradation
When outputs switch, ground bounce occurs and this causes an increase in the prop-
agation delay [8]. This can be explained as follows, with reference to Figure 4.1.1.
When the output switches, voltage appears across L1. Any voltage appearing across
L1 causes a reduction in the voltage across the pull down transistor which in turn
causes the current flowing through it to reduce. Thus the discharging of the capacitor
slows down and hence the propagation delay of the output waveform increases. This
effect is even more pronounced when more number of outputs switch at the same
time. This has been illustrated in Figure 4.2.2.

4.3. Mitigation Techniques 34
Figure 4.2.2: Degradation of
propagation delay due to supply
bounce
Figure 4.2.3: Layout and
schematic of buffers with multiple
fingers
4.2.3 Other issues
There are various other consequences of supply bounce like ground noise undershoots
may cause unexpected leakage currents due to turning on (forward biasing) of the
source-substrate junctions, change in DC operating points of analog circuits, etc.
4.3 Mitigation Techniques
4.3.1 Intelligent Engineering
Some of the commonly used strategies for reducing ground bounce have been dis-
cussed briefly below.
4.3.1.1 Staggered switching of SSO buffers
In Section 4.1.2.1 it was seen that larger the number of SSO, more is the ground and
power supply bounce. To avoid this, we can use buffers with multi finger layout as
shown in Figure 4.2.3 [6]. The smaller individual buffers in the multi finger layout
would switch at slightly different times and would thus reduce the amplitude of the
overall ground bounce. The output waveforms of SSO with and without staggering
are shown in Figure 4.3.1. The drawback of this technique is the reduced operating
speed.

4.3.1.2 Increase number of supply pins
When the number of supply pins are increased, as shown in Figure 4.3.2, the parasitic
inductances become parallel to each other and the eﬀective inductance decreases [6].
Thus the supply bounce noise also decreases. This has been illustrated graphically
in Figure 4.3.3
Figure 4.3.1: Ground bounce with and without staggering of SSO
Figure 4.3.2: Schematic of chip
package interface with multiple
ground supply pins
Figure 4.3.3: Simultaneous
switching noise (SSN) vs. number
of drivers for varying number of
supply pins
4.3.1.3 Output pin positioning
It was seen in Section 4.1.2.3 that the location of pin positions with respect to the
power supply pins also aﬀect the amplitude of the supply bounce. Hence, high drive
outputs & SSO must be placed as close as possible to the ground supply pins. Critical
signals like clock must be kept as far as possible from high drive outputs & SSO and

near ground supply pin to have as small ground bounce noise on these critical signals
as possible.
4.3.1.4 Separate supply pins for Analog and Digital circuits
It is important to keep separate power supply pins and pads for analog and digital
components of a chip. Since switching activity occurs mostly in digital circuits,
keeping separate pins and pads would help avoid coupling of supply bounce noise
generated due to digital components with the analog components of the chip.
4.3.1.5 Slew rate control
If the chip is not meant for high speed operations, the slew rate should be controlled.
Lower slew rate would mean smaller di/dt and thus smaller power supply bounce.
4.3.2 Guard Rings
4.3.2.1 Passive guard rings
Figure 4.3.4: Passive guard ring configuration
Guard rings help in reducing power supply bounce by efficiently absorbing noise
signals [6]. Passive guard rings can be placed close to noise sources in a configuration
shown in Figure 4.3.4 to reduce power supply bounce noise efficiently.
4.3.2.2 Active guard rings
Active guards consist of an amplifier, an active component. A typical active guard
ring configuration is shown in Figure 4.3.5. Active guard rings help reduce power
supply bounce noise more efficiently as compared to passive guard rings, but at the
cost of the extra power and area.
4.3.3 On chip decoupling or bypass capacitors (decap)

Figure 4.3.5: Active guard ring configura-
tion
The use of a decoupling capacitor on chip
is an efficient technique to reduce supply
bounce [6]. A typical scenario schematic
is shown in Figure 4.3.6. Decoupling ca-
pacitors are charged during steady sup-
ply voltages. Whenever there is a local
spike in current, the decap provides the
instantaneous charge requirements of the
chip, reducing the di/dt drawn from the
chip and thus the supply bounce. Decou-
pling capacitors are usually distributed
across the chip to meet the instantaneous
current requirements across the chip.
Figure 4.3.6: On chip decoupling capacitor
Active decap technique can be used to get larger effective capacitances from same
amount of capacitance, with he help of opamps (active elements). This technique
is used when chip area is a critical concern and higher decoupling capacitors are
required.

Chapter 5
Electromagnetic emission and
interference in VLSI circuits
Electromagnetic emissions can cause interference with electronic devices. Interference
is said to occur when the energy received causes the receptor to behave in undesired
manner. The interference can either occur directly (ex:common impedance coupling)
or indirectly (ex: crosstalk, radiation coupling).
It is important to design systems which are electromagnetically compatible with
the environment i.e. it is important to design a system which satisfy the following
criteria [7]
ˆ It does not cause interference with other systems
ˆ It is not susceptible to emissions from other systems
ˆ It does not cause interference with itself
In order to prevent interference, we can either [7]
ˆ Suppress the emission at its source, or
ˆ Try to make the coupling as ineﬃcient as possible, or
ˆ Make the receptor less susceptible to the emissions
5.1 EMC subcomponents
Electromagnetic energy can be divided into four categories as shown below
ˆ Radiated emissions (Figure 5.1.1)
ˆ Radiated susceptibility (Figure 5.1.2)
39

5.2. Antenna 40
ˆ Conducted emissions (Figure 5.1.3)
ˆ Conducted susceptibility (Figure 5.1.4)
Figure 5.1.1: EMC: Radiated Emissions
Figure 5.1.2: EMC: Radiated Susceptibility
Figure 5.1.3: EMC: Conducted Emissions
Figure 5.1.4: EMC: Conducted Susceptibility
5.2 Antenna
The electric ﬁeld strength, E, at a given r from an antenna, shown in Figure 5.2.1,
can be calculated as [5]
E =
k × I × A
r
sinν (5.2.1)

5.3. Emissions 41
where, I is the current through the antenna, A is the area of the antenna, nu is angle
of the point with the plane of the antenna and k is the antenna constant. Antennas
are indirectly created within and outside the chip due to current loops which result
in electromagnetic emissions.
5.3 Emissions
5.3.1 Conducted Emission
Figure 5.2.1: Schematic of radiated electric
field from an antenna
This type of emission can be further cat-
egorized as given below [6]
5.3.1.1 Through ground and power
supply lines
Current spikes at ground and power sup-
ply lines result in conducted emissions.
Although presence of chip decoupling ca-
pacitances reduces current spikes at the
ground and power supply lines, they can-
not fully eliminate the supply bounce.
5.3.1.2 Through I/O
As discussed in Chapter 4, simultaneous switching of I/O ports can result in sig-
nificant current being drawn from the power supply. The chip package interface
parasitics can act as antennas and propagate electromagnetic emissions.
5.3.1.3 Radiated emissions from current loops
Low impedance loops ca sustain large currents which can generate significant elec-
tromagnetic fields.
5.3.2 Radiated Emission
This type of emission can be further categorized as given below [6]
5.3.2.1 Common mode radiation
This type of radiation is also called as monopole antenna radiation. This is caused
due an unintential ground bounce which raises all ground connections of a chip above

5.4. Factors affecting EMC 42
the system ground. Roughly, it can be calculated as
ECM = 4 × 10−7
×
L × f × If
d
(5.3.1)
where, f is frequency of operation, L is cable length, d is distance from cable and If
is the common mode current in the cable at the frequency f. (All are in SI units.)
5.3.2.2 Differential mode radiation
This occurs when an AC current passes in small loops. Roughly, it can be calculated
as
EDM = 265 × 10−16
×
A × f2
× If
d
(5.3.2)
where A, f, If and d are as defined in Section 5.3.2.1.
5.4 Factors affecting EMC
The three main factors affecting EMC are supply voltage, frequency and grounding
[6].
5.4.0.3 Supply voltage
Higher supply voltages result in large voltage swings, which result in larger currents
and thus more emissions. On the other hand, lower supply voltages can affect sus-
ceptibility of the device.
5.4.0.4 Frequency
When the chip operates at higher frequencies, digital components in it create current
spikes due to switching activity which result in emissions.
5.4.0.5 Grounding
The type of grounding also affects EMC. Hence, the topologies shown in Figure 5.4.1
are adopted for based on the range of operating frequency.
5.5 EMC reduction techniques
5.5.0.6 Device level noise reduction
ˆ Various techniques discussed in Section 4.3 can be used to reduce device level
noise and thus EMC. Some of those techniques are using multiple ground and

5.5. EMC reduction techniques 43
Figure 5.4.1: Grounding Topologies depending on frequency
power supply pins,
ˆ Fewer clocks should be off and should turned off when not required (effectively
reducing the f of the chip).
ˆ Minimizing areas of loops within the chip can also help in reduction of EMC
as given by Equation 5.2.1.
5.5.0.7 Routing noise reduction
ˆ Spacing between adjacent active traces should be kept greater than trace width.
This would help in reducing crosstalk noise.
ˆ Clock signal loop areas should be kept as small as possible.
ˆ High speed lines and clock signals should be kept short and direct and loops
should be avoided.
ˆ There should be no floating outputs to avoid necessary switching and thus noise
generation of the floating node.
ˆ Critical signals like clock signals, chip enables should be kept separate from I/O
ports.

5.5. EMC reduction techniques 44

References
[1] Semiconductor Industry Association. International Technology Roadmap for
Semiconductors, 2007.
[2] P. Moon et al. Process and electrical results for the on-die interconnect stack for
intel’s 45nm process generation. Intel Technology Journal, June 2008.
[3] R. Ho, Ken Mai, and M. Horowitz. Managing wire scaling: a circuit perspective.
pages 177–179, 2003.
[4] R. Ho, K.W. Mai, and M.A. Horowitz. The future of wires. Proceedings of the
IEEE, 89(4):490–504, 2001.
[5] Texas Instruments. Electromagnetic emission from logic circuits. Technical report,
1999.
[6] Sanjeev Kumar Jain. Isssues in deep-submicron cmos technology. Technical re-
port, Indian Institute of Technology Delhi.
[7] Clayton Paul. Introduction to Electromagnetic Compatibility. Wiley, 2006.
[8] Fairchild Semiconductor. Understanding and minimizing ground bounce. Tech-
nical report.
[9] Neil Weste and David Harris. CMOS VLSI Design: A Circuits and Systems
Perspective. Addison-Wesley, 2011.
45

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