1. Solar-powered Laptop Charger
Half-bridge DC-DC Converter
in 31352 Power Electronics I
by Emre Gezgin, s093473
Søren Ryeskov, s140593
Dhairav Vakil, s162007
Nathan Wiegman, s161568
Technical University of Denmark
Department of Electrical Engineering
31352 Power Electronics I
December 6, 2016
1
3. Chapter 1
Introduction
In this system design experiment, the team analyses different isolated DC-DC converter topologies, selects a topology
and designs magnetics, filters, and controls for the chosen system. The system must step down a DC voltage input
from a solar panel to a low voltage output, a laptop, with minimal component stress. The PV cell input acts as a DC
source, providing 24-45V depending on current sunlight. The design specifications are seen in table 1.1.
Specification Value
Output Voltage 19V
Output Current 3A
Max Output Ripple 50mV
Input Voltage 24V to 45V
Table 1.1: System Specifications
In the following chapters, methodology for determining the optimal converter topology is examined. Following this,
the magnetic components, filter components, and controller components are determined. Finally, a list of components
including price and manufacturer required to build the power converter to our specific purpose is described.
3
4. Chapter 2
Topology Selection
The team chose four converter topologies to analyse from a pool of galvanically-isolated converters. The topologies
were selected based off their assumed component stresses. The below analysis determines the topology with the lowest
total component stress.
2.1 Forward Converter
2.1.1 Introduction
This section covers the forward converter. It explains how this converter operates and waveforms for each component
are sketched. Furthermore, challenges and advantages of this topology related to the specifications are briefly discussed.
The schematic of the Forward converter can be seen in figure 2.1. All components are assumed ideal.
Figure 2.1: Electric Schematic of the Forward Converter
2.1.2 Functionality
When the input sourced is on and the MOSFET is on current will be drawn from the source through the primary
winding L1 and also the magnetizing winding Lm which is in parallel with L1. The magnetizing winding is not
physically wound wires on the transformer core, it is simply a way to model the transformer behaviour. The voltage
across the magnetizing winding is constant and the current will rise in accordance with equation 2.1.
VLm = Lm ·
di
dt
(2.1)
When the MOSFET is then turned off, the current in Lm must be reduced and a voltage of opposite polarity must
be applied to comply with the steady-state inductor volt-second balance, otherwise the core will saturate. Thus the
voltage across any inductor in steady state must be equal to zero.
The average absolute voltage over a period T is defined as:
< |v(t)| >=
1
T
T
0
|v(t)|dt (2.2)
In order to prevent saturation of the core, a physical demagnetizing winding L2 is connected in series with a
diode D1. The orientation of the diode and polarity of L2 is such that current will flow into the positive terminal of
Vg when the MOSFET is OFF. The direction of the current will induce a voltage across L1 and thus Lm, thereby
applying a negative voltage across it, referred to the previous polarity of the voltage. Once again, this discharge of the
magnetizing inductance follow equation 2.1 and thus the inductor volt-second balance is kept once the current reaches
zero. The current must reach zero before the next switching period begins. Therefore, the switching period may be
divided into three stages.
On the secondary side, when the MOSFET is on, D2 will be forward biased and conducting current. D3 will be
reverse biased and blocking. When the MOSFET is turned off and D1 is conducting, the current through L3 will be
zero. This happens because the current through L2 is in the opposite direction of what it was in L1 and thus it will
try to reverse the flow of current in L3, but D2 will then be reverse biased and block the current flow.
Now D3 will be forward biased and conducting current; it is acting as a freewheeling diode, otherwise the current
in Lout would have nowhere to go. In this way, energy will be supplied to the load. This output stage is similar to
that of the buck converter and operation is the same, thus the forward converter is a step down type converter.
4
5. During to first subinterval, the output inductor Lout is being charged and the current will increase. During the
second and third subinterval, Lout is being discharged. The current will be freewheeling through D3 and any ripple
component in the current will go through the filtering capacitor and the DC current component will flow through load.
2.1.3 Duty cycle ratio
The duty cycle ratio may be derived using the inductor volt-second balance on Lout. Which may be found as:
(
n3
n1
Vg − V )D − V (1 − D) = 0 (2.3)
The voltage across the inductor between time 0 and DT (denoted by D) is equal to (n3
n1
Vg − V ) and from DT to
T (denoted by 1-D), the voltage is -V. The equation can be rearranged to obtain the transfer function as a function
of the transformer turns ratio and the duty cycle, as seen in eq. 2.4
Vout
Vg
=
n3
n1
· D, where D ≤
1
1 + n2
n1
(2.4)
The duty cycle is limited and is now investigated. When examining the volt-second balance on the first winding
n1, (D is replaced by D1) one obtains:
VgD1 + (−Vg
n1
n2
) + D3 = 0 (2.5)
The converter undergoes three switching intervals where the third interval has the MOSFET and D1 off, thus the
voltage is zero accross the transformer, thus eq. 2.5 can be rearanged to eq. 2.6
VgD1 = (Vg
n2
n2
) (2.6)
The three sub-intervals, D1, D2 & D3 must equal 1 when added together, however none of them may be negative,
which leads to 2.7
D3 = 1 − D1 − D2 ≥ 0 (2.7)
By substituion, the duty cycle limit can be obtained:
D =
1
1 + n2
n1
(2.8)
Typically, the two primary side windings are designed with an equal number of turns, resulting in:
D ≤ 50% (2.9)
In figures 2.2 to 2.5 the waveforms of the different components and the current flow during the three subintervals
can be seen. For the inductors, scraped areas in the same graph indicates the the two areas are equal. Note that
inductance and capacitances are assumed large enough to have zero ripple, however the current in Lout is still sketched
more realistically.
Vg and Vout are not sketched, since they are constant and thus a sketch would be redundant.
All components are assumed to be ideal, therefore there is no voltage drop across the MOSFET and diodes when
they are conducting.
Current and its direction is indicated with a red arrow forming the current loop.
5
6. Voltage and Current wave forms
Figure 2.2: Voltage (left) and Current (right) wave forms
6
7. Current flow during the three subintervals
Figure 2.3: Current flow during the first subinterval
Figure 2.4: Current flow during the second subinterval
Figure 2.5: Current flow during the third subinterval
2.1.4 Stress factors
To simplify the stress factor calculations, all components are considered ideal and inductances and capacitance are
assumed infinitely large. This means that when a component conducts, the current immediately jumps to a given
value and remains constant as long as it is conducting. The same principle is true for voltages.
Thus the output voltage is constant at 19V, and the output current is also constant at 3A. The input current
will have two different values depending on whether the input voltage is 24V or 45V. This gives rise to two different
scenarios.
The transformer turns ratio is needed to perform these calculations. since the Forward converter acts as a step
down type converter and the input voltage may be as low as 24V while maintaining 19V on the output, the transformer
will have to step up the voltage. This is the way it must be, due to the duty cycle ratio limit as shown in eq. 2.4.
Thereby the transformer turns ratio is selected as follows:
n1 : n2 : n3 (2.10)
1 : 1 : 3 (2.11)
This turns ratio will result in a step up of the voltage, from the primary side to the secondary side, by a factor
of 2. Likewise it will also result in a step down of the current from primary to secondary. A ratio of 1:1 between the
windings on the primary side allows for a duty cycle up to 50% in accordance with 2.4.
7
8. The RMS currents of all the components is derived from the definition,
IRMS =
1
T
·
T
0
i(t)2dt (2.12)
With all components considered ideal, when conducting, the current will be constant. Thus piecewise integrals can
be made in the form of,
IRMS =
1
T
·
D1T
0
i1(t)2dT +
D2T
D1T
i2(t)2dT +
T
D2T
i3(t)2dT (2.13)
Where one or two subintervals may have zero current, as one can see in figure 2.3, 2.4 & 2.5
In table 2.1, the RMS currents of the respective components, as well as their corresponding simplified equations
and minimum & maximum values, can be seen.
Component Simplified equation Minimum Maximum
MOSFET IRMS = Iin ·
√
D1 2.76A 3.77A
D1 IRMS = Iin ·
√
D2 2.76A 3.77A
D2 IRMS = Iout ·
√
D1 1.38A 1.89A
D3 IRMS = Iout0 ·
√
1 − D1 2.33A 2.66A
n1 IRMS = Iin ·
√
D2 2.76A 3.77A
n2 IRMS = Iin ·
√
1 − D1 − D3 2.76A 3.77A
n3 IRMS = Iout ·
√
D1 1.38A 1.89A
Lout IRMS = Iout 3A 3A
Table 2.1: RMS currents
To calculate the stress factors, the following formula is used, where the weight factor is set to 1:
SCSFi =
j Wj
Wi
V 2
max,iI2
RMS,i
P2
; Vmax,i = max(v(t)) (2.14)
WCSFi =
j Wj
Wi
V 2
max,iI2
RMS,i
P2
; Vmax,i =< |v(t)| >T (2.15)
WCSFi =
j Wj
Wi
V 2
peak,iI2
RMS,i
P2
; Vpeak,i = max(v(t)) (2.16)
All of these RMS currents and maximum voltages result in the following stress factors:
SCSF = 73.1 (2.17)
WCSF = 93.9 (2.18)
CCSF = 0 (2.19)
The zero CCSF is a result of components assumed ideal and infinitely large inductance and capacitance. There is
no ripple current through the capacitance and thereby, there is zero CCSF, in accordance with 2.16.
2.1.5 Advantages and disadvantages
The given project specifications requires a power converter with step down capabilities. The forward topology is a
galvanically isolated converter which does exactly that. In direct comparison to the buck converter, the forward con-
verter uses five additional components, three of them winding components and two of the semiconductor components.
The arrangement of the two diodes on the secondary side of the circuit ensures that there is no back e.m.f.; there
is transformation of the output voltage, back to the primary side. Unlike the flyback converter, where the output
voltage is transformed back to the primary side. However, the two windings on the primary side will induce a voltage
on another. They will not conduct current at the same time and thereby one will induce a voltage equal to Vin · N
where N is the turns ratio between the two primary side windings. The MOSFET and the diode on the primary side
must then be able to handle higher voltages than just Vin. In this particular case, both must be able to withstand a
voltage of up to 2·Vin,max = 90V , which will cause higher SCSF. The forward topology uses only one switch, with the
Source-terminal connected to ground. This allows for easier switching than converters with high-side switches, such
as the half-bridge and full-bridge. In comparison to the three other converter topologies outlined in this report, the
forward converter has the fewest diodes and fewest MOSFETS which will result in lower semiconductor power losses.
8
9. 2.1.6 Real semiconductor voltage influence
In a real-world scenario, the semiconductors will cause a voltage drop when conducting. The voltage drop of the
MOSFET will be determined by its on-resistance RDS(on) which can vary greatly. Some may have just a few milliohms
while others may have a few hundred milliohms. The on-resistance varies greatly with the physical size of the device.
Diodes have a forward voltage drop often around 0.7V for conventional diodes, or often around 0.3V for Schottky
diodes.
The effect of voltage drops of the semiconductors in the forward converter, may result in slightly different voltages
being applied to the two primary windings. The first subinterval, where the core is magnetized will have a certain
length and if a smaller voltage is then applied to the second winding, the current will be slightly smaller and the
second subinterval will then be slightly longer than the first. The duration of the switching period will have to be set
accordingly.
In the output stage, the forward voltage drop in the diodes will also result in a slightly smaller voltage being
applied to Lout and thereby a slightly smaller current.
The optimal situation will then be one, where the diodes have a forward voltage as low as possible to both reduce
power losses in the diode and to achieve circuit behaviour slightly closer to the ideal scenario.
9
10. 2.2 Full-Bridge Buck Converter
2.2.1 Introduction
This section will cover the full bridge converter. It explains how this converter operates and waveforms for each
component are sketched. Furthermore challenges and advantages of this topology related to the specifications are
discussed.
The schematic of the full bridge converter can be seen in figure 2.6. All components are assumed ideal. In this diagram,
the MOSFETs in the circuit are shown as switches for ease of display. An ideal MOSFET behaves the same as a
switch in this case.
Figure 2.6: Electric Schematic of the Full-Bridge Buck Converter
2.2.2 Functionality
The ideal full-bridge DC-DC converter operates in two stages. First, a full bridge DC-AC converter chops the DC
voltage into an AC signal. This is passed through a transformer to isolate the output voltage, preventing ground loops
and reducing noise. Then a full bridge rectifier converts the stepped AC voltage back to DC. Finally, an inductor
maintains the output voltage. The inductor-capacitor combination also acts as a low-pass filter to remove switching
noise.
The ideal full-bridge DC-AC converter uses four MOSFETs to create a square AC signal with maximum amplitude
equal to the input voltage. The MOSFETs turn on in pairs–S1/S4 and S2/S3. The switching period is broken into
two sections with time T to ensure that S1/S2 and S3/S4 are not on at the same time to avoid short-circuiting the
source. This allows for a theoretical maximum duty cycle D of 100%. In reality, the maximum duty cycle is lower due
to the switching on/off times. The AC voltage across the transformer is equivalent to the DC input voltage in normal
polarity while S1/S4 are on, and in the opposite polarity while S2/S3 are on. The waveforms of the components on
the primary side can be seen in figures 2.10 to 2.13.
The ideal full-bridge AD-DC converter operates in two stages, similar to the DC-AC converter. It receives the AC
signal from the first stage through the transformer, stepped by the turns ratio, N. It then uses four diodes to convert
the AC signal to a DC signal across the output filter. The waveforms of the components on the secondary side can
be seen in figures 2.14 to 2.18 Note that inductance and capacitances are assumed large enough to have zero ripple,
however the current in Lout is still sketched more realistically.
During a full period, 2T, there are four subintervals. During subinterval one, while S1/S4 are on, D2/D3 are
forward-biased and D1/D4 are reverse-biased, as seen in figure 2.7. Then in subinterval two, all the MOSFETs turn
off, allowing the output inductor to discharge through the output load, and following a current path through all
four diodes, as shown in figure 2.8. In the third subinterval, MOSFETs S2/S3 turn on creating a voltage across
the transformer primary in the opposite polarity from subinterval one. This causes D1/D4 to be forward-biased and
D2/D3 to be reverse-biased, as seen in figure 2.9. Finally, all MOSFETs turn off, causing the same reaction as in
subinterval two.
Figure 2.7: Subinterval 1: S1,4 On
10
11. Figure 2.8: Subinterval 2 and 4: all S Off
Figure 2.9: Subinterval 3: S2,3 On
Figure 2.10: Ci Waveforms
Figure 2.11: S1,4 Waveforms
Figure 2.12: S2,3 Waveforms
11
13. Symbol Min Input Max Input Expression
Turns Ratio N 1 1
Input Voltage Vin 24V 45V
Output Voltage Vout 19V 19V
Output Current Iout 3A 3A
Output Voltage Ripple ∆Vout 50mV 50mV
Duty Cycle D 0.79 0.42
MOSFET Max Voltage max(VSi
) 24V 45V Vin
MOSFET RMS Current RMS(ISi ) 1.89A 1.37A N · Io
D
2
Diode Max Voltage max( VDi ) 24V 45V − NVin
Diode RMS Current RMS(IDi ) 2.01A 1.79A 0.5Iout
√
D + 1
Cin Max Voltage max(VCin
) 24V 45V Vin
Cin RMS Current RMS(VCin
) 1.45A 1.99A I2
in + (NIout)2
√
D
Cout Max Voltage max(VCout
) 19V 19V Vout
Cout RMS Current RMS(ICout ) 0A 0A 0
L Max Voltage max(|VL|) 5V 26V NVin − Vout
L RMS Current RMS(IL) 3A 3A Iout
Table 2.2: Table of Full-Bridge Buck Formulae Note i denotes all MOSFETs and Diodes
Selecting Duty Cycle and Turns Ratio
The transfer function for a full-bridge buck converter is given in equation 2.20.
Vo
Vi
=
n2
n1
∗ D (2.20)
This equation is dependent on both the turns ratio and the duty cycle. As the duty cycle has an upper limit of
100%, it can be used to select an appropriate turns ratio. Given the input and output voltages, as seen in table 1.1,
and assuming n1 = 1, n2 = N and N = turnsratio, solving equation 2.20 for ND yields a range of values for ND as
shown in equation 2.21.
Vo
2 ∗ ViMAX
< ND <
Vo
2 ∗ ViMIN
(2.21)
Then, it is possible to select a turns ratio such that D is always less than 100% given the system specifications.
The resulting values of ND are always less than one, thus the turns ratio is one. The duty cycle is solely dependent
on the input voltage. The results of these calculations can be seen in table 2.2.
2.2.3 Stress Factors
To simplify the stress factor calculations, all components are assumed ideal and very large. The definition of RMS
Current is seen in equation 2.12 and the derived equations for each component are seen in table 2.2. The average
absolute voltage is given in equation 2.2. For simplicity, the component weight factor j Wj
Wi
is set to one.
Semiconductor Stress Factor The individual SCSF is calculated as shown in equation 2.14. The total SCSF for
the Full-Bridge Buck converter is the sum of all individual SCSF, and is calculated as seen in equation 2.22, where
the first fraction is all four MOSFETs and the second fraction is all four diodes.
SCSF = 4
45V 2
1.89A2
57W2
+ 4
(45V )2
2.01A2
57W2
= 18.98 (2.22)
Winding Stress Factor The WCSF is calculated as shown in equation 2.15. The total WCSF for the Full-Bridge
Buck converter is calculated as seen in equation 2.23, where the first fraction is LP , the second is LS, and the third
is Lout. In this ideal case, Lout is large enough such that there is no output current ripple. This makes di/dt through
Lout zero, and thus the voltage across it is also zero.
WCSF =
22.5V 2
3A2
57W2
+
22.5V 2
3A2
57W2
+
0V 2
3A2
57w2
= 2.80 (2.23)
Capacitor Stress Factor The CCSF is calculated as shown in equation 2.16. The total CCSF for the Full-Bridge
Buck converter is calculated as shown in equation 2.24, where the first fraction is Cin and the second fraction is Cout.
CCSF =
45V 2
6.3A2
57W2
+
19V 2
0A2
57W2
= 0.64 (2.24)
13
14. 2.2.4 Advantages and Disadvantages
The full bridge converter can be used as a step down or step up converter. The full bridge converter utilises both flux
directions on the transformer, and thus must balance the flux. This is naturally provided if using a current control.
Flux balance also reduces the winding stress, and allows for use of a physically smaller transformer. The full bridge
converter is the most complex converter analysed, including twelve components. Eight of the twelve components are
active, semiconductor components, which leads to a high stress value. Similarly, since the full bridge converter utilises
a full bridge inverter a high side driver for the MOSFET must be developed. This is a time consuming process that
adds complexity to the design.
14
15. 2.3 Half Bridge Converter Topology
2.3.1 Introduction
This section explains the Half Bridge Converter. The functionality, schematic, waveform, advantages, and disadvan-
tages of this topology are explored. The schematic of the Half Bridge converter can be seen in figure 2.19 below. All
components are assumed ideal.
Figure 2.19: Schematic of the Half Bridge Converter
2.3.2 Functionality
The half-bridge converter is a DC-DC converter that can either step up or step down input voltages. It utilises
two MOSFETs to perform switching operation, two capacitors, and two diodes to limit peak transistor voltage. Both
MOSFETs (Q1 and Q2) must not conduct simultaneously, otherwise shorting of the source will occur. The functionality
of the Half Bridge Converter can be divided into 4 sections. Time 0 To DTs, DTs to 0.5Ts, 0.5Ts to (D + 0.5)Ts, and
(D + 0.5)Ts to Ts.
The main advantages of the Half Bridge are a high switch blocking to Vin and the excitation of the core in both
flux directions. Similar to the Full Bridge, the Half Bridge Converter can operate in the discontinuous conduction
mode at light load and can operate over the entire duty cycle range from 0% to 100% which is very useful. Also, the
Half Bridge Converter features transformer isolation.
The Half Bridge output voltage follows the following formula:
Vout = nDVin (2.25)
As one can see, the output voltage is directly related to the duty cycle, and the number of turns in the transformer
unlike most other topologies.
Time 0 to DTs
When the first MOSFET (Q1) is turned on, the current flows from the input source to the secondary side. Q2
remains off as if it was on, short circuiting would occur. The diodes D1 and D2 remain conducting as well as the
capacitors, as the peak Voltage is clamped to the input Voltage Vg. Diode D4 does not conduct, but D3 does. VT
(the voltage on the primary side of the transformer) is half of what the input voltage Vg is. The output voltage Vs
that flows through resistor R1 and C3 is thus ND0.5Vg due to kirchoff’s voltage law. Ig is also Vg/2LM where Ig is
the source current, Vg is the source voltage, and LM is the magnetising inductance.
The following schematic describes the time when MOSFET Q1 is on.
15
16. Figure 2.20: MOSFET Q1 is on
Time DTs to 0.5Ts and Time DTs to 2Ts
During this time both MOSFETS (Q1 and Q2) are off. This means that the input Voltage Vg does not flow through
the circuit. Because of this, VT and Vs are both 0. The only components that are conducting are Diodes D3 and D4.
Also, the Inductor L1 has charge and has current flowing through it. D1, D2, C1 and C2 continue to conduct.
The following schematic describes the time when MOSFET Q1 and Q2 are both off.
Figure 2.21: MOSFET Q1 and Q2 are off
0.5Ts to (D + 0.5)Ts
When the MOSFET (Q2) is turned on, current flows down the MOSFET and turns on Diode D4.D1,D2,C1 and
C2 continue to conduct, but Q2 remains off; If it was on short circuiting would occur.
The following schematic describes the time when MOSFET Q2 is on.
Figure 2.22: MOSFET Q2 is on
The following are the waveforms of the half-bridge converter. Ideal components are assumed.
16
17. Figure 2.23: Half-Bridge Converter Waveforms
Figure 2.24: Half-Bridge Converter Waveforms
The following is a table of values for Calculating the Stress Factors for the Half Bridge Converter.
17
18. Min Max Expression
Turn Ratio 2 2 2Vo
Vi
Input Voltage 24V 45V
Output Voltage 19V 19V
Output Current 3A 3A
Output Voltage Ripple 50mV 50mV
Duty Cycle 0.422 0.791
MOSFET Voltage 12V 22.5V 0.5Vin
MOSFET RMS Current 3A 3A 2
N Iout
Diode Max Voltage 24V 45V Vin
Diode RMS Current 0A 3A
Capacitor Max Voltage 12V 22.5V 0.5Vin
Capacitor RMS Current 1.95A 2.67A Io
√
D
Inductor Max Voltage 12V 22.5V 0.5Vin
Inductor RMS Current 3A 3A
Table 2.3: Half Bridge Converter Formulae
2.3.3 Duty Cycles
The Transfer function for a Half-Bridge Converter is the following:
Vo
Vi
=
1
2
·
N2
N1
· D (2.26)
Theoretically, the Half-Bridge Converter can work at any duty cycle (0 < D < 1). However, for practical purposes,
the ratio is around 50%. This ensures that the MOSFETs are not on at the same time and short circuiting of the source
does not occur. Based of equation 2.26, one can determine that the turns ratio must be greater than 2Vin/Vin(Min).
Because of this, the equation 2.27 can be determined.
2 · Vo
Vin(Max)
< N · D <
2 · Vo
Vin(Min)
(2.27)
Thus, a good turns ratio based off of the initial conditions could be 2. This thus leaves the duty cycle to range
from 0.422 to 0.791.
2.3.4 Stress Factors
j Wj
Wi
is the general form of how stress factors are calculated for each component.
Table 2.4: Summary of Stress Factors
Value
SCSF 25.24
WCSF 5.61
CCSF 2.22
Semiconductor Stress Factor
For Semiconductor Stress Factor calculation, equation 2.28 was used. This stress calculation includes 2 MOSFETS
and 4 diodes. The SCSF ended up being 25.24.
SCSF =
V 2
maxI2
RMS
P2
(2.28)
Winding Stress Factor
For Winding Stress Factor calculation, equation 2.29 was used and was calculated including 4 different windings
that are present in the system. The WCSF ended up being 5.61.
WCSF =
V 2
maxI2
RMS
P2
(2.29)
Capacitor Stress Factor
For Capacitor Stress Factor calculation, equation 2.30 was used and was based off of the two 3 capacitors in the
system. The CSSF ended up being 2.22
18
19. CCSF =
V 2
peakI2
RMS
P2
(2.30)
2.3.5 Summary
In conclusion, the Half-Bridge Converter is ideal when low power levels are utilised. The Half-Bridge is advantageous
due to its low part use, wide range of duty cycles, and maximum switch blocking. Its disadvantages are, however,
that it cannot be current programmed due to the high amounts of current that flow through the transistor ( doubling
transformer turns doubles currents). For these reasons, the team chose this converter topology to build on in the rest
of the report.
As a step down converter, the Half-Bridge converter is a viable choice as the output voltage follows nD0.5Vd
19
20. 2.4 Pushpull
2.4.1 Introduction
This section will cover the push-pull converter. It will cover how the push-pull converter works and how the waveforms
for each component and an analysis where the advantages and disadvantages of this topology are explained.
The push-pull converter schematic can be seen on figure 2.25. All components are assumed ideal.
Figure 2.25: Electric Schematic of the Push-pull Converter
2.4.2 Functionality
The push-pull converter is a isolated DC-DC converter that can be used as step-down converter. It has 2 MOSFETs
to perform the switching operation and a centre tap transformer on both the primary and the secondary side. 2 diodes
to work as a rectifier and an inductor that together works as a buck converter to stabilise the output voltage.
The MOSFETs work with equal duty cycles but in different switching periods to maintain a voltage balance across
the primary windings of the transformer. Because of the equal duty cycle for the MOSFETs the push-pull converter
can operate with a duty cycle range of 0 ≤ D < 1.
The push-pull converter has 3 stages. First is when MOSFET Q1 is on and conducting.
This will utilize the transformer and will result that D1 is the only diode thats conducting because the direction change
in the magnetic field in the transformer core as seen on figure 2.26.
Second stage is when both Q1 and Q2 is off and not conducting.
This stage is always between either when Q1 is on or when Q2 is on. Nothing will happen on the primary side, but
on the secondary side, both diode D1 and D2 will be on and conduct like a buck converter as seen on figure 2.27.
The 3 and last stage is when the second MOSFET Q2 is on.
This will result in the mirrored situation as in the first stage. The magnetic field is changed and this will result that
only D2 is conduction as seen on figure 2.28. After this stage the converter will return to the second stage and then
start over by switching Q1 again.
20
21. Figure 2.26: Showing current flow in stage of push pull converter where Q1 is conducting
Figure 2.27: Showing current flow in stage of push pull converter where neither Q1 or Q2 is conducting
Figure 2.28: Showing current flow in stage of push pull converter where Q2 is conducting
All the waveforms for the push pull converter can be seen on figure 2.29 to figure 2.33
21
22. Figure 2.29: Voltage (left side) and current (right side) waveforms for Q1 and Q2
Figure 2.30: Voltage (left side) and current (right side) waveforms for D1 and D2
Figure 2.31: Voltage (left side) and current (right side) waveforms for the primay and secondary side of the transformer
Figure 2.32: Voltage (left side) and current (right side) waveforms for inductor L
Figure 2.33: Voltage for transformers primary side (left side) and magnetic current for transformer (right side) wave-
forms
The illustrated waveforms shows either a voltage or a current for the push pull converter for a full period T where
all the stages are included.
22
23. 2.4.3 Duty Cycle and ratio
The transfer function of the push pull converter is equation 2.31 where N equals the turn ratio Nsecond
Nprimary
Vo
Vi
= N · D (2.31)
As seen in the equation, it depends on both the turn ratio, N, of the transformer and the duty cycle, D. Because
the MOSFETs of the push pull converter never overlap in their individual switching period, its possible to have a
duty cycle 0 ≤ D < 1. Because of these 2 values its possible to keep the maximum and minimum duty cycle close by
picking the right turn ratio value. All the calculated maximum and minimum values for the push pull converter are
listed in table 2.5.
Component Equation Min Max
Turn Radio V out = V in · Duty · N 2 2
Duty Cycle V out = V in · Duty · N .40 .21
Mosfet V 2 · V in 48 90
Mosfet RMS 1
N · Iout 1.5 1.5
Diode V V in · N 48 90
Diode RMS sqrt(1 − D) · Iout 2.33 2.66
Transformer P V V in 24 45
Transformer P RMS Iin 1.19 .63
Transformer S V V in · N 48 90
Transformer S RMS Iout 3 3
Inductor V V in · ratio − V out 29 71
Inductor RMS Iout 3 3
Table 2.5: Calculated maximum and minimum values
2.4.4 Stress Factors
To simplify the calculations all components are assumed ideal. The used values are all listed in table 2.5.
Semiconductor Stress Factor To calculate the SCSF the stress of all the MOSFETs and diodes must be summed
up. This is calculated by using equation 2.32 and the result is listed in table 2.6.
SCSF =
902
· 1.52
(3 · 19)2
· 2 +
902
· 2.662
(3 · 19)2
· 2 (2.32)
Winding Stress Factor To calculate the WCSF the loss of all the inductors must be added up as done in equation
2.33 and the result is listed in table 2.6.
WCSF =
24.492
· 1.192
(3 · 19)2
+
33.992
· 32
(3 · 19)2
+
29.982
· 32
(3 · 19)2
(2.33)
Capacitor Stress Factor The CCSF is calculated by adding up the stress all the capacitors in the push pull
converter. The assumption of ideal components result in a CCSF close to zero because the output capacitor is has no
ripple current and therefore its removed from the equation as shown in equation 2.34, but even is the output capacitor
is removed the calculated result is listed in table 2.6.
CCSF =
452
· 1.192
(3 · 19)2
+
192
· 02
(3 · 19)2
(2.34)
SCSF 46.62
WCSF 5.95
CCSF .88
Table 2.6: Push pull stress factor results
2.4.5 Real world analysis
The push pull converter has a few advantages over other topologies. The push pull converter has only 2 MOSFETs
which will result in easier control and a lower loss compared to some other topologies like the full bridge converter.
The MOSFETs in the push pull converter has both a grounded source and because of this the MOSFETs are easier to
control. Unlike other topologies the push pull converter can work with a duty cycle 0 ≤ D < 1 and this will result in
23
24. easier pick of component parameters and making the converter more reliable and efficient. But like everything else the
push pull converter has disadvantages. The 2 MOSFETs used in the push pull converter suffers under high voltage
stress (2 · V in) and therefore must be able to handle much higher voltage than other topologies. Because the push
pull converter only uses half the windings on the transformer, there is a high loss of magnetic energy in the core.
2.4.6 Component Stress Factors
The component stress factors can be seen in table 2.7.
Topology SCSF WCSF CCSF
Forward 73.12 93.90 0.00
Full Bridge 90.73 22.53 2.47
Half Bridge 25.24 5.61 2.22
Push Pull 46.62 5.95 0.88
Table 2.7: Table of Topology Component Stress Factors
The team selected the half bridge topology due to it having the lowest combined stress factor value. The half bridge
is ideal for low power applications. It has a low number of components, a wide range of duty cycles, and comparatively
low component stress. The low diode blocking voltage also suggests the possible use of a Schottky diode to reduce
forward voltage drop, and thereby reduce losses in the system. The half bridge converter cannot be current controlled,
but that is irrelevant to the project specification. The only true disadvantage of the half bridge converter is the need
for a high-side MOSFET driver.
24
25. Chapter 3
Magnetics Design
In this report the team designs the magnetic components of a half bridge converter. The inductors in the circuit have
a large effect on the output. A well-designed transformer can reduce losses in the circuit and a well-designed output
inductor can reduce the output ripple to reduce stress on other components in the circuit. For these, and other reasons,
proper design in vital to the end product. Some values from the initial design are necessary. The circuit schematic is
seen in figure 2.19 and the circuit characteristics are seen in table 2.3.
3.1 Inductor Design
For designing an inductor, key requirements should be made. These include the avoidance of saturation and a high de
winding resistance. The design process requires a large enough Kg (the effective magnetic core size), air gap, turns,
and wire size.
3.1.1 Core Material Selection/Specifications
Material The following specifications are for the N87 material used for the inductor’s core. The benefits of using
this material include a wide range of optimal frequency ranges and low core losses at relative frequencies. For our
Half-Bridge Converter, this material works the best.
Figure 3.1: Specifications for N87 Core Material
25
26. Table 3.1: Mathematical Constants at 100◦
C for selected core
Symbol Value
Wire Resistivity ρ 2.3µΩ
Peak Winding Current Imax 3.6
Ripple Current IL 0.6A
Ripple Current Acceleration Term Kr 3.0
Core Geometrical Constant Kg 1.03n
Inductance L 2.54µH
Winding Resistance R 0.000326ρ
Winding Fill Factor Ku 0.5
Maximum operating flux density Bmax 200mT
Core Window Area WA 18.45mm2
Mean length per turn MLT 2.0cm
Cross-sectional area of core Ac(Area of Core) 0.13cm2
Core Type An RM 7 core with material type N87 and with no air-gap was also chosen as it allows larger wires,
minimises board space, and is easy to assemble. The centre post also generates less core loss and heat buildup. The
small size also makes it a viable option as it makes the converter lighter and smaller.
Wire Selection/Specifications Litz wire was chosen for the windings. For the Half-Bridge Converter, a high
frequency wire is required. Litz Wire reduces the conductor impedance caused by eddy losses and the skin effect.
Because of this, the enamelled Litz wire was chosen.
For approximation purposes, the frequency that was utilised in determining the strand diameter was 100kHz. Thus,
the strand diameter is 0.100mm.
3.1.2 Design
Table 3.2: Calculations
Symbol Value
Number of Turns n 21
Air Gap AL 34.78 mH
1000turn
3.1.3 Number of Turns
The number of turns is calculated with the following formula. It is assumed that the number of turns is rounded up.
n =
L · Imax · 104
Bmax · Ac
= 20.8 (3.1)
Air Gap For the given core type and material, the AL is able to be determined via the following equation. This
value is useful in calculating the correct inductance value
AL = 1100 · 10−3
· 10 ·
√
10 ·
mH
1000turns
. (3.2)
The value ends up being 34.78mH/1000turn.
Core Geometrical Constant The Core Geometrical Constant is a measure of the magnetic size of a core when
winding resistance is a dominant constraint.
CoreGeometricalConstant =
Ac2
WA
MLT
≥
ρL2
I2
max
B2
maxRK2
u
(3.3)
For our purposes, we can make the constant anything greater than the calculated value. Because of this, the value
can be approximate the Kg to be 1.0289n.
Inductance The inductance was determined via a system of equations utilising the ripple current equation below.
The higher duty cycle was used and a frequency of 600kHz was also used. The frequency is double that of the switches
(the diodes rectify the bipolar current from the transformer).
Ic =
((1 − V out
V in ) · DutyCycle
L · Fr
(3.4)
26
27. Because we wanted our ripple current to be low and our Ripple Current Acceleration Term to be close to 3, we
decided to make the ripple current 0.6 and solve for the inductor value.
L =
n2
Rg
=
µ0 · Ac · n2
lg
= 2.54µH (3.5)
Winding Area For the winding area we wanted a small value. The value ended up being 0.309cm2
. This value is
the maximum winding area and is shown in 3.6. The maximum round area is given by equation 3.7. We also assumed
the value for Ku to be 0.5.
Ku · Wa ≥ n · Aw = 0.444 (3.6)
Ku · Wa ≥ n · Aw · 0.66 = 0.293 (3.7)
Winding Resistance/ Wire size The Winding Resistance can be calculated with the following equation. The
resistance created from the wire is directly proportional to the number of turns.
R = ρ ·
lb
Aw
= ρ ·
n · (MLT)
Aw
= 326µρ (3.8)
The wire needed for the inductor will be a Litz wire type with individual standard diameter of 0.050mm to get
the frequency range between 500kHz-850kHz as the inductor frequency will be the double of the converter frequency.
The total wire thinkness will be 0.54mm2
and the length will be 134mm. It will be arranged in 3 layers of 11 turn
and the inductor wire layout can be seen in figure 3.2
Figure 3.2: Inductor Windings
Note, the inductor in the circuit is gapless. This image was taken from the data-sheet and modified.
27
28. 3.2 Transformer Design
There are three major components to consider when designing a transformer: core material, core shape, and winding
type. Each of these has an effect on the behaviour of the transformer.
3.2.1 ETD 29/16/10 Design
Core Material Selection The core material sets the flux density of the magnetic field generated by the windings
of the transformer. The core material also affects the core losses and potential core failure by changing the Curie
temperature. The team analysed the given materials and found that only the N87 material had an acceptable frequency
range. The N97 material is very similar to the N87 material, as seen in table 3.3, with some notable improvements. The
N97 material has better permeability, flux density, Curie temperature, core loss, and effectively the same frequency
range and core shapes. Thus, the team plans to use the N97 core material in the transformer.
Property N87 N97
Material MnZn MnZn
Permeability 2200 ± 25% 2300 ± 25%
Flux Density (100◦
C) 390 mT 410 mT
Frequency Range 25–500 kHz 25–500 kHz
Curie Temperature > 210◦
C > 230◦
C
Relative Core Losses, 100 kHz, 200 mT, 100◦
C 375 kW
m3 375 kW
m3
Relative Core Losses, 300kHz, 200mT, 100◦
C 390 kW
m3 390 kW
m3
Relevant Core Shapes RM, ETD, EFD RM, ETD, EFD, ER
Table 3.3: Material Properties
Core Type Selection The team selected the ETD 29/16/10 core initially, as it appears large enough to house a
three winding transformer. To determine if this core is valid for use in this application, the team calculated the max
safe power dissipation in the core as seen in equation 3.9, where PCmax is the max safe power dissipation, Tmax is
the maximum temp, Tmin is the normal operating temperature, and Tr is the core thermal resistance given in the
data-sheet. Then the real core loss is calculated according to equation 3.10, where PCLoss is the real core loss, Pv is
the core material loss seen in table 3.3, and Ve is the volume of the core shape as given in the data-sheet. Since Ve is
given in mm3
and Pv is given in kw/m3
, the team used a conversion factor to ensure correct output. The results can
be seen in table 3.4.
PCmax =
TmaxTmin
Tr
(3.9)
PCLoss = Pv · Ve (3.10)
Next, the team selects the number of turns according to equation 3.11, where nsec is the number of turns on the
secondary, Vo is the transformer output voltage, d is the maximum duty cycle, fsw is the switching frequency, ∆B is
the total change in flux, and Ae is the core cross sectional area given in the data-sheet. This does not yield an integer,
so the next highest even integer is selected. Then, the number of turns in the primary, npri, is given by equation 3.12
where N is the turns ratio. The results can be seen in table 3.4.
nsec =
Vo
D
fsw · ∆B · Ae
(3.11)
npri =
nsec
N
(3.12)
Parameter Calculated Value
PCmax 2.68 W
PCLos 1.07 W
nsec 13.16 ≈ 14
npri 7
Table 3.4: Core Shape Results
28
29. Wire Selection Next, the team must select an appropriate wire type. Due to the high switching frequency of a half
bridge converter, the team chose to use Litz wire. This will reduce skin effect and proximity effect in the inductor,
thereby reducing the parasitic resistance and losses in the circuit. The team must also select the wire gauge. For
maximal efficiency, the windings should fill the window of the transformer core. The window area is given by equation
3.13, where Al is the window area, OD is the outer diameter of the core window, ID is the inner diameter of the
core window, h is the height of the core window, and the division by two is because only one side of the core need be
considered. The results can be seen in table 3.5.
Al =
OD − ID
2
· h (3.13)
Then, the team calculated the area of the window that can be occupied by wires according to equation 3.14, where
Acu is the area of copper and fcu is the fill factor of Litz wire given in the data-sheet. The results can be seen in table
3.5.
Acu = Al · fcu (3.14)
Since this area is used by all three windings of the transformer, the area of a primary or secondary winding is given
by Acu/3. Then, the team calculated the area of the individual wires according to equation 3.15, where Awire is the
cross sectional area of the wire, npri is the number of turns in the primary winding and n is the number of turns in
the winding. The results can be seen in table 3.5.
Awire =
Acu
3
n
(3.15)
The area of the wire can be used to find the radius of the wire to determine the number of turns per layer, as seen
in equation 3.16, where lbob is the length of the bobbin. The results can be seen in table 3.5.
turnsLayer =
lbob
3
2 · Awire
π
(3.16)
Next, the team calculated the length of the wires according to equation 3.17, where li is the length of the layer
i, K is the winding rotation factor, assumed to be 1.02 in this case, rbob is the radius of the bobbin, i is the layer
number starting at 0, rwire is the wire radius, and n is the number of turns in the layer. The winding rotation factor
is due to the slight rotation of the windings on the coil former, as they can not be truly perpendicular circles. This
increases the total length of the wire by a small amount, thus a factor of 1.02. The total length is the sum of the
different sections, plus an additional 20mm to each wire to account for the wire outside the coil former. The results
can be seen in table 3.5.
li = 2 · π · K · (rbob + i · rwire) · n (3.17)
The team used equation 3.18 to find the resistance of the windings, where ρ is the resistivity of copper at 100◦
C,
l is the calculated wire length given in table 3.5, and r is the wire radius. The results can be seen in table 3.5.
RDC = ρ
l
2πr2
(3.18)
The team then calculated the skin depth according to equation 3.19. Equation 3.19 yields the skin depth of a
copper conductor at 100◦
C, where δ is the skin depth in centimetres and f is the AC frequency, assumed to be
150kHz.
δ =
7.5
√
f
(3.19)
AC resistance of a Litz wire can be shown by equation 3.20, where RDC is the DC resistance given by equation
3.18 and Astr is the area of a single strand of the wire given in the data-sheet (Vaisanen et al. [2013]). The results are
shown in table 3.5.
RAC = RDC · Astr
sinh (2 Astr ) + sin (2 Astr )
cosh (2 Astr ) − cos (2 Astr )
+ 1/3
8
√
14
2
− 1 (sinh (2 Astr ) − sin (2 Astr ))
cosh (2 Astr ) + cos (2 Astr )
(3.20)
Next, the team calculated the magnetizing inductance of the transformer according to equation 3.21, where µ0 is
the permeability of free space, µr is the relative permeability of the core material, n is the number of turns, AL is
the cross-sectional area of the coil, and l is the length of the coil. The graphs shown in figure 3.3 illustrate the ±25%
variance in µr for N87 type material and N97 type material. The vertical black line marks the rated permeability for
both core materials.
29
30. Lm =
µ0µrn2
AL
l
(3.21)
Figure 3.3: Possible Magnetising Inductances with ETD 29/16/10 core
Finally, the team calculated the value of Kr according to equation 3.22 to ensure the core loss and wire loss had
an acceptable ratio. The results of this equation are shown in table 3.5. While the Kr value is not within the optimal
range of 2–3, the team believes it is close enough to be acceptable in this application.
Kr =
IMax
IP eak−P eak
(3.22)
30
31. Parameter Calculated Value
Al 97.0 mm2
Acu 38.8 mm2
AwireP ri 1.3 mm2
AwireSec 0.65 mm2
turnsLayerP ri 7.1 ≈ 5
turnsLayerSec 10.0 ≈ 10
lpriT otal 413 mm
lsecT otal 797 mm
RDCP ri 11.1 mΩ
RDCSec 42.9 mΩ
RACP ri 12.4 mΩ
RACSec 46.6 mΩ
Kr 1.39
LM 53.2 µH
PCore 1.07 W
PW ire 0.86 W
PT otal 1.93 W
PCMax 2.68 W
Table 3.5: ETD 29/16/10 Transformer Results
As seen in table 3.5, the calculated Ploss is quite close to the allowable PCMax. After many iterations of the ETD
core shape, and many different sizes the team could not find an acceptable core loss dissipation.
EFD 25/13/9 Design
Thus, the team used equations 3.10 to 3.22 on different core shapes to determine a better core shape. For some cores,
the winding bobbin was rectangular and thus the team used equation 3.23 when calculating the wire length, where i
is the layer number starting at 0, hbob is the height of the bobbin, wbob is the width of the bobbin, K is the winding
rotation factor, assumed to be 1.02 in this case, and n is the number of turns in a layer. The total length is the sum
of all layers, plus an additional 20mm to each wire to account for wire outside the coil former.
li = (2 · hbob + 2 · wbob) · K · n (3.23)
The team decided that the EFD 25/13/9 type was acceptable for the application, due to the larger overhead of
power dissipation, lower overall power dissipation in the core, lower ripple current, and lower RMS current which
reduces component stress. However, the EFD core has a less favourable ratio of winding to core power loss and fewer
turns on the transformer. The team chose a switching frequency of 300kHz to have similar wire and core losses. The
results of the EFD calculations are seen in table 3.6. The winding distribution is seen in figure 3.4
31
32. Parameter Calculated Value
npri 6
nsec 12
Al 51.7 mm2
Acu 20.7 mm2
AwireP ri 1.15 mm2
AwireSec 0.57 mm2
turnsLayerP ri 6.39 ≈ 6
turnsLayerSec 9.04 ≈ 6
lpriT otal 226 mm
lsecT otal 496 mm
RDCP ri 6.9 mΩ
RDCSec 30.1 mΩ
RACP ri 14.1 mΩ
RACSec 52.8 mΩ
Kr 1.85
LM 26.6 µH
PCore 0.66 W
PW ire 0.87 W
PT otal 1.29 W
PCMax 3.0 W
Table 3.6: EFD 25/13/9 Transformer Results
Figure 3.4: Transformer Windings
Note, the primary windings are in red, secondary one in blue, and secondary two in green. The isolation material is
shown in yellow.
Possible magnetizing inductances can be seen in the graphs of figure 3.5. It is worth noting, that the magnetizing
inductance will be slightly less than half that of the ETD core scenario. However, the team decided that over all size,
weight, and a core loss was a better result. The ratio between the losses are slightly worse for the EFD core, but this
is an acceptable trade off. Furthermore the estimated losses of the ETD core are much further below the limit than
that of the EFD core scenario. This means, that the transformer may driver a larger load without overheating. It
could be possible to charge more than one laptop or maybe charge one laptop and one tablet. The team decided that
this would make for a better and more versatile product without adding higher costs and more components to the
design.
32
33. Parameter ETD EFD
Pwire 0.86 W 0.87 W
Pcore 1.07 W 0.66W
Ptotal 1.70 W 1.53 W
Pmax 2.68 W 3.00 W
Possible power increase 38.79% 96.31%
Pwire
Pcore
0.80 1.31
Table 3.7: Comparison of losses using different cores
Figure 3.5: Possible Magnetising Inductances with EFD 25/13/9 core
33
34. 3.2.2 Magnetics summary
The transformer was designed with 6 turns on the primary winding and 12 turns on the secondary winding. After an
iterative process, including designs with different kinds of core material, the team selected the EFD5 core and N97
material as this provided better characteristics with regard to permeability, curie temperature, etc.. This led to a wire
loss of 0.87 W and 0.66 W which is considered satisfactory. Furthermore the size of the core was reduced considerably.
The team also took into account the ±25% of possible tolerance in permeability such that the transformer would still
be functional at either extreme.
The output inductor was designed with 21 turns, an air gap and the N87 core material. The core type was chosen
to be the RM7 core. The output inductors values of 2.54µH and its small physical size owes to the higher frequency
it experiences. The topology of the converter essentially rectifies the current from the transformer, thus making the
output inductor experience double the frequency, resulting in 600 kHz. Increased frequency has the benefit of smaller
magnetic components as is achieved in this project.
The final waveforms of the circuit are seen in figures 3.6 to 3.17.
Figure 3.6: Q1 Waveforms
Figure 3.7: Q2 Waveforms
Figure 3.8: D1 Waveforms
Figure 3.9: D2 Waveforms
34
36. Figure 3.15: D4 Waveforms
Figure 3.16: Output L Waveforms
Figure 3.17: Output C Waveforms
The designed magnetic components have low total losses, as well as a good ratio of wire and core loss. This lends
itself to a high overall circuit efficiency. The necessary materials to construct the magnetic components are seen in
table 6.3.
36
37. Chapter 4
Filter Design
4.1 Filter Design
4.1.1 Introduction
In this section, the team details the design of input and output filters for the half-bridge buck converter. The filters
are important to the safety of the device connected to the output, in this case a laptop, as well as to satisfy the EMC
standards for high-frequency devices. The schematic before the inclusion of the filters is seen in figure 2.19. The Small
Signal Model of the circuit equivalent to that in figure 2.19 is shown in figure 4.1. The system requirements are seen
in table 2.3.
The small signal model may be derived much the same way as a regular buck converter. The functionality of the
half bridge buck converter is such that only one switch is one at any one time, also there will be some time where
both are off. Current will only flow out of one of the two secondary windings at any one time, thus the half bridge
buck can be modelled just like the buck converter with the addition of the turns ratio in the transformer.
Figure 4.1: Small Signal Model of Half-Bridge Circuit
When designing a product that is to be sold on the market the EMC directives must be obeyed. Different EMC
directives exist throughout the world. In this project, the team will conform to the CISPR-13 standard.
4.1.2 Input Filter
To design the input filter, the team had to take into account the in input impedance of the converter so as to not
impede operation of the switching control circuits, CISPR standard 13 for EMC input noise, and overall filter cost.
The results of the calculations in the section are seen in table 4.1
ZN , the converter input impedance with no small changes in the output voltage, and ZD, the converter input
impedance with no small changes in the duty cycle, can be used in equations 4.2 and 4.3 to determine acceptable
values of ZO. The output inductor is 2.54 µH and the output capacitor is 2.5 µF which will be shown later. When the
input filter is designed, the output impedance of it must follow Middlebrook’s Extra Element Therom which states,
that the addition of impedance will change the transfer function of a power converter. Thus it will change the control
loop transfer function which may degrade performance. To avoid this, Middlebrook’s Extra Element Theroem provides
a correctio factor:
Correctionfactor =
1 + Zo(s)
ZN (s)
1 + Zo(s)
ZD(s)
(4.1)
The original transfer function of the converter and control is multiplied by the correction factor given in eq. 4.1.
When the correction factor is close to unity, the transfer function of the control and converter loop will not be affected
considerably. To achieve this, the following inequalities must be met:
|ZO| |ZN | (4.2)
|ZO| |ZD| (4.3)
37
38. ZN is seen in equation 4.4, where R is the modelled output resistance, N is the turns ratio, and D is the worst-case
duty cycle, 0.791.
ZN (s) = −
R
N2D2
(4.4)
ZD is seen in equation 4.5, where L is the converter output inductance, and C is the converter output capacitance.
ZD(s) =
R(1 + sL
R + s2
LC)
N2D2(1 + sRC)
(4.5)
Whereas ZN (s) is constant, ZD(s) is not. Thus, ZD(s) is plotted versus frequency in fig. 4.2
Figure 4.2: Magnitude plot of ZD
It is noted, that ZD(s) has its lowest value of -20 dB at approximately 56 kHz. -20 dB corresponds to a decimal
value of 0.1. With the given component values, |ZN | is equal to 2.53. To satisfy Middlebrook’s inequality, the output
impedance, Zo of the input filter should be lower than 0.1. A factor of 10 is chosen.
The schematic of the input filter output impedance is seen in figure 4.3, where Lf is the filter inductance, Cf is
the combination of series capacitances Ci1 and Ci2, Ri is the filter damping resistance, and Cb is the filter damping
capacitance. Since the half-bridge converter design already includes two capacitors on the primary side, Ci1 and Ci2
as seen in figure 2.19, it is possible to use them as part of the imput filter as well. It is simple to calculate values of
Lf and Cb using equation 4.6, where ZCb is the capacitor impedance and ZLf is the inductor impedance.
Figure 4.3: Filter Output Impedance Calculation Schematic
ZO = ZCin||ZLi||ZRbCb
=
1
2πfswC + 1
2πfswL + 1
Rb+ 1
2πfswCb
(4.6)
Equations 4.7 to 4.9 are used to calculate the proper attenuation to comply with CISPR standard 13, where Asq is
related to the ripple current, Ipk is the peak small signal current, fsw is the switching frequency, ZLISN = 50Ω is the
LISN network input impedance, dBµA is the relative current signal strength, and dBµV is the relative voltage signal
strength. Given that CISPR standard 13 allows for 56dBµV , the design requires some attenuation, plus arbitrary
overhead for safety.
Asq =
Ipksin(πDfsw)
π
(4.7)
38
39. dBµA = 20log10(Asq) + 120 = 50dB (4.8)
dBµV = 20log10(ZLISN ) + dBµA = 85dB (4.9)
As a safety margin, 20 dB is added, making for an attenuation of 105 dB.
The cut-off frequency of this filter must be low enough to cause the proper attenuation for the CISPR standard.
The cutoff frequency, fc, is selected at 500 Hz, to make sure the attenuation of 105 dB is achieved at already 150 kHz.
The CISPR-13 standard measures the noise from 150 kHz up to 30 MHz. The filter inductor is chosen to be 500µH,
and the filter capacitor can be solved for in the resonant frequency equation:
ff =
1
2π Lf Cf
→ Cf ≈ 500µF (4.10)
The ratio between Cf and Cb is chosen to be 4, since this value will result in the optimum blocking resistor being
equal to the characteristic impedance of the filter [Sclocchi, 2010]:
Rb =
Lf
Cf
= 0.63Ω (4.11)
The blocking capacitor may then be found to be:
Cb = Cf · 4 = 500µF · 4 = 2mF (4.12)
For comparison, two graphs will follow in fig. 4.4 & 4.5. One will be the designed filter with dampening and the
other will be the filter without the dampening. This is done in order to examine the influence of the dampening
network on the filter behaviour. The dampening resistor and capacitor is desired to only reduce the resonant peak and
not otherwise impact the filter characteristics. Some influence may be unavoidable, however minimising it is much
desired.
Figure 4.4: Magnitude plot of the filter with dampening network
39
40. Figure 4.5: Magnitude plot of the filter without dampening network
As can be seen in the plots of fig. 4.4 & 4.5, the dampening network effectively reduces the size of the resonance
peak. The peak is reduced to approximately 3 dB- The cross over frequency is slightly lower, but the low frequency
asymptote and the high frequency asymptotes remain the same. In fig. 4.6 a zoomed in view of the damped filters
magnitude plot is illustrated. The attenuation at 150 kHz is approximately 99 dB and at 300 kHz it is approximately
111 db. From this, it is seen that the attenuation at the switching frequency is 6 dBs better than what was required
and that the attenuation at 150 kHz is also very good.
Figure 4.6: Zoomed in view of the magnitude plot of the filter with dampening network
In-Rush Current Due to the high switching frequency, in-rush current can be quite high. It is calculated according
to the ETSI standard as seen in figure 4.7.
40
41. Figure 4.7: Caption
Input filter summary
The input filter has been successfully designed. The output impedance of the filter satisfies the Middlebrook’s Extra
element theorem:
|Z0| ≤ |ZN | (4.13)
0.01 ≤ 2.53 (4.14)
and
|Z0| ≤ |ZDlowest| (4.15)
0.01 ≤ 0.1 (4.16)
The filter sufficiently damps the resonance peak and does not affect the low and high frequency asymptotes.
The given values for the filter comply with both technical design specifications, while being small for low cost and
low circuit footprint. Typically an in-rush current limiting circuit would be placed before the input filter, similar to
the circuit in figure 4.8.
Figure 4.8: In-rush Circuit Schematic
Fortunately, the PWM controller described in section 5.2 has a soft-start mode. This mode limits the duty cycle
on start-up, limiting the possible in-rush current to manageable levels. This removes the need for an in-rush limiting
circuit.
41
42. Characteristic Value
ZN -2.53 Ω
ZO 0.001 Ω
Asq 0.000338 A
dBµA 50.6 dB
dBµV 84.6 dB
Attenuation + 20dB safety margin 105dB
Cf 500µF
Ci1 = Ci2 1mF
Lf 500µH
Ri 0.63Ω
Cb 2mF
Table 4.1: Input Filter Calculated Values
4.1.3 Output Filter Design
An output filter for a Half-Bridge Buck converter is compromised of an inductor and capacitor as seen in figure 4.9.
Its purpose is to smoothly deliver energy to the load. The output inductor influences the amount of ripple current
experienced on the load; the higher the inductance, the lower the ripple current along with maintaining a minimum
inductance. Similarly, the output capacitor influences the amount of ripple voltage and a minimum capacitance must
be met to meet the requirements of the converter. If the capacitance is high the ripple voltage and voltage overshoot
is low, however, the time for feedback loop response increases.
Figure 4.9: Basic LC Output Filter
The values from the following equations are given in Table 4.2. Equations 4.18 and 4.19 are utilised to calculate
the appropriate capacitance value. Equation 4.18 is used to calculate the minimum capacitance from the ripple
consideration. Equation 4.19 is used to calculate the capacitance from the overshoot consideration voltage.
After each of these equations are calculated, the lowest possible capacitance has to be the higher out of the two
resultant values. The value Irip is the Ripple Current, T is the Period, Vpp and Vov is the Voltage overhead.
Vov = 3% · Vo (4.17)
Cmin =
Irip · T
8 · Vpp
(4.18)
Cmin =
L · I2
rip
((Vov + Vo)2 − Vo)2
(4.19)
Equation 4.20 is used to calculate the Equivalent Series Resistance. This value stems from the series resistance
from the capacitor. It impacts the output voltage ripple and efficiency of the converter. Ip is the peak current.
ESRmax =
Vov
Ip
(4.20)
Equation 4.21 is used to calculate the RMS current that flows throughout the output capacitor. The ripple current
is directly proportional to this value.
42
43. IcRMS = (
(I2
rip)
12
) (4.21)
The transfer function for the Output Filter is given in the equation 4.22. This equation includes the output
capacitor, inductor, and resistor. In figures 4.1.3 and 4.1.3, the bode plot of this transfer function is shown.
T2 =
1/(( 1
R1+s · C3)
(( 1
R1+s · C3) + s · L1))
(4.22)
One can see from the bode plot that there is a pole at around 60Hz with a peak magnitude of around 12 dB. This
correlates to the frequency plot where the peak value occurs at −100 deg in phase.
Figure 4.10: Output Filter Bode Plot
Figure 4.11: Output Filter Phase Diagram
Value Symbol Value
Ripple Current ∆I 0.6A
Peak to Peak Current Across Inductor and Capacitor Ipp 0.6A
Capacitor RMS Current IcRMS 173mA
Inductance L1 2.54µH
Capacitance C3 2.5µF
Output Inductor Frequency Fw 600kHz
Period T 1.67µs
Ripple Voltage ∆V 50mV
Voltage Overshoot Vov 57mV
Output Voltage Vo 19V
Peak to Peak Voltage across Inductor and Capacitor Vpp 10.5V
Equivalent Series Resistance ESRmax 0.25Ω
Equivalent Series Resistance of Capacitor ESRC3 2.9mΩ
Output Resistor R1 6.33Ω
Table 4.2: Output Filter Characteristics
43
44. 4.2 Filter Design Summary
Based off our findings for the input and output filters, the team was able to make a list of components for our Half-
Bridge Buck Converter. The final circuit is visible below in figure 4.12. In tables 4.1 and 4.2, values for Ri, Cif , Li,
L1, C3, and R1 are designated to the components within the circuit.
Figure 4.12: Half-Bridge Circuit Schematic with Input and Output Filters
44
45. Chapter 5
Controller Design
5.1 Selection of controller type
The purpose of a controller is to maintain constant output voltage in spite of changes in current and voltage. Because
the team is using a Half-Bridge converter topology, current programmed control is not an option due to the high
amounts of current flowing through the transistors. Due to the limitations of our design, the team decided to utilise
voltage mode control.
In power electronics, when control is to be designed, one might look to control schemes called type 1, 2 and 3.
These types are related, but not identical, to regular controllers; PID, PI, PD, etc. In a power converter, it is the
output filter that dominates the cross over frequency, thus an adjustment in the gain will not have an effect on it,
though the controller itself may. The gain will have an effect on the static error and low frequency response, an
integral term will also contribute to a small, if not zero, static error. Dependent on the converter, the phase might
be in need of adjustment and this is what is the aim of control in power electronics. The different control types offer
different possibilities of introducing poles and zeroes in the transfer function. Poles provides a negative turn in phase
and zeroes provide a positive. By careful design of these poles and zeroes, the designer can tune the phase and provide
a so called boost, if necessary. The type 1 control is an integral term with one pole at the origin and will not boost
the phase, it is the simples of the three. The type 2 control has one pole at the origin and one pole and one zero, that
can be placed where it is desired. Dependent on the placement of the pole and zero, the phase may be boosted up
to 90 degrees. The type 3 control has one pole at the origin and the designer can place two poles and two zeroes as
desired.
To determine if the converter is in need of a phase boost, the frequency response must be investigated. In this
situation, the converter at hand is drawn up and simulated with the PLECS software. The bode plot of the converter
without control is illustrated in fig. 5.1
Figure 5.1: Bode plot of the designed HB buck conveter
The cross over frequency of the converter without control is at 60 kHz and the phase is -80 degrees at this point
and will end at 90 degrees. Thus the phase margin in 100 degrees and is not in need of a boost. With this in mind,
the type 1 control may be designed. The circuit is illustrated in fig. 5.2
45
46. Figure 5.2: Type 1 controller schematic. Vo is the controller output and Ve is the error signal
Vref is selected to be 7.5V and thus the converter output must divided from 19V as is desired to 7.5V. This is
done by R1 = 660 kΩ and R2 = 430 kΩ.
The transfer function for the type 1 is given by:
TT ype1 =
1
R1 · C1 s
(5.1)
R1 has already been determined and C1 is selected to be 1µF this will makes sure it dominates over any parasitic
elements when the circuit is built and will places the pole in low frequency. The transfer function for the controller
may the be rewritten as:
TT ype1 =
1.5
s
(5.2)
The Bode plot of the converter with type 1 control is illustrates in fig. 5.3
Figure 5.3: Bode plot of the designe HB buck conveter with type 1 control
As can bee seen in figure 5.3, the cross over frequency has decreased to approximately 15 kHz, which is to be
expected. The type 1 controller is an integrator term and has as pole at low frequencies as detailed earlier. Thus the
whole graph is shifted down, and the cross over frequency is lowered. The phase margin is increased slightly. The
reason the the increased phase margin is exactly the slight shift in gain and no change in the phase, as is expected
from the type 1 control.
Next, the output of the converter is simulated. The result is simulated in fig 5.4
46
47. Figure 5.4: Current (top) and voltage (bottom) of the simulated converter with type 1 control
The output power increases smoothly at start up. No overshoot is seen and steady state is reached after approxi-
mately 200 ms.
For the comparator in the type 1 compensator, the TL431 with Vref set to 7.5 V is used.
During the initial stages of the design, the team chose components from the list given in class. The component list
is seen in table 5.1.
Component Part Number
Controller UC3825
Comparator TL431
Opto-coupler 4N35-37
Gate driver HIP 2100
Table 5.1: Initial list of components
While researching these components, the team discovered a chip specifically designed for half-bridge switching
control, the LM5039. It includes an integrated reference voltage, PWM controller, and gate driver. The chip costs
about the same as a single one of the individual components in table 5.1. This makes it the obvious choice going
forward.
5.2 PWM Controller and Gate Driver
The team selected the LM5039 as the MOSFET controller. The simplified application schematic is seen in figure 5.5
[PWM, 2004]. The LM5039 consists of a controller with a comparator for the regulation and a gate driver build for the
half bridge converter. The chip can run on voltages between 13 to 100v then there will be no issue powering it with the
solar panel. There is adjustable soft start capability to prevent overshoot at start-up. The gate driver has the needed
high and low side drivers which are capable to deliver 2A peak. This should be enough to power large MOSFETs. The
build in oscillator can be programmed up to frequencies of 2MHz which suits the demand of a switching frequency of
300KHz for this converter.
By using this controller the team will reduce the cost price, power consumption and the complexity of the controller
module when the prototype is going to be designed and build later in this course.
47
48. Figure 5.5: PWM Controller Circuit Schematic
For proper implementation of the LM5039 chip, a few external components are necessary. Resistor RT , connected
to the RT pin in figure 5.5 controls the oscillation frequency according to equation 5.3. A comparison of the two values
is given in the data-sheet, as seen in figure 5.6.
RT =
1
Fosc
10 · 109
= 33.3kΩ (5.3)
Figure 5.6: Oscillation Frequency vs. RT
The UV LO pin controls the under-voltage lockout of the chip. Above a voltage threshold, the chip functions
normally, but below that threshold it will shutdown or standby, depending on the values of RUV LO1, between VIN
and UV LO, and RUV LO2, between UV LO and GND. These resistances are calculated according to equations 5.4
and 5.5, where VHY S is the desired hysteresis voltage under VP W R and VP W R is the desired turn on voltage at VIN .
RUV LO1 =
VHY S
23µA
= 870kΩ ≈ 820k + 75kΩ (5.4)
48
49. RUV LO2 =
1.25R1
VP W R − 1.25
= 48kΩ ≈ 47k + 1kΩ (5.5)
The RAMP pin controls the PWM ramp signal. This signal varies in proportion to the input line voltage, allowing
for voltage mode control of the MOSFETs. The RAMP signal is compared to the error signal to control the duty
cycle of the HO and LO MOSFET drivers. The values CF F , connected from RAMP to GND, and RF F , connected
from VIN to RAMP, control the maximum on-time of HO and LO MOSFETs. Given the switching frequency and
maximum duty cycle of the converter and given a standard value for CF F in the data-sheet of 470pF, RF F is calculated
according to equation 5.6.
RF F =
TON + 10%
CF F · ln[(1 − 2.2V
VIN
)−1]
= 32.7kΩ ≈ 33kΩ (5.6)
The COMP pin takes in the current output of the opto-coupler. The internal circuit converts the current to a
voltage via an internal 6kΩ resistor, then compares it to the RAMP voltage. In the Figure 5.8 this can be seen along
with the rest of the opto-coupler-controller interface.
For calculating the bootstrap capacitor(CBoot), ACL capacitor (Cacl), and the soft start capacitor (Css), either
the 430irf Mosfet or the UC3825 controller data-sheet were used. For Cacl and Css, pre assigned values were found
and used for values; they ended up being 1nF and 10µF. They are seen in the final schematic in figure 6.1
The bootstrap capacitance was calculated using equations 5.7, 5.8, and 5.9. In equation 5.7, Vgs is the minimum
gate source voltage, VF is the voltage over the diode, and VDD is the supply voltage.
Vboot = VDD − VF − Vgs (5.7)
When calculating the total charge from all the components in equation 5.8, Ton is equivalent to 0.5D
fswitch
where D is
the worst case duty cycle (0.791) and fswitch is 300kHz. Also, Qgmax refers to the maximum charge across the gate,
Qgate refers to the total gate charge, ILgs is the leakage current from the gate source, ILcap is the current leakage from
the capacitor, Ilboot is is the leakage current from the bootstrap circuit, and Qls is the charge for the internal level
shifter.
Qtotal = Qgmax + QLgs + (ILgs + ILcap + Ilboot) · Ton = 73nC (5.8)
Finally CBoot is calculated in equation 5.9
Cboot =
Qtotal
Vboot
= 5.1nF (5.9)
5.3 Optocoupler
In this section, the opto-coupler will be explained and investigated. The need for electrical isolation in power systems
should be readily understood. One would not desire to direct the flow of power anywhere but to the intended load.
Furthermore electrical isolation may be important both for safety as well as durability. The isolation between certain
parts of the system may decrease the risk of power surges into sensitive components. In this situation, the voltage at
the output must me sensed in order to perform closed loop control of the converter. As the converter delivers over
50W to the load, it is highly unwanted that this power might, for some reason, find its way to sensitive components
like op-amps. Bu using isolation, an upper limit for the voltage and current going into these components may be set.
This limit can be much lower than the sensed voltage.
5.3.1 Operation
An opto-coupler consists of a light source and a light sensor. When a voltage is applied to the source, the sensor will
draw a current from another source. In this case, the opto-coupler consist of a LED and a photo-transistor. When a
forward voltage is applied to the LED, light is produced within the casing. As with any other diode, the higher the
voltage is, the more current flows. This is a non-linear relation. When more current is flowing, more light is produced.
As the photo-transistors base i subjected to the light, it will conduct a current. The more light it is subjected to, the
more current flows. Once again this is a non-linear relation. Because of the non-linearities, one should take care to
determine an operating point and linearise operation around it. By use of a voltage divider, the quiescent point may
be set with the component rating in mind.
49
50. 5.3.2 Design
The schematic for the selected opto-coupler is shown in figure 5.7.
Figure 5.7: Optocoupler schematic
The opto-coupler outputs a current. This current could be used in control containing current mode devices or
a resistor may be placed in parallel between the emitter and GND. In this design, the current mode operation is
chosen since the selected controller requires it. In figure 5.8 it is illustrated how the collector of the photo-transistor
is connected to the controller.
Figure 5.8: Optocoupler-controller interface schematic
As described in the data-sheet of the LM5039 PWM controller, the output duty cycle ranges with current into the
COMP pin. It ranges from maximum duty cycle at 0mA and minimum at 1mA. Thus the opto-coupler output should
be selected to comply with the controller.
When studying the data-sheet of the CEL PS2811-1M opto-coupler, the voltage-current characteristics for the
diode is such, that 0.4 mA is running through the photo-LED at 1 V forward voltage and 25◦
C forward as seen in
figure 5.9Opto-coupler [2013].
50
51. Figure 5.9: LED conduction graph
At an input diode current of 0.4mA, the opto-coupler output side will supply between 1.25 and 2 times the input
side current, as seen in figure 5.10. This is within the range of acceptable COMP pin currents. A higher converter
output voltage will increase the voltage in the controls section thereby increasing the opto-coupler input current,
output current, and finally decreasing the duty cycle. The opposite is also true, a lower converter output voltage
increases the duty cycle, as expected. Due to the multiplicative nature of the opto-coupler current ratio, a small
change in the converter output voltage will cause a relatively large change in duty cycle. This may cause issues with
stability, but should allow for quicker response to voltage fluctuation.
Figure 5.10: Input to output current transfer characteristics
The components necessary for the converter controller design were determined and are tabulated in 6.3. It should
be noted that when 2 occurrences of the same component occur, this is done on purpose. Due to the specificity of
our applications and limited availability of a very specific resistor value, the team decided to use resistors in series to
attain the appropriate resistance value.
51
52. Chapter 6
Conclusion
The final circuit schematic is seen in figure 6.1.
Figure 6.1: Final Schematic with Component Values
The half-bridge topology is the result of a selection process, where several converter topologies were examined.
The topology with the lowest overall component stress factors was selected and the team moved forward with this
topology.
In conclusion, the Half-Bridge Converter is ideal when low power levels are utilised. The Half-Bridge is advantageous
due to its low part use, wide range of duty cycles, and maximum switch blocking. Its disadvantages are, however,
that it cannot be current programmed due to the high amounts of current that flow through the transistors, since the
transistor current is directly correlated to transformer turns. For these reasons, the team chose this converter topology
to build on in the rest of the report.
As a step down converter, the Half-Bridge converter is a viable choice as the output voltage follows 0.5NDVin.
As with any converter, in general, this topology requires control to regulate the output voltage. The converter must
syphon power from a solar panel which, depending on the available light, will put out different voltages, thus the
system should be able to react to these changes and keep the output voltage at 19V when the input is between 24V
and 45V.
The controller is implemented with a type 1 negative feedback compensator, isolated with an opto-coupler. The
type 1 compensator does not boost the phase. The phase of the converter’s transfer function did not turn below -90
degrees, thus a phase boost was not necessary.
To comply with EMC standards the team designed an input filter. In addition the output filter was tuned to fit
the specifications of the project. The output filter is the main manipulator of the converters cross over frequency,
thus the compensator will only have some impact on this, furthermore, the gain of the compensator will not affect
the crossover frequency. A large loop gain will however reduce the static error. The input filter was designed with
an output impedance that is much lower than the input impedance of the converter, in order to not affect the closed
loop control transfer function. The lowest input impedance was found to be 0.1Ω and the team chose that the output
impedance of the input filter should not exceed one tenth of that. The output impedance was found to be only 0.001Ω
which is very good. The input impedance is damped so that the resonance peak is only 3 dB.
The components that make up the output filter has turned out to be relatively low in value and thus quite small
in physical size. This is to be expected from the 600kHz they experience as previously stated. Both filters exhibit
good characteristics and behaviour when their corresponding Bode plots are examined.
The team also included PWM control and gate driver IC in the design. The combined IC allows for fewer
components, circuit simplicity, and overall lower cost than selecting multiple individual components.
In final conclusion, the team has successfully designed a DC-DC power converter along with appropriate control
and EMI filters.
52
53. 6.1 Parts List
The parts referenced in this section use the labels from the final schematic, seen in figure 6.1.
Component Description Distributor Dist. Part No. Price
Transformer EFD 25/13/9 N97 B¨urklin B66421G0000X197 e0.75
Transformer Primary 1.15mm2
x 226mm Litz In House N/A N/A
Transformer Secondary 0.57mm2
x 496mm Litz In House N/A N/A
Output Inductor Core RM 7 N87 no air-gap Mouser B65819J0000R087 e1.77
Output Inductor Wire 0.54mm2
x 134mm Litz In House N/A N/A
Cout 2.7µF RS Components 808-3450 7DKK per
CSW 1&2 2 x 100µF RS Components 519-4059 1.4DKK per
D1 & D2 2 x P600B-E3/54 Diode RS Components 639-1532 4.4DKK per
M1 & M2 2 x IXFP10N60P RS Components 194-502 17.2DKK per
Total Price 73DKK
Table 6.1: List of Components for Converter
Component Description Distributor Dist. Part No. Price
Rin 0.6Ω RS Components TBD TBD
Cin 220µF RS Components 762-1796 15DKK
Lin RM 6 N87 Core In House N/A N/A
Lin Wire In House N/A N/A
Total Price 15DKK
Table 6.2: List of Components for Input Filter
Component Description Distributor Dist. Part No. Price
Controller LM5039 Mouser 926-LM5039MH/NOPB 4.72e
Optocoupler PS2811-1M Mouser 551-PS2811-1-M-A 0.88e
RT 33.3kΩ RS Components 683-3544 0.81DKK
RUV LO1 820kΩ RS Components 165-1283 0.28DKK
RUV LO1 75kΩ RS Components 487-8087 5.63DKK
RUV LO2 47kΩ RS Components 148-893 0.33DKK
RUV LO2 1kΩ RS Components 707-7666 0.17DKK
RRAMP 33.3kΩ RS Components 683-3544 0.81DKK
CRAMP 470pF RS Components TBD TBD
CSS 10µF RS Components TBD TBD
CACL 1nF RS Components TBD TBD
CBOOT 5.1nF RS Components 851-8310 1.79DKK
RSUP 100Ω RS Components 148-269 0.35DKK
RREF 1 576Ω RS Components 754-6708 1.092DKK
RREF 2 1kΩ RS Components 707-7666 0.17DKK
CREF 100nF RS Components 653-0153 1.329DKK
ROP T O1 100Ω RS Components 148-269 0.35DKK
ROP T O2 2kΩ RS Components 148-578 0.35DKK
CCOMP 1µF RS Components 721-5265 8.122DKK
RCOMP 1 680Ω RS Components 683-5723 1.029DKK
RCOMP 2 1kΩ RS Components 707-7666 0.17DKK
Total Price 64.432DKK
Table 6.3: List of Components for Controller
The total price for the whole controller is ≈ 153 Danish Kroner.
53
54. Chapter 7
Authorship
Table 7.1 details the authors of each section. If no subsections are listed, assume the author(s) wrote all subsections
within the section listed.
Author Sections
Nathan Wiegman 1, 2.2, 3.2, 4.1.1, 4.1.2, 5.2, 5.3 5.1, 6, 7
Søren Ryeskov 1, 2.1, 3.2, 4.1.2, 5.1, 5.3, 6
Emre Gezgin 2.4, 3.1, 3.2.2, 4.1.3, 5.2, 6
Dhairav Vakil 2.3, 3.1, 3.2.2, 4.2, 4.1.3, 4.2, 5.2, 6, 7
Table 7.1: Authorship
54
55. Bibliography
Opto-coupler. Ps-2811-1 ps2811-4 low input current, high ctr 4, 16-pin ssop photocoupler, 2013. URL
http://www.cel.com/pdf/datasheets/ps2811.pdf.
PWM. Uc3825 high speed pwm controller, 2004. URL http://www.ti.com/lit/ds/symlink/uc1825.pdf.
Michele Sclocchi. Input filter design for switching power supplies, 2010. URL
http://www.ti.com/lit/an/snva538/snva538.pdf.
Vesa Vaisanen, Jani Hiltunen, Janne Nerg, and Pertti Silventoinen. Ac resistance calculation methods and practical
design considerations when using litz wire. IEEE Industrial Electronics, 39th Annual Conference:368–375, 2013.
55
