EE5440 – Computer Architecture - Lecture 3
•Download as PPTX, PDF•
0 likes•783 views
Topics included: ================================================= Assembly Language CISC Instruction Sets Characteristics of RISC RISC and CISC Styles Encoding of Machine Instructions
Recommended
Recommended
More Related Content
What's hot
What's hot (20)
Similar to EE5440 – Computer Architecture - Lecture 3
Similar to EE5440 – Computer Architecture - Lecture 3 (20)
More from Dilawar Khan
More from Dilawar Khan (8)
Recently uploaded
Recently uploaded (20)
EE5440 – Computer Architecture - Lecture 3
- 1. EE5440 COMPUTER ARCHITECTURE Mr. Dilawar Lecturer, Computer Science Faculty, Bakhtar University Kabul, Afghanistan.
- 2. Previous Lecture • Memory Locations and Addresses • Memory Operations • Instructions and Instruction Sequencing • Addressing Modes
- 4. Lecture Outline • Assembly Language • CISC Instruction Sets • Characteristics of RISC • RISC and CISC Styles • Encoding of Machine Instructions
- 5. Assembly Language • So far, we used normal words for instruction operations • Replaced by acronyms called mnemonics such as LD, ST, ADD, and BR. • These mnemonics and rules for their use – assembly language. • Set of rules and specification of a complete instruction – Syntax. • Assembler – In memory and processes the user program. • Source program and object program.
- 6. CISC Instruction Sets • They are not constrained to load/store architecture. • Instructions do not necessarily have to fit into a single word. • Most AL operations use two-address format. • Modern CISC processors typically do not use a three-address format.
- 7. CISC Instruction Sets • An Add instruction of this type is • Consider again the task of adding two numbers
- 8. CISC Instruction Sets • Contains the functionally of Load and Store instructions, with a different approach
- 9. CISC Instruction Sets Additional Addressing Modes • Auto-increment mode • EA is the content of register; Value is incremented automatically when used. • Auto-decrement mode • Access the memory location reverse order. • First decremented and then they are used as EA. • EA is determined by the index mode using the PC in place of general purpose register – Relative Addressing.
- 10. CISC Instruction Sets Additional Addressing Modes
- 11. CISC Instruction Sets Condition Codes • Accomplished by recording the required information in individual bits, often call condition code flags. • Grouped together inside condition code register or status register.
- 12. CISC Instruction Sets Condition Codes
- 13. RISC and CISC Styles • RISC and CISC are two different styles of instruction sets. • RISC style is characterized by: • Simple addressing modes and all instruction fitting in a single word. • AL operations are performed in processor registers. • Load/Store architecture. • Fewer instructions in the instruction set, as a consequences of simple addressing modes. • Fast execution by the processing unit using techniques such as pipelining. • Programs larger in size, but more, but simpler instructions are needed to perform complex tasks.
- 14. RISC and CISC Styles • CISC style is characterized by: • More complex addressing modes. • More complex instructions, where an instruction may span multiple words. • Many instructions that implement complex tasks. • AL operations both on memory and register operands. • Single MOV instruction. • Programs smaller in size, but fewer, but more complex instructions are needed to perform complex tasks.
- 15. RISC and CISC Styles • Before the 1970s, all computer were of CISC type. • To simplify the development of software by making the hardware capable of performing justly complex tasks. • To move the complexity from the software level to the hardware level. • Makes the programs simpler and shorter. • Computer memory was smaller and more expensive to provide.
- 16. RISC and CISC Styles • RISC-style designs – High performance by making the hardware simple • Instructions executed in pipelined fashion. • Move complexity from the hardware level to software level. • Sophisticated compilers were developed to optimize the code consisting of simple instructions. • The size of the code became less important as memory capacities increased.
- 17. RISC and CISC Styles • While the RISC and CISC styles are two different approaches • Add some non-RISC instructions to a RISC processor. • To reduce the number of instructions executed, as long as the execution of these new instructions is fast.
- 18. Encoding of Machine Instructions
- 19. Summery • Assembly Language • CISC Instruction Sets • Characteristics of RISC • RISC and CISC Styles • Encoding of Machine Instructions
- 20. Thank You For your Patience
Editor's Notes
- Machine instructions are represented by patterns of 0s and 1s. Such patterns are awkward to deal with when discussing or preparing programs. Therefore, we use symbolic names to represent the patterns.
- None of the locations are overwritten.
- In some CISC processors one operand may be in the memory but the other must be in a register.
- Useful for accessing successive memory location or for stack implementation.
- Operations performed by the processor typically generate results such as numbers that are positive, negative, or zero. The processor can maintain the information about these results for use by subsequent conditional branch instructions.
- Load/store architecture that does not allow direct transfers from one memory location to another; such transfers must take place via a processor register.
- Today, memory is inexpensive and most computers have large amounts of it.
- RISC-style designs emerged as an attempt to achieve very high performance by making the hardware very simple, so that instructions can be executed very quickly in pipelined fashion.
- In this section, we introduced the basic concept of encoding the machine instructions. Different commercial processors have instruction sets that vary in the details of implementation. Appendices B to E present the instruction sets of four processors that we have chosen as examples.