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CSE 490/590 Computer ArchitectureMIPS Review & Pipelining I<br />Steve Ko<br />Computer Sciences and Engineering<br />Univ...
2<br />Last Time…<br />An ISA can have multiple implementations<br />(Briefly) CISC vs. RISC<br />CISC: microcoded (macro ...
3<br />MIPS Instruction Formats<br />Register-Register<br />5<br />6<br />10<br />11<br />31<br />26<br />0<br />15<br />1...
Reg-Reg Instructions<br />Op (e.g., 0) encodes that this is a reg-reg instruction<br />Func encodes the datapath operation...
Reg-Imm Instructions<br />Rd  (Rs1) Op (Imm)<br />ADDI R1,R2,#3<br />Add immediate<br />Regs[R1]  Regs[R2] + 3<br />LD R...
Jump / Call<br />Rd  (Rs1) Op (Imm)<br />J name<br />Jump<br />PC6…31 name<br />JAL name<br />Jump and link<br />Regs[R3...
7<br />Implementing MIPS:Single-cycle per instructiondatapath & control logic<br />
8<br />RegWrite<br />0x4<br />clk<br />Add<br />inst<25:21><br />we<br />inst<20:16><br />rs1<br />rs2<br />addr<br />PC<b...
9<br />RegWrite<br />0x4<br />clk<br />Add<br />we<br />inst<25:21><br />rs1<br />rs2<br />addr<br />rd1<br />PC<br />inst...
10<br />clk<br />we<br />rs1<br />rs2<br />addr<br />rd1<br />PC<br />inst<br />ws<br />ALU<br />wd<br />rd2<br />z<br />I...
11<br />clk<br />we<br />rs1<br />rs2<br />addr<br />rd1<br />PC<br />inst<br />ws<br />ALU<br />wd<br />rd2<br />z<br />I...
12<br />Datapath for Memory Instructions<br />Should program and data memory be separate?<br />Harvard style: separate (Ai...
 Note:</li></ul>Somehow there must be a way to load theprogram memory <br />Princeton style: the same (von Neumann’s influ...
 Note: </li></ul>A Load or Store instruction requires <br />   accessing the memory more than once <br />   during its exe...
13<br />RegWrite<br />MemWrite<br />WBSrc<br />ALU / Mem<br />0x4<br />clk<br />Add<br />we<br />“base”<br />clk<br />rs1<...
14<br />CSE 490/590 Administrivia<br />Please purchase a BASYS2 board (100K) as soon as possible.<br />Projects should be ...
15<br />    6	   5	5 	      16<br />opcode    rs                    offset 		BEQZ, BNEZ<br />    6	  5	5              16<b...
Absolute jumps append target4 to PC<31:28> to calculate the target address: 256 MB range
jump-&-link stores PC+4 into the link register (R31)</li></li></ul><li>16<br />PCSrc<br />br<br />WBSrc<br />MemWrite<br /...
17<br />WBSrc<br />MemWrite<br />rind<br />0x4<br />clk<br />we<br />clk<br />rs1<br />rs2<br />ALU<br />Control<br />we<b...
18<br />0x4<br />clk<br />we<br />rs1<br />rs2<br />ALU<br />Control<br />rd1<br />addr<br />PC<br />ws<br />inst<br />wd<...
19<br />WBSrc<br />MemWrite<br />0x4<br />clk<br />ALU<br />Control<br />we<br />addr<br />PC<br />addr<br />inst<br />ALU...
20<br />WBSrc<br />MemWrite<br />0x4<br />clk<br />we<br />clk<br />rs1<br />rs2<br />ALU<br />Control<br />we<br />rd1<br...
21<br />Single-Cycle Hardwired Control:Harvard architecture<br /> We will assume <br /><ul><li> clock period is sufficient...
22<br />Pipelined MIPS<br />
23<br />stage<br />3<br />stage<br />4<br />stage<br />2<br />stage<br />1<br />An Ideal Pipeline <br /><ul><li> All objec...
 No sharing of resources between any two stages
 Propagation delay through all pipeline stages is equal
 The scheduling of an object entering the pipeline</li></ul>   is not affected by the objects in other stages<br />These c...
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Pipelining1

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Pipelining1

  1. 1. CSE 490/590 Computer ArchitectureMIPS Review & Pipelining I<br />Steve Ko<br />Computer Sciences and Engineering<br />University at Buffalo<br />
  2. 2. 2<br />Last Time…<br />An ISA can have multiple implementations<br />(Briefly) CISC vs. RISC<br />CISC: microcoded (macro instructions & microinstructions)<br />RISC: combinational logic<br />MIPS microarchitecture<br />Good RISC example<br />Fixed format instructions<br />Load/store architecture with single address mode<br />Simple branch<br />Will continue on this today…<br />
  3. 3. 3<br />MIPS Instruction Formats<br />Register-Register<br />5<br />6<br />10<br />11<br />31<br />26<br />0<br />15<br />16<br />20<br />21<br />25<br />Op<br />Rs1<br />Rs2<br />Rd<br />Func<br />Register-Immediate<br />31<br />26<br />0<br />15<br />16<br />20<br />21<br />25<br />immediate<br />Op<br />Rs1<br />Rd<br />Branch (Same format as Reg-Imm)<br />31<br />26<br />0<br />15<br />16<br />20<br />21<br />25<br />immediate<br />Op<br />Rs1<br />Rs2/Opx<br />Jump / Call<br />31<br />26<br />0<br />25<br />target<br />Op<br />
  4. 4. Reg-Reg Instructions<br />Op (e.g., 0) encodes that this is a reg-reg instruction<br />Func encodes the datapath operations (add, sub, etc.)<br />Rd  (Rs1) Func (Rs2)<br />ADD R1,R2,R3<br />Add<br />Reg[R1]  Regs[R2] + Regs[R3]<br />4<br />Register-Register<br />5<br />6<br />10<br />11<br />31<br />26<br />0<br />15<br />16<br />20<br />21<br />25<br />Op<br />Rs1<br />Rs2<br />Rd<br />Func<br />
  5. 5. Reg-Imm Instructions<br />Rd  (Rs1) Op (Imm)<br />ADDI R1,R2,#3<br />Add immediate<br />Regs[R1]  Regs[R2] + 3<br />LD R1,30(R2)<br />Load word<br />Regs[R1]  Mem[30 + Regs[R2]]<br />BEQZ R4, name<br />Branch equal zero<br />If (Regs[R4] == 0) PC  name<br />5<br />Register-Immediate<br />31<br />26<br />0<br />15<br />16<br />20<br />21<br />25<br />immediate<br />Op<br />Rs1<br />Rd<br />
  6. 6. Jump / Call<br />Rd  (Rs1) Op (Imm)<br />J name<br />Jump<br />PC6…31 name<br />JAL name<br />Jump and link<br />Regs[R31]  PC + 4; PC6…31 name<br />6<br />Jump / Call<br />31<br />26<br />0<br />25<br />target<br />Op<br />
  7. 7. 7<br />Implementing MIPS:Single-cycle per instructiondatapath & control logic<br />
  8. 8. 8<br />RegWrite<br />0x4<br />clk<br />Add<br />inst<25:21><br />we<br />inst<20:16><br />rs1<br />rs2<br />addr<br />PC<br />inst<15:11><br />rd1<br />inst<br />ALU<br />ws<br />z<br />wd<br />rd2<br />Inst.<br />Memory<br />clk<br />GPRs<br />inst<5:0><br />ALU<br />Control<br />OpCode<br />6 5 5 5 5 6<br /> 0 rs rt rd 0 func rd  (rs) func (rt)<br />31 26 25 21 20 16 15 11 5 0<br />Datapath: Reg-Reg ALU Instructions<br />RegWrite Timing?<br />
  9. 9. 9<br />RegWrite<br />0x4<br />clk<br />Add<br />we<br />inst<25:21><br />rs1<br />rs2<br />addr<br />rd1<br />PC<br />inst<20:16><br />inst<br />ws<br />ALU<br />wd<br />rd2<br />z<br />Inst.<br />Memory<br />GPRs<br />clk<br />inst<15:0><br />Imm<br />Ext<br />inst<31:26><br />ALU<br />Control<br />ExtSel<br />OpCode<br />6 5 5 16<br />opcode rs rt immediate rt  (rs) op immediate<br />31 26 25 2120 16 15 0<br />Datapath: Reg-Imm ALU Instructions<br />
  10. 10. 10<br />clk<br />we<br />rs1<br />rs2<br />addr<br />rd1<br />PC<br />inst<br />ws<br />ALU<br />wd<br />rd2<br />z<br />Inst.<br />Memory<br />GPRs<br />Imm<br />Ext<br />ExtSel<br />6 5 5 5 5 6<br /> 0 rs rt rd 0 func rd  (rs) func (rt)<br />opcode rs rt immediate rt  (rs) op immediate<br />Conflicts in Merging Datapath<br />RegWrite<br />Introduce<br />muxes<br />0x4<br />Add<br />inst<25:21><br />inst<20:16><br />inst<15:11><br />clk<br />inst<15:0><br />inst<31:26><br />ALU<br />Control<br />inst<5:0><br />OpCode<br />
  11. 11. 11<br />clk<br />we<br />rs1<br />rs2<br />addr<br />rd1<br />PC<br />inst<br />ws<br />ALU<br />wd<br />rd2<br />z<br />Inst.<br />Memory<br />GPRs<br />6 5 5 5 5 6<br /> 0 rs rt rd 0 func rd  (rs) func (rt)<br />opcode rs rt immediate rt  (rs) op immediate<br />Datapath for ALU Instructions<br />RegWrite<br />0x4<br />Add<br /><25:21><br /><20:16><br /><15:11><br />clk<br /><15:0><br />Imm<br />Ext<br /><31:26>, <5:0><br />ALU<br />Control<br />BSrc<br />Reg / Imm<br />ExtSel<br />OpSel<br />RegDst<br />rt / rd<br />OpCode<br />
  12. 12. 12<br />Datapath for Memory Instructions<br />Should program and data memory be separate?<br />Harvard style: separate (Aiken and Mark 1 influence)<br />- read-only program memory<br /><ul><li> read/write data memory
  13. 13. Note:</li></ul>Somehow there must be a way to load theprogram memory <br />Princeton style: the same (von Neumann’s influence)<br /><ul><li> single read/write memory for program and data
  14. 14. Note: </li></ul>A Load or Store instruction requires <br /> accessing the memory more than once <br /> during its execution<br />
  15. 15. 13<br />RegWrite<br />MemWrite<br />WBSrc<br />ALU / Mem<br />0x4<br />clk<br />Add<br />we<br />“base”<br />clk<br />rs1<br />rs2<br />we<br />rd1<br />ws<br />addr<br />ALU<br />addr<br />PC<br />wd<br />rd2<br />z<br />inst<br />GPRs<br />rdata<br />Data <br />Memory<br />clk<br />Inst.<br />Memory<br />disp<br />Imm<br />Ext<br />wdata<br />ALU<br />Control<br />RegDst<br />ExtSel<br />OpCode<br />OpSel<br />BSrc<br /> 6 5 5 16 addressing mode<br />opcode rs rt displacement (rs) + displacement<br />31 26 25 21 20 16 15 0<br />Load/Store Instructions:Harvard Datapath<br />rs is the base register<br />rt is the destination of a Load or the source for a Store<br />
  16. 16. 14<br />CSE 490/590 Administrivia<br />Please purchase a BASYS2 board (100K) as soon as possible.<br />Projects should be done individually.<br />Quiz 1<br />Fri, 2/4<br />Closed book, in-class<br />10%<br />Class cancelled on Fri, 4/15<br />Will update the schedule<br />
  17. 17. 15<br /> 6 5 5 16<br />opcode rs offset BEQZ, BNEZ<br /> 6 5 5 16<br />opcode rs JR, JALR<br /> 6 26<br />opcode target J, JAL<br />MIPS Control Instructions<br />Conditional (on GPR) PC-relative branch<br />Unconditional register-indirect jumps<br />Unconditional absolute jumps<br /><ul><li>PC-relative branches add offset4 to PC+4 to calculate the target address (offset is in words): 128 KB range
  18. 18. Absolute jumps append target4 to PC<31:28> to calculate the target address: 256 MB range
  19. 19. jump-&-link stores PC+4 into the link register (R31)</li></li></ul><li>16<br />PCSrc<br />br<br />WBSrc<br />MemWrite<br />0x4<br />Add<br />clk<br />ALU<br />Control<br />addr<br />we<br />PC<br />inst<br />addr<br />ALU<br />Inst.<br />Memory<br />clk<br />rdata<br />Data <br />Memory<br />Imm<br />Ext<br />wdata<br />Conditional Branches (BEQZ, BNEZ)<br />RegWrite<br />pc+4<br />Add<br />clk<br />we<br />rs1<br />rs2<br />rd1<br />ws<br />wd<br />rd2<br />GPRs<br />z<br />zero?<br />RegDst<br />ExtSel<br />OpCode<br />OpSel<br />BSrc<br />
  20. 20. 17<br />WBSrc<br />MemWrite<br />rind<br />0x4<br />clk<br />we<br />clk<br />rs1<br />rs2<br />ALU<br />Control<br />we<br />rd1<br />addr<br />PC<br />ws<br />addr<br />inst<br />wd<br />rd2<br />ALU<br />GPRs<br />z<br />rdata<br />Inst.<br />Memory<br />clk<br />Data <br />Memory<br />Imm<br />Ext<br />wdata<br />zero?<br />RegDst<br />ExtSel<br />OpCode<br />OpSel<br />BSrc<br />Register-Indirect Jumps (JR)<br />PCSrc<br />RegWrite<br />br<br />pc+4<br />Add<br />Add<br />
  21. 21. 18<br />0x4<br />clk<br />we<br />rs1<br />rs2<br />ALU<br />Control<br />rd1<br />addr<br />PC<br />ws<br />inst<br />wd<br />rd2<br />ALU<br />GPRs<br />z<br />Inst.<br />Memory<br />clk<br />Imm<br />Ext<br />zero?<br />RegDst<br />ExtSel<br />OpCode<br />OpSel<br />BSrc<br />Register-Indirect Jump-&-Link (JALR)<br />PCSrc<br />RegWrite<br />WBSrc<br />MemWrite<br />br<br />rind<br />pc+4<br />Add<br />Add<br />clk<br />31<br />we<br />addr<br />rdata<br />Data <br />Memory<br />wdata<br />
  22. 22. 19<br />WBSrc<br />MemWrite<br />0x4<br />clk<br />ALU<br />Control<br />we<br />addr<br />PC<br />addr<br />inst<br />ALU<br />rdata<br />Inst.<br />Memory<br />clk<br />Data <br />Memory<br />Imm<br />Ext<br />wdata<br />Absolute Jumps (J, JAL)<br />PCSrc<br />RegWrite<br />br<br />rind<br />jabs<br />pc+4<br />Add<br />Add<br />clk<br />we<br />rs1<br />rs2<br />31<br />rd1<br />ws<br />wd<br />rd2<br />GPRs<br />z<br />zero?<br />RegDst<br />ExtSel<br />OpCode<br />OpSel<br />BSrc<br />
  23. 23. 20<br />WBSrc<br />MemWrite<br />0x4<br />clk<br />we<br />clk<br />rs1<br />rs2<br />ALU<br />Control<br />we<br />rd1<br />addr<br />PC<br />ws<br />addr<br />inst<br />wd<br />rd2<br />ALU<br />GPRs<br />z<br />rdata<br />Inst.<br />Memory<br />clk<br />Data <br />Memory<br />Imm<br />Ext<br />wdata<br />zero?<br />RegDst<br />ExtSel<br />OpCode<br />OpSel<br />BSrc<br />Harvard-Style Datapath for MIPS<br />PCSrc<br />RegWrite<br />br<br />rind<br />jabs<br />pc+4<br />Add<br />Add<br />31<br />
  24. 24. 21<br />Single-Cycle Hardwired Control:Harvard architecture<br /> We will assume <br /><ul><li> clock period is sufficiently long for all of </li></ul> the following steps to be “completed”:<br />1. instruction fetch<br />2. decode and register fetch<br />3. ALU operation<br />4. data fetch if required<br />5. register write-back setup time<br /> tC > tIFetch + tRFetch + tALU+ tDMem+ tRWB<br /><ul><li> At the rising edge of the following clock, the PC,</li></ul> the register file and the memory are updated<br />
  25. 25. 22<br />Pipelined MIPS<br />
  26. 26. 23<br />stage<br />3<br />stage<br />4<br />stage<br />2<br />stage<br />1<br />An Ideal Pipeline <br /><ul><li> All objects go through the same stages
  27. 27. No sharing of resources between any two stages
  28. 28. Propagation delay through all pipeline stages is equal
  29. 29. The scheduling of an object entering the pipeline</li></ul> is not affected by the objects in other stages<br />These conditions generally hold for industrial assembly lines. <br />But can an instruction pipeline satisfy the last condition?<br />
  30. 30. 24<br />Pipelined MIPS<br />To pipeline MIPS:<br />First build MIPS without pipelining with CPI=1 <br />Next, add pipeline registers to reduce cycle time while maintaining CPI=1<br />
  31. 31. 25<br />PC<br />IR<br />write<br />-back<br />phase<br />fetch<br />phase<br />execute<br />phase<br />decode & Reg-fetch<br />phase<br />memory<br />phase<br />Pipelined Datapath<br />0x4<br />Add<br />we<br />rs1<br />rs2<br />rd1<br />we<br />addr<br />ws<br />addr<br />rdata<br />ALU<br />wd<br />rd2<br />rdata<br />GPRs<br />Data<br />Memory<br />Inst.<br />Memory<br />Imm<br />Ext<br />wdata<br />Clock period can be reduced by dividing the execution of an instruction into multiple cycles<br /> tC > max {tIM, tRF, tALU, tDM, tRW} ( = tDM probably)<br />However, CPI will increase unless instructions are pipelined<br />
  32. 32. 26<br />“Iron Law” of Processor Performance<br /> Time = Instructions Cycles Time<br /> Program Program * Instruction * Cycle<br /><ul><li>Instructions per program depends on source code, compiler technology, and ISA
  33. 33. Cycles per instructions (CPI) depends upon the ISA and the microarchitecture
  34. 34. Time per cycle depends upon the microarchitecture and the base technology</li></li></ul><li>CPI Examples<br />27<br />Microcoded machine<br />Time<br />7 cycles<br />5 cycles<br />10 cycles<br />Inst 3<br />Inst 1<br />Inst 2<br />3 instructions, 22 cycles, CPI=7.33<br />Unpipelined machine<br />Inst 1<br />Inst 2<br />Inst 3<br />3 instructions, 3 cycles, CPI=1<br />Pipelined machine<br />Inst 1<br />3 instructions, 3 cycles, CPI=1<br />Inst 2<br />Inst 3<br />
  35. 35. 28<br />Technology Assumptions<br /><ul><li>A small amount of very fast memory (caches)</li></ul> backed up by a large, slower memory <br /><ul><li> Fast ALU (at least for integers)
  36. 36. Multiported Register files (slower!)</li></ul>Thus, the following timing assumption is reasonable<br />tIMtRF tALUtDM tRW<br />A 5-stage pipeline will be the focus of our detailed design<br /> - some commercial designs have over 30 pipeline stages to do an integer add!<br />
  37. 37. 29<br />Acknowledgements<br />These slides heavily contain material developed and copyright by<br />KrsteAsanovic (MIT/UCB)<br />David Patterson (UCB)<br />And also by:<br />Arvind (MIT)<br />Joel Emer (Intel/MIT)<br />James Hoe (CMU)<br />John Kubiatowicz (UCB)<br />MIT material derived from course 6.823<br />UCB material derived from course CS252<br />

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