Fpga creating counter with external clock

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Fpga creating counter with external clock

  1. 1. FPGACreating Counter Created by Akhmad Hendriawan hendri@eepis-its.edu
  2. 2. You are free:to Share — to copy, distribute and transmit the workUnder the following conditions:Attribution — You must attribute the work in the manner specified by the authoror licensor (but not in any way that suggests that they endorse you or your useof the work).Noncommercial — You may not use this work for commercial purposes.No Derivative Works — You may not alter, transform, or build upon this work. Created by Akhmad Hendriawan hendri@eepis-its.edu
  3. 3. Design system
  4. 4. Background●I try implement counter seven segmen withinput clock from switch.●Because push button is mechanical then I try toremove bouncing effect with debouncing circuit
  5. 5. Problem and solutionAlthough I succeed to implement my design and upload to bit stream toFPGA but there was warning with warning message “ prescaller may haveexcessive skew”.
  6. 6. My first prescaller with warninglibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;Library UNISIM;use UNISIM.vcomponents.all;entity Prescaller is Port ( clk_i : in STD_LOGIC; psc_out : out STD_LOGIC);end Prescaller;architecture Behavioral of Prescaller issignal clk_r: std_logic_vector(17 downto 0) := (others=>0);beginprocess (clk_i,clk_r)begin if rising_edge(clk_i) then clk_r <= clk_r+1; end if;end process;psc_out<=clk_r(17);end Behavioral;
  7. 7. library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all; Prescaller.vhdLibrary UNISIM;use UNISIM.vcomponents.all;entity Prescaller is Port ( clk_i : in STD_LOGIC; psc_out : out STD_LOGIC);end Prescaller;architecture Behavioral of Prescaller issignal clk_r: std_logic_vector(17 downto 0) := (others=>0);beginprocess (clk_i,clk_r)begin Implement clock buffer to output prescaler solve if rising_edge(clk_i) then warning error. clk_r <= clk_r+1; end if;end process; BUFG_inst : BUFG port map ( O => psc_out, -- Clock buffer output I => clk_r(17) -- Clock buffer input );end Behavioral;
  8. 8. library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity debouncing is Port ( clk_i : in STD_LOGIC; dbin : in STD_LOGIC; dbout : out STD_LOGIC);end debouncing;architecture Behavioral of debouncing issignal Q1, Q2, Q3 : std_logic; Debouncing.vhdbeginA: process(clk_i)begin if (clk_ievent and clk_i = 1) then Q1 <= dbin; Q2 <= Q1; Q3 <= Q2; end if;end process;B: process(clk_i)begin if (clk_ievent and clk_i = 1) then dbout <= Q1 and Q2 and (not Q3); end if;end process;end Behavioral;
  9. 9. library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_unsigned.ALL;entity counterBCD is Port ( clk_i : in STD_LOGIC; bcd_o : out STD_LOGIC_VECTOR (3 downto 0));end counterBCD;architecture Behavioral of counterBCD issignal clk_r: std_logic_vector (3 downto 0) := (others=>0); Counter BCD.vhdbeginprocess (clk_i)begin if rising_edge(clk_i) then if(clk_r < 9) then clk_r<= clk_r+1; else clk_r<= (others => 0); end if; end if;end process;bcd_o <= clk_r;end Behavioral;
  10. 10. library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity decoder is Port ( clk : in STD_LOGIC; bcd : in STD_LOGIC_VECTOR (3 downto 0); segment7 : out STD_LOGIC_VECTOR (6 downto 0));end decoder;architecture Behavioral of decoder isbeginprocess (clk,bcd)begin if (clkevent and clk=1) then Decoder.vhd case bcd is --common anoda gfedcba when "0000"=> segment7 <="0000001"; -- 0 when "0001"=> segment7 <="1001111"; -- 1 when "0010"=> segment7 <="0010010"; -- 2 when "0011"=> segment7 <="0000110"; -- 3 when "0100"=> segment7 <="1001100"; -- 4 when "0101"=> segment7 <="0100100"; -- 5 when "0110"=> segment7 <="0100000"; -- 6 when "0111"=> segment7 <="0001111"; -- 7 when "1000"=> segment7 <="0000000"; -- 8 when "1001"=> segment7 <="0000100"; -- 9 --nothing is displayed when a number more than 9 is given as input. when others=> segment7 <="1111111"; end case; end if;end process;end Behavioral;
  11. 11. library IEEE;use IEEE.STD_LOGIC_1164.ALL; COMPONENT decoder PORT(entity syscnt is clk : IN std_logic; Port ( clk_i : in STD_LOGIC; bcd : IN std_logic_vector(3 downto 0); pb_i : in STD_LOGIC; segment7 : OUT std_logic_vector(6 downto 0) counter_out : out STD_LOGIC_VECTOR (6 downto 0) ); ); END COMPONENT;end syscnt; signal psc_cable: std_logic;architecture Behavioral of syscnt is signal db_cable: std_logic; signal bcd_o_cable: std_logic_vector(3 downto 0); COMPONENT Prescaller PORT( begin clk_i : IN std_logic; psc_out : OUT std_logic Inst_Prescaller: Prescaller PORT MAP( ); clk_i => clk_i, END COMPONENT; psc_out => psc_cable ); COMPONENT debouncing PORT( Inst_debouncing: debouncing PORT MAP( clk_i : IN std_logic; clk_i => psc_cable, dbin : IN std_logic; dbin => pb_i, dbout : OUT std_logic dbout => db_cable ); ); END COMPONENT; Inst_counterBCD: counterBCD PORT MAP( COMPONENT counterBCD clk_i => db_cable , PORT( bcd_o => bcd_o_cable clk_i : IN std_logic; ); bcd_o : OUT std_logic_vector(3 downto 0) ); Inst_decoder: decoder PORT MAP( END COMPONENT; clk => db_cable, bcd => bcd_o_cable, segment7 => counter_out Syscnt.vhd ); end Behavioral;

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