CMOS Ring Oscillator Using Stacking Techniques to Reduce Power Dissipation and Leakage Current

“CMOS Ring Oscillator Using Stacking
Techniques to Reduce Power Dissipation
and Leakage Current”
Thesis submitted in partial fulfillment of the requirement for
the degree of
M. Tech (Electronics and Communication Engineering)
Under the Supervision of
Shweta Dabas
(Assistant professor)
By
Vikas Kumar Sah
(05716412811)
To
University School of Information, Communication &
Technology
Guru Gobind Singh Indraprastha University
Dwarka, Delhi-110078
JUNE 2017

ii
DECLARATION
This is to certify that thesis/Report entitled “CMOS Ring Oscillator Using Stacking
Techniques to Reduce Power Dissipation and Leakage Current” which is
submitted by me in partial fulfillment of the requirement for the award of degree
M.Tech (ECE) in USICT, GGSIP University, Dwarka, Delhi comprises only my
original work and due acknowledgement has been made in the text to all other
material used.
Date: 5th June 2017 Vikas Kumar Sah

iii
Certificate
This is to certify that thesis/Report entitled “CMOS Ring Oscillator Using Stacking
Techniques To Reduce Power Dissipation and Leakage Current” which is
submitted by Vikas Kumar Sah in partial fulfillment of the requirement for the
award of degree M.Tech (ECE) in USICT, GGSIP University, Dwarka, Delhi is a
record of the candidate own work carried out by him under my supervision. The
matter embodied in this thesis is original and has not been submitted for the award of
any other degree.
Date: 5th June 2017 Shweta Dabas
(Asst. professor)

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ACKNOWLEDGEMENT
I would like to express my deep gratitude towards my mentor, Shweta Dabas,
who has given me the constant support, suggestions and help to carry out progress in
doing this Thesis. His method of teaching the minute details helped me to acquire
deep insight into the subject. I also take this opportunity to thank all others who gave
me support for completion of the thesis.
Many thanks to the lovely group mates in VLSI group for sharing their
knowledge and experience in analog IC design. Special thanks to Rahul Kumar and
Arvind for all the technical support.
To my father, for his friendship, guidance and his always present support,
persistence and help with every mean he has at his reach. To my mother, to my sister,
to my brother and all my family, for being always a source of love, support and
encouragement.
Vikas Kumar Sah
M.Tech (ECE)
05716412811

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CONTENT
Declaration ii
Certificate iii
Acknowledgement iv
List of Figure vii
List of Table x
List of Acronyms xi
List of Symbols xiii
Abstract xv
CHAPTER PAGE
1. Introduction 1
1.1 Motivation 1
1.2 Needs of Power Loss 2
1.3 Thesis organization 3
2. Literature Review 5
2.1 Oscillator Principles 5
2.2 Barkhausen Criteria 7
2.3 Types of Oscillators 8
2.3.1 LC Oscillator 10
2.3.2 Oscillator w/o Resonators: Ring Oscillator 11
2.3.3 Oscillator w/o Resonators: Relaxation Oscillator 13
2.4 Important Characteristics of Oscillator and Applications 13
2.5 Theory of CMOS Ring Oscillator 15
2.5.1 Delay Times 17
2.5.2 Single Ended Ring VCO 19

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2.5.3 Differential Loop Ring Oscillator 20
3. CMOS Ring Oscillators 22
3.1 Ring Oscillator Basics 22
3.2 Frequency Domain Analysis 23
3.3 Single-Ended Ring Oscillator 26
3.4 Differential Ring Oscillator 28
4. COMS Ring Oscillator with Stacking Techniques 32
4.1 Stacking Technique 32
4.2 Techniques for Leakage Power Reduction 33
4.3 Proposed Approach 34
4.3.1 Sleepy Stack 36
4.3.2 Stack Approach 37
4.3.3 Sleep Transistor Approach 38
4.3.4 Sleepy Stack Approach 38
4.3.6 Dual Sleep Approach 40
4.3.7 Dual Stack Approach 40
5. Simulation and Results 41
6. Conclusion and Future Scope 68
7. References 70

vii
List of Figures
Figure 2.1: Positive feedback oscillator system modeled in s-domain.
Figure 2.2: Positive feedback system.
Figure 2.3: Resonator tank model.
Figure 2.4: LC oscillator model.
Figure 2.5: Ring Oscillator block model.
Figure 2.6: Relaxation oscillator.
Figure 2.7: Ring oscillator by odd number of inverters.
Figure 2.8: Differential Ring oscillator.
Figure 2.9: Delay Time.
Figure 2.10: Current starved inverter as a delay stage.
Figure 2.11: CMOS ring oscillator by three basic inverters (∆𝑡 𝑑𝑒𝑙𝑎𝑦=3∆𝑡).
Figure 2.12: Single end ring VCO.
Figure 2.13: Differential Ring Oscillator.
Figure 3.1: Amplifier Block - A(s).
Figure 3.2: Ring oscillator linear model.
Figure 3.3: Current starved inverter.
Figure 3.4: (a) Capacitive load control, (b) Resistive load control.
Figure 3.5: Frequency tuning by control of 𝑉𝑑𝑑.
Figure 3.6: 4-Stage differential ring oscillator.
Figure 3.7: Simple differential pair.
Figure 3.8: Differential pair with symmetrical loads.
Figure 3.9: Differential pair with symmetrical loads & amplitude control circuitry.
Figure 4.1: Sleepy Stack Keeper.
Figure 4.2: Sleepy Stack.
Figure 4.3: Stack Method.
Figure 4.4: Sleep Approach. .
Figure 4.5: Sleepy Stack.
Figure 4.6: Sleepy Keeper.
Figure 4.7: Dual Sleep.
Figure 4.8: Dual Stack.

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Figure 5.1: 7 Stage Ring Oscillator.
Figure 5.2: Comparison of Frequency 7 Stage RO at different channel width and
voltages.
Figure 5.3: Comparison of Power of 7 Stage RO at different channel width and
voltages.
Figure 5.4: Waveform of 7 stage Ring Oscillator.
Figure 5.5: 5 stage Ring Oscillator.
Figure 5.6: Comparison of Frequency of 5 Stage RO at different channel width and
voltages.
Figure 5.7: Comparison of Power of 5 Stage RO at different channel width and
voltages.
Figure 5.8: Waveform of 5 stage Ring Oscillator.
Figure 5.9: 5 Stage Stacked Ring Oscillator.
Figure 5.10: Comparison of Frequency of 5 Stage Stacked RO at different channel
width and voltages.
Figure 5.11: Comparison of Power of 5 Stage Stacked RO at different channel width
and voltages.
Figure 5.12: Waveform of 5 Stage Stacked RO.
Figure 5.13: 5 Stage Ring Oscillator Stacked with 3 stage Ring Oscillator (cascade
form of RO).
Figure 5.14: Comparison of Frequency of Cascade RO at different channel width and
Voltages.
Figure 5.15: Comparison of Power of Cascade RO at different channel width and
Voltages.
Figure 5.16: Waveform of cascade RO.
Figure 5.17: 5 Stage Sleepy Stacked Ring Oscillator.
Figure 5.18: Comparison of Frequency of 5 Stage Sleepy Stacked RO at different
channel width and Voltages.

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Figure 5.19: Comparison of power of 5 Stage Sleepy Stacked RO at different channel
width and Voltages.
Figure 5.20: Waveform of 5 Stage Sleepy Stacked RO.
Figure 5.21: 5 Stage Dual Stacked RO.
Figure 5.22: Comparison of Frequency of 5 Stage Dual Stacked RO at different
channel width and voltages.
Figure 5.23: Comparison of Power of 5 Stage Dual Stacked RO at different channel
width and voltages.
Figure 5.24: Waveform of 5 Stage Dual Stacked RO.
Figure 5.25: Comparison of frequency of different RO for 𝑊𝑝=1μm and 𝑊𝑛=0.5μm.
Figure 5.26: Comparison Graph of frequency for 𝑊𝑝 = 0.8𝜇𝑚 and 𝑊𝑛 = 0.4𝜇𝑚.
Figure 5.27: Comparison graph of power of different RO for 𝑊𝑝=1μm and
𝑊𝑛=0.5μm.
Figure 5.28: Comparison Graph of Power of different RO for 𝑊𝑝=0.8μm and
𝑊𝑛=0.4μm.

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List of Tables
Table 5.1: Frequency and power consumption variation of 7 stage RO at different
voltage and channel width.
Table 5.2: Frequency and Power Consumption Variation of 5 Stage RO at different
width and Voltages.
Table 5.3: Frequency and Power Consumption Variation of 5 Stage Stacked RO at
different width and Voltages.
Table 5.4: Frequency and Power consumption variation of 5 stage Stacked with 3
stage RO at different width and voltages.
Table 5.5: Frequency and Power Consumption Variation of 5 Stage Sleepy Stacked
RO at different width and Voltages.
Table 5.6: Frequency and Power Consumption Variation of 5 Stage Dual Stacked RO
at different width and Voltages.
Table 5.7: Comparison table of frequency of different RO for 𝑊𝑝=1μm and
𝑊𝑛=0.5μm.
Table 5.8: Comparison Table of Frequency of different RO for 𝑊𝑝=0.8μm and
𝑊𝑛=0.4μm.
Table 5.9: Comparison Table of Power of different RO for 𝑊𝑝=1μm and 𝑊𝑛 = 0.5μm.
Table 5.10: Comparison Table of Power of different RO for 𝑊𝑝=0.8μm and
𝑊𝑛=0.4μm.

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List of Acronyms
CMOS Complementary Metal Oxide Semiconductor
TSMC Taiwan Semiconductor Manufacturing Company
ULSI Ultra Large-Scale Integration
TIPS Tera Instructions per seconds
VLSI Very Large-Scale Integration
MHz Mega Hertz
GHz Giga Hertz
T Transistor
PLL Phase Locked Loop
VCO Voltage Controlled Oscillator
LC Inductor Capacitor
RF Radio Frequency
PCB Printed Circuit Board
SNR Signal-To-Noise-Ratio
ADC Analog-To-Digital Converters
SCP Source Coupled Pair
DC Direct Current
RO Ring Oscillator
MOS Metal Oxide Semiconductor
VLSI Very Large-Scale Integration

xii
PD Phase Detector
LPF Low Pass Filter
XOR Exclusive OR
ITRS International Technology Roadmap for Semiconductors
DAC Digital to Analog Converter

xiii
List of Symbols
fo Frequency of LC oscillator
Rp Parallel negative resistance
fLC Resonant frequency of LC oscillator
XL Reactance of the inductor
XC Reactance of the capacitor
Td Delay of each stage of oscillator
Toffset Constant offset period
Tstep Period of the quantization step
Tconstant Constant delay of each cell
Ttune Delay tuning range of standard cell
Ceq Equivalent capacitance of DCO
Cj Junction capacitance
∆C Change in capacitance with the application of control bits
Ptotal Total power consumption in any CMOS circuit
α Switching activity
CL Capacitance of the load
Vdd Supply voltage
Vds Drain to source voltage
Vgs Gate to source voltage
f Clock frequency

xiv
Pdynamic Dynamic power dissipation
fclk Switching frequency
Cox Gate oxide capacitance per unit area
Vt Threshold voltage
L Channel length
W Gate width
W/L Width to length ratio of transistors
N Number of delay stages in the ring oscillator
µ Mobility
Vbias Reverse bias voltage across the junction
Isub Subthreshold leakage current
VT Thermal voltage
K Total gain of PLL
H(s) Transfer function of PLL
He(s) Error transfer function of PLL
CG Gate to source capacitance
𝑰 𝒄𝒐𝒏𝒕𝒓𝒐𝒍 Current Control
𝑽 𝒄𝒐𝒏𝒕𝒓𝒐𝒍 Voltage Control

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ABSTRACT
The main objective of this thesis is to analyze CMOS Ring Oscillator and reduce
power dissipation to better results. Especially, this work focuses on analysis of CMOS
ring oscillator and the reduction of the power dissipation, which is showing an ever-
increasing growth with the scaling down of the technologies. Various techniques at
the different levels of the design process have been implemented to reduce the power
dissipation at the circuit, architectural and system level.
Furthermore, the number of gates per chip area is constantly increasing, while the gate
switching energy does not decrease at the same rate, so the power dissipation rises
and heat removal becomes more difficult and expensive. Then, to limit the power
dissipation, alternative solutions at each level of abstraction are proposed.
Power and Delay are the two significant parameters which defines the circuit
performance. Our main concern in this thesis is to reduce the power and delay of
CMOS ring oscillator. The dynamic power requirement of CMOS circuits is rapidly
becoming a major concern in the design of personal information systems and large
computers. This thesis also includes the comparison of CMOS ring oscillator made up
of different number of transistors.
All the circuits are implemented on PYXIS TOOL (MENTOR GRAPHICS) using
standard TSMC 18nm technology. Respective graphs have also been plotted for
Power Dissipation, Delay and Power Delay Product.

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CHAPTER I
INTRODUCTION
CMOS ring oscillator can be designed using different number of transistors i.e. 10T,
14T, 16T, 20T, 30T, and 40T. In this thesis, all these ring oscillators have been designed
and simulated on PYXIS TOOL MENTOR GRAPHICS using standard TSMC 18nm
technology. Analysis and comparison of all CMOS ring oscillator have been done by
plotting graphs for Power, Delay and Power Delay Product. To reduce power
dissipation and delay a new technique called STACKING TECHNIQUES has been
implemented.
1.1 Motivation
In the past few decades ago, the electronics industry has been experiencing an
unprecedented spurt in growth, thanks to the use of integrated circuits in computing,
telecommunications and consumer electronics. We have come a long way from the
single transistor era in 1958 to the present day ULSI (Ultra Large-Scale Integration)
systems with more than 50 million transistors in a single chip [1].
The ever-growing number of transistors integrated on a chip and the increasing
transistor switching speed in recent decades has enabled great performance
improvement in computer systems by several orders of magnitude. Unfortunately, such
phenomenal performance improvements have been accompanied by an increase in
power and energy dissipation of the systems. Higher power and energy dissipation in
high performance systems require more expensive packaging and cooling technologies,
increase cost, and decrease system reliability. Nonetheless, the level of on-chip
integration and clock frequency will continue to grow with increasing performance
demands, and the power and energy dissipation of high-performance systems will be a
critical design constraint.
For example, high-end microprocessors in 2010 are predicted to employ billions of
transistors at clock rates over 30GHz to achieve TIPS (Tera Instructions per seconds)

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performance [1]. With this rate, high-end microprocessor’s power dissipation is
projected to reach thousands of Watts. This thesis investigates one of the major sources
of the power/energy dissipation and proposes and evaluates the techniques to reduce
the dissipation.
Digital CMOS integrated circuits have been the driving force behind VLSI for high
performance computing and other applications, related to science and technology. The
demand for digital CMOS integrated circuits will continue to increase soon, due to its
important salient features like low power, reliable performance and improvements in
the processing technology.
1.2 Need for Low Power Design
There are various interpretations of the Moore’s Law that predicts the growth rate of
integrated circuits. One estimate places the rate at 2X for every eighteen months. Others
claim that the device density increases ten-fold every seven years. Regardless of the
exact numbers, everyone agrees that the growth rate is rapid with no signs of slowing
down. New generations of processing technology are being developed while present
generation devices are at very safe distance from the fundamental physical limits. A
need for low power VLSI chips arises from such evolution forces of integrated circuits.
The Intel 4004 microprocessor, developed in 1971, had 2300 transistors, dissipated
about 1 watts of power and clocked at 1 MHz Then comes the Pentium in 2001, with
42 million transistors, dissipating around 65 watts of power and clocked at 2.40 GHz
[1]. While the power dissipation increases linearly as the years go by, the power density
increases exponentially, because of the ever-shrinking size of the integrated circuits. If
this exponential rise in the power density were to increase continuously, a
microprocessor designed a few years later, would have the same power as that of the
nuclear reactor.
Such high power density introduces reliability concerns such as, electro migration,
thermal stresses and hot carrier induced device degradation, resulting in the loss of
performance. Another factor that fuels the need for low power chips is the increased
market demand for portable consumer electronics powered by batteries. The craving
for smaller, lighter and more durable electronic products indirectly translates to low

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power requirements. Battery life is becoming a product differentiator in many portable
systems.
Being the heaviest and biggest component in many portable systems, batteries have not
experienced the similar rapid density growth compared to the electronic circuits. The
main source of power dissipation in these high-performance battery-portable digital
systems running on batteries such as note-book computers, cellular phones and personal
digital assistants are gaining prominence. For these systems, low power consumption
is a prime concern, because it directly affects the performance by having effects on
battery longevity. In this situation, low power VLSI design has assumed great
importance as an active and rapidly developing field.
Another major demand for low power chips and systems comes from the environmental
concerns. Modern offices are now furnished with office automation equipment that
consume large amount of power. A study by American Council for an Energy-Efficient
Economy estimated that office equipment account for 5% for the total US commercial
energy usage in 1997 and could rise to 10% by the year 2004 if no actions are taken to
prevent the trend [2].
1.3 Thesis Organization
The primary goal of this thesis is to analyze the CMOS Ring Oscillator and demonstrate
a circuit level design approach, for use in designs which demand extreme low power
dissipation.
This thesis is organized as follows:
CHAPTER I: INTRODUCTION. This chapter introduces power consumption issues
in VLSI. This chapter also summarizes the need of low power design in the today’s era
of scaling down of technologies and nanotechnology. Finally, this thesis chapter
explains organization of the thesis.
CHAPTER II: LITERATURE REVIEW. This chapter briefly explains CMOS Ring
Oscillator made up different number of transistors. It also explains the principle of

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stacking technique that emerges as a new approach to low power VLSI design. It also
introduces different sources of power dissipation that occur in CMOS digital circuits
and the different techniques of reducing power dissipation in CMOS Ring Oscillator
circuits.
CHAPTER III: CMOS RING OSCILLATOR. This chapter explains the CMOS
Ring Oscillator made up of different number of transistors. It analyses CMOS Ring
Oscillator configurations made up of different number of transistors i.e. 10T, 14T, 16T,
20T, 30T, and 40T. It also includes simulations and graphs depicting analysis based of
Power, Delay and Power Delay Product.
CHAPTER VI: LOW POWER CMOS RING OSCILLTOR WITH STACKING
TECHNIQUE. This chapter gives the design of CMOS Ring Oscillator using stacking
technique, which gives low power dissipation and better response.
CHAPTER V: SIMULATION AND RESULTS. This chapter gives the design of
experimental CMOS RO’s and the comparison Tables and the Graphs and compare the
power consumptions with the different types of Ring Oscillator.
CHAPTER VI: CONCLUSION AND FUTURE SCOPE. This chapter summarizes
the major accomplishments of this thesis and presents the scope for future and further
research.

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CHAPTER II
LITERATURE REVIEW
2.1 Oscillator Principles
Oscillators are usually characterized by using linear analysis technique. This approach
is common although they are highly nonlinear feedback systems. The resulting
frequency-domain (or s-domain) analysis cannot yield the exact response.
Nevertheless, frequency-domain analysis techniques are applied to the oscillator to gain
insight about the oscillator and they work particularly well for oscillator using analog
gain stages. Linear system-analysis proves to be a reasonable first-order approximation
for most cases.
An oscillator is a system employing positive feedback. As shown in figure 2.1, it is
constructed from an amplifier block and a frequency-selection network connected in a
positive-feedback loop. Although an actual oscillator does not have an input X(s) to
drive the oscillator as shown in figure 2.1, the assumption of this input signal simplifies
the s-domain analysis of the feedback loop. A simple analysis of this system shows that
the transfer function can be written as[3]
H(s) =
X(s)
Y(s)
=
A(s)
1−A(s)α(s)
(2.1)
Where A(s) is the s-domain function of the amplifier block, and 𝛼(𝑠) is the s-domain
transfer function of the frequency of the frequency-selective network. Let us define
the loop gain L(s) as
L(s) = A(s)𝛼(𝑠) (2.2)
Where L(s) is simply the open loop gain of the loop.

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Figure 2.1: Positive feedback oscillator system modeled in s-domain
According to the standard oscillator definition, this system must have a finite output
even in the absence of an input signal. From the above equations, it is easily seen that
this condition occurs if the transfer function converges to infinity at a specific
frequency, implies at the loop gain L(s) should be equal to one at this frequency. Thus,
the magnitude of the loop gain should be equal to unity and the phase of the loop gain
should be an integer multiple of 2π for the feedback loop to provide stable oscillator.
This condition is called the Barkhausen criterion. Note that this criterion only
guarantees that the oscillator will be sustained after it starts but it does not guarantee
that the oscillator will start. Practically, the magnitude of the loop gain should be
designed to be slightly larger than the unity for the oscillation to start. This suggests
that because of the positive feedback, any possible oscillation will grow indefinitely
unless there is a nonlinear mechanism to stop the growth of the signals. Older design
uses nonlinear amplitude control circuitry to achieve this but modern integrated
oscillator designs usually rely on the hard-limiting of the power supplies and the gain
drop of FETs at large signal level. Physically, any internal noise in the system at the
specific oscillator frequency will be amplified by the help of the positive feedback gain,
resulting in a periodic signal at the output. The gain of the feedback will then drop to
unity as the signals get larger because of the amplitude limiting mechanism to yield a
steady-state oscillatory signal. The gain of the loop function determines if the oscillator

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will start or not but it is the phase characteristics of the feedback loop that determines
the oscillation frequency. From the previous discussion, the feedback system oscillates
when the phase is zero or an integer multiple of 2π. Large values of dφ(ω)/dω
indicates an oscillator with a stable output frequency since any change in loop phase,
which can occur due to a slight variance in one of the circuit parameters or temperature,
will correspond to less disturbance at frequency and vice-versa [4]. The relation of this
simple statement with the Q-factor of an oscillator will be discussed in the following
chapters.
2.2 Barkhausen Criteria
The VCO is a nonlinear larger signal feedback system, so it is very difficult to get the
exact analysis of the VCO. However, we can still use the small signal model to do some
study. Based on the first order approximation, how the VCO works can be explained
and how to improve the VCO frequency tuning range can also be studied. Therefore, it
is necessary to give the general small signal model first. The VCO is a positive feedback
system, shown as Figure 2.2, and it is built by the delay cell or amplifier block. The
VCO must be a positive feedback system, because the delay cell or amplifier block has
to have too much phase shift at a certain frequency to make the oscillation start. In other
words, the noise signal will be amplified and accumulated on the input signal again;
then the oscillation will start. If the phase shift is not enough, the system will become
an amplifier[5].
Figure 2.2: Positive feedback system

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From Figure 2.2, the transfer function of the VCO can be written as:
H(s)=
𝐕 𝐨𝐮𝐭
𝐕𝐢𝐧
=
𝐀(𝐬)
𝟏−𝛃𝐀(𝐬)
(2.3)
In some cases, even if the phase shift is enough, the oscillation cannot start, since the
gain of the amplifier block is too small. If the gain is less than 1, the positive feedback
system will also latch up to the power supply rather than oscillation.
There is a theory named “Barkhausen Criteria” to describe the conditions needed to
make oscillation. The Barkhausen Criteria can be summarized as follow:
1. The gain of the amplifier block of VCO must equal more than 1 as:
|𝐴(𝑠)| ≥ 1 (2.4)
2. The phase shift of the amplifier block must equal to 3600
as:
A(s) = 3600
(2.5)
In most situations, even the gain of the amplifier block is equal to 1, so the oscillation
still does not start or is not stable. Generally, the VCO designer makes the gain as large
as possible and CMOS technology can easily obtain this. Also, the Barkhausen Criteria
is the necessary conditions for the oscillation, but is not sufficient[6].
2.3 Types of Oscillators
Integrated VCOs for high-frequency communications applications can be implemented
using ring architectures, relaxation circuits, or LC based networks. Among these, LC
oscillators have the best phase-noise and frequency performance because of their use
of passive resonant elements with high quality Q factors[4-5]. LC oscillators have been
constructed using bonding wires, integrated inductors, or external inductors. Using

9
external parts, however, raises the cost of the system and introduces other problems
such as increased parasitic levels and increased power dissipation; therefore, fully
monolithic designs are highly desirable. There are other problems related with the
utilization of bonding wires as the high Q inductor of the LC oscillator such as the lack
of accurate control of the inductance value. In state-of-the-art CMOS processing, it is
possible to fabricate integrated inductors with high quality factors (Q ~ 85 [7]). They
can be implemented monolithically at the expense of adding processing steps that
significantly increase the cost and the complexity of the system. Micro-Electro-
Mechanical-Systems (MEMS) designers, for example, use various etching techniques
to obtain high-performance monolithic inductors. Addition of inductors to a CMOS
process also introduces problems such as the control of eddy currents in the substrate
and magnetic coupling.
Ring oscillators, on the other hand, are suitable for monolithic system design using any
digital CMOS fabrication process. Ring designs may require less die area when
compared to the LC counterparts because of the lack of area-consuming passive
elements (inductors and varactors). In addition, the design of ring oscillators is
straightforward using integrated circuit design techniques. Other properties of ring
oscillators, such as the availability of multiple phases at the output and the wide tuning
range can be useful for some specific applications including frequency synthesizers and
oversampling circuits. These characteristics of ring oscillators lead to the conclusion
that they are still important in modern integrated communications systems. As implied
above, the noise performance of a ring oscillator is generally worse than LC oscillators
because of the low-quality factor Q of the ring structure [7, 8]. However, by using
different ring architectures and circuit techniques, it is possible to achieve frequencies
and noise levels comparable to LC designs.
The final candidate for the high frequency integrated VCO design is the relaxation
oscillator. A relaxation oscillator employs the same elements as a ring oscillator with-
out the need for high-quality inductors. The only difference is the use of an additional
capacitive element. This contrasts with high-speed ring oscillator designs, which utilize
the capacitive parasitic of the metal-oxide-semiconductor (MOS) transistors. Only a
few CMOS relaxation oscillator designs have been published, with the fastest running
at 900 MHz [9]. They also do not match the noise performance of LC and ring
oscillators because of their relatively low effective quality Q factor.

10
Figure 2.3: Resonator Tank Model
2.3.1 LC Oscillators
The core of an LC oscillator is a resonator tank that is constructed from on-chip
inductors and varactors. This tank performs as the frequency-selective network that was
shown in the oscillator model of Figure 2.1. As shown in Figure 2.3, the resonator tank
can be simply modelled as a parallel connected LC network along with the series
parasitic resistance R, of the inductor. As discussed before, the tank might have a very
high-quality Q factor; however, the tank, alone, is not sufficient for steady oscillations
because of the energy loss on the parasitic. After excitation, the resonator will only
oscillate for approximately Q many cycles until all the stored energy is dissipated on
the R, unless the energy loss is accompanied for. Therefore, every LC oscillator
employs an active circuitry that cancels the parasitic resistance with its negative
effective resistance by providing the required energy at every cycle. This active
circuitry is shown as the —R component in the oscillator model of Figure 2.4. The
frequency of the LC oscillator is strictly determined only by the characteristics of the
resonator, that is 𝜔𝑟 = (√ 𝐿 𝑒𝑞 𝐶𝑒𝑞), and ideally is not effected by the active circuitry
if the capacitive loading of the —R element is ignored.

11
2.3.2 Oscillators w/o Resonators: Ring Oscillators
It is interesting to note that although the oscillator model in Figure 2.1 contains an
amplifier and a frequency-selective network, it is possible to build an oscillator that
Figure 2.4: LC oscillator model
Figure 2.5: Ring Oscillator block model
satisfy the Barkhausen criterion without any resonator. As illustrated in Figure 2.5, a
ring oscillator is the most widely used type that does not contain a frequency-selective
structure. The lack of a High-Q resonator makes it harder to obtain sufficient noise and
frequency performance especially for high-frequency RF applications. Nevertheless,
ring oscillators are extensively used in communications systems due to their simplicity

12
and ease of implementation. Furthermore, various optimization and circuit design
techniques are available to boost their performance close to their LC counterparts.
A basic ring oscillator consists of an odd number N of inverter stages connected in a
positive feedback loop. Therefore, there are an odd number of inversions in the loop. If
one of the nodes is excited, the pulse will propagate through all the stages and will
reverse the polarity of the initially excited node. The frequency of the oscillation will
be 1/ (2* N * Td) where Td is the propagation delay of a single stage. Ring oscillators
will be discussed extensively in the following chapters.
Figure 2.6: Relaxation oscillator
2.3.3 Oscillators w/o Resonators: Relaxation Oscillators
The other type of oscillator that lacks a frequency-selective network is the relaxation
oscillator. The operation of a relaxation oscillator is like that of a multivibrator. In each

13
cycle, a capacitor is charged by an active element, a transistor most of the time, until a
predetermined threshold is exceeded to trigger an event which quickly discharges the
capacitor. After returning to the initial state, this cycle is repeated to yield a steady state
oscillation. Schematics of an example integrated design is shown in Figure 2.6[8].
Relaxation oscillators can be built in a standard CMOS process with less complexity
even when compared to ring oscillators due to the single-stage design. At high
frequencies, however, they are harder to stabilize due to diminishing hysteresis, which
is required for a stable oscillation. They also do not match the noise performance of LC
and ring oscillators because of their relatively low effective quality Q factor [8].
2.4 Important Characteristics of Oscillators and Applications
The important characteristics of an oscillator strongly depend on the application.
Multiple-GHz RF communications systems, for example, are probably the most
demanding of all applications. Because of the extremely lossy transmission media (air),
the receiver circuitry is required to have exceptionally low noise levels to reduce the
BER of the received signal. The design of data/clock recovery networks or frequency
synthesizers employing PLLs, therefore, is very challenging in RF applications. LC
oscillators are most widely used in these systems because of their low noise
characteristics although some ring designs come close to challenging LC counterparts
at lower frequencies [9-10].
Most systems requiring a high-frequency VCO, on the other hand, have more relaxed
noise requirements. When the transmission media is closer to being ideal, such as in
fiber-optical data transmission systems including local area network transceivers and
DSL transceivers, noise specifications may ease a bit [11]. Clock generators, which are
used to supply the timing information to microprocessors, digital signal processing
systems, and dynamic random-access memory arrays, do not have such strict noise
specifications and modern ring oscillator designs are usually sufficient for these
applications. Zero delay clock buffers usually employ PLLs with ring oscillators for
synchronizing the timing of circuits at different parts of the chip or the printed circuit
board (PCB) reducing clock skew and timing errors.

14
Maximum frequency required from an oscillator depends on the data transmission
and/or data processing rate specifications of the system. Design of higher frequency
systems are more challenging due to many reasons. First, the switching capability of a
transistor is limited by the characteristics of the fabrication process. Maximum
switching speed is usually limited to approximately 1/5 of the transistor 𝑓𝑡(unity gain
frequency) of the process. In a standard 0.25 pm CMOS technology, for example, 𝑓𝑡 is
approximately 25 GHz. An LC oscillator's center frequency appears to depend only on
the inductance and the capacitor values such that reducing them would increase the
frequency. The maximum frequency, however, cannot be indefinitely increased due to
the reduction of the self-resonance frequency of the inductor and the parasitic
capacitances. Furthermore, other specifications of the oscillator get more stringent
when operation frequency is increased. Noise requirement of the system is an example.
With increasing data transfer speeds, the clock periods become shorter, decreasing the
amount of absolute timing uncertainty (jitter) that can be tolerated at the output. Finally,
there are other problems related with the design of systems when operation frequencies
exceed a few GHz such as the skin effect or the increased bulk-node currents. Power
dissipation of a system is directly dependent upon the data transmission and/or
processing rate of the system. That is, a faster system dissipates more power which can
be seen from the dynamic power dissipation equation [12]
𝑃 = 𝑉𝑝
2
𝐶𝐿 𝑓 (2.6)
Where P is the power that is dissipated on a node with capacitance of 𝐶𝐿, oscillating at
a frequency off with a peak voltage amplitude of 𝑉𝑝. Power dissipation may not be
significantly important if the system does not depend on batteries to operate, i.e. if it is
not mobile. Even for such cases, extreme power dissipation is not desired because of
the problems related with the increase in temperature of the system due to high power
dissipation. Noise characteristics of a circuit also depend on the maximum available
power. Larger signal levels correspond to better signal-to-noise-ratio (SNR) improving
the phase noise of the oscillator.
Stability of the system under parameter variations is another important issue. The output
parameters of the system should stay inside the specifications when the temperature of
the system is varied as specified. Changes due to fabrication parameter variations are

15
really an issue of yield and must be minimized to increase the yield, which in turn
reduces the cost. Military rated products are the most demanding ones in that sense
requiring the circuit to operate at extreme conditions.
Other than these major issues, there are some other desirable properties of oscillators
in some specific applications. Analog-to-digital converters (ADC) or oversampling
networks, for example, benefit from multiple output phases of the clock generator.
Some of these networks use sampling circuitry with multiple clock inputs, each
individually triggering the sampling event at signal transitions, to multiply the sampling
rate by the number of available phases. Multiple phases are naturally available from
ring oscillators although a couple of ring LC designs were published in the literature
[12, 13] to supply multiple phases. Tuning range of an oscillator is another
characteristic that needs close attention. Narrow tuning range may create problems in
meeting the frequency specification with a single fabrication run, and multiple
iterations may be necessary. On the other hand, wide tuning range increases the gain of
the VCO resulting in a higher sensitivity to control line noise. Therefore, the tuning
range of a VCO should be optimized according to the specifications of the application.
Generally ring oscillators have much wider tuning range than their LC counterparts
although there are different design techniques available to implement wide tuning range
LC oscillators (digital tuning and analog tuning applied together) [14].
2.5 Theory of CMOS Ring Oscillator
CMOS Ring voltage controlled oscillator with combined delay stages is presented.
Initially the general condition of oscillators is discussed then two common inverters are
introduced and their delay times are calculated parametrically. Our analysis and
parametrically calculations states that delay time of basic type inverter changes in
opposite direction compared with current starved inverter versus supply voltage
changing, so a combined schematic can be used to obtain better frequency stability.
CMOS VCO reduced the oscillation frequency dependence to supply voltage
considerably and is appropriate for On-Chip applications since no passive element is
used.

16
Voltage control oscillator (VCO) is one of the most significant part of any digital and
analog systems. While there are several structures for design of oscillators, one of the
most common structures is the ring oscillators which can be used as clock in systems.
The most significant advantage of full transistor oscillator is the issue that this type of
oscillator is compatible with integration and there is no passive element such as
capacitor or inductor. This feature is important since die area in CMOS technology is a
really important factor and full transistor circuits occupy less area in chip. This paper
initially discusses the general condition for oscillation then parametrically calculates
the delay time of two common inverters. Then shows that a combined configuration for
CMOS ring oscillator is more stable regarding oscillation frequency versus supply
voltage variation. In fact, the combined structure has less frequency deviation with
noisy supply voltages. In addition, simulation results verify the analysis findings. A
ring oscillator is made of some delay stages. An oscillator can be designed by odd
number of single-input single-output delay stages or by even number of differential
delay stages. Based on Barkhausen criteria every stage should add 180/N phase to the
signal (or reduce) and the other 180° provided by the sign of inverters (N; number of
stages are odd). You can have an oscillator with even numbers of delay stages by use
of differential configuration with connections based on Fig.
Figure 2.7: Ring oscillator by odd number of inverters
Figure 2.8: Differential Ring oscillator

17
𝐴1(𝑗𝜔) = 𝐴2(𝑗𝜔) =. . . = 𝐴 𝑁(𝑗𝜔) =
−𝑔 𝑚 𝑅
1+𝑗𝜔𝑅𝐶
(2.7)
|𝐴1(𝑗𝜔) = 𝐴2(𝑗𝜔) =. . . = 𝐴 𝑁(𝑗𝜔)| = 1 (2.8)
2.5.1 Delay Times
To design a ring oscillator according to structure in previous section, we should use
inverters as delay stages. Regarding the delay time as the most important parameter in
this kind of oscillator we should better calculate the delay time of stages. With the
assumption of two inverters, basic type and current starved inverters and we have
calculated the delay times for these inverters with the aim of Fig. This figure shows the
ideal input and typical out puts for inverters. Let’s assume that delay time is
proportional to 𝑡2−𝑡0 so its need to calculate 𝑡2 − 𝑡0as delay time. So, we have for basic
inverter.
Figure 2.9 Delay Time

18
𝑡 𝑑𝑒𝑙𝑎𝑦 ∝ 𝑡2 − 𝑡0 = (𝑡2 − 𝑡1) + (𝑡1 − 𝑡0) (2.9)
Figure 2.10 Current starved inverter as a delay stage
The gate voltage of M1 and M2 supplied through circuit bias and there is no dependency
between this voltage and input or output. This voltage is determined by the current of
M5 and M6, which 𝑉 𝑐𝑡𝑟𝑙 controls this current. [𝑡0<t<𝑡1 𝑉𝑖𝑛=𝑉𝑑𝑑&𝑉𝑜𝑢𝑡 = [𝑉𝑑𝑑,𝑉𝑑 − 𝑉𝑡].
M3saturation, M1saturation &M4cut off
Here, the current is determined by M1 but not M3. This is because current flow through
M1 is determined by the current mirror formed by M1-M5 and is independent of the
gate-source voltage of M3

19
Figure 2.11: CMOS ring oscillator by three basic inverters (∆𝒕 𝒅𝒆𝒍𝒂𝒚=3∆𝒕)
2.5.2 Single Ended Ring VCO
The ring oscillator is basically a closed loop comprised of an odd number of identical
inverters, which form an unstable negative feedback circuit. The period of oscillation
is twice the sum of gate delays in ring comprises inverters. A voltage control ring
oscillator CMOS inverter first used for clock recovery in an Ethernet controller. Since
then ring oscillator widely used in wireless devices. A simple ring oscillator is just an
inverter chain in odd number, to make negative feedback we use a buffer to make
number of stages even. So that the feedback helps in oscillation. The figure Show single
end VCO.
Figure 2.12: Single end ring VCO

20
2.5.3 Differential Loop Ring Oscillator
The differential oscillator has output to reject common-mode noise, power supply
noise. The CMOS used in differential form. Figure 2.11 show the ring oscillator with 3
stage ring oscillators with differential cell. A simple ring oscillator is just differential
inverter chain in odd number, to make negative feedback we use a buffer to make
number of stages even. So that the feedback helps in oscillation. There are many
features that differentiate the delay cell used in ring oscillator. The most important is
slew time that determines the overall phase noise performance. There are three
categories of delay cell. First is fast slewing saturated delay cell.
Figure 2.13: Differential Ring Oscillator

21
This delay cell has fast rise and fall time. It also performs full switching and therefore
belongs to the saturated class of delay cell. The second type of delay cell is a slow
slewing saturated delay cell. Here the inverter consists of a source of a source coupled
pair (SCP) and hence this is a current based inverter. It is called slow slewing because
it has a longer gate delay. The third type of delay cell is non-saturated delay cell. This
is also a voltage inverter based delay cell. In this delay cell, some transistors are never
on/off as a result output waveform never reach 𝑉𝑑𝑑 or ground, which is why this type
of delay cell is called none saturated[15].

22
CHAPTER III
CMOS RING OSCILLATORS
3.1 Ring Oscillator Basics
As discussed in the previous chapter, the Barkhausen criterion for oscillation can be
satisfied with a positive feedback loop that does not contain any frequency-selective
elements. Referring to the oscillator model of the previous chapter, a ring oscillator can
be constructed by closing the feedback loop around an amplifier block while an LC
oscillator needs both the amplifier block and the frequency-selective network to operate
properly. A ring oscillator is realized by connecting several amplification stages in
series, as shown in Figure 3.1. Then, the loop is closed by connecting the output of the
last element to the input of the first element forming the positive feedback[16].
The most basic ring oscillator employs single-ended inverters in place of the
amplification stages. In this case, an odd number N of inverter stages is needed for
steady oscillations. Otherwise the oscillator latches up at a DC level which corresponds
to the satisfaction of Barkhausen criterion at zero frequency. From another perspective,
an odd number of stages will oscillate because if one of the nodes is excited, the pulse
Figure 3.1: Amplifier Block - A(s)
Will propagate through all the stages and will reverse the polarity of the initially excited
node starting the oscillations. On the other hand, for an even number of stages, the pulse

23
will still propagate through the stages but will not reverse the polarity of the initial node.
In the previous chapter, it was already implied that the frequency of the oscillation will
be 1 (2 ∗ 𝑁 ∗ 𝑇𝑑)⁄ where Td the propagation delay[16-17].
3.2 Frequency Domain Analysis
This discussion, however, does not tell anything about the oscillation criteria of ring
oscillators when different types of stages are used or when a differential architecture is
utilized. Therefore, let us generalize this discussion to ring oscillators with gain stages
that can be characterized by a transfer function. In this case, we can define the loop gain
L(s) as:
L(s) = 𝐴1(𝑠)𝐴2(𝑠)𝐴3(𝑠) … … 𝐴 𝑁(𝑠) (3.1)
Where𝐴1(𝑠), 𝐴2(𝑠), 𝐴3(𝑠), and 𝐴 𝑁(𝑠)are the s-domain transfer functions of individual
delay stages. For most practical applications, the gain stages are identical so that the
loop gain reduces to
L(s) = 𝐴 𝑁
(𝑠) (3.2)
Where N is the number of stages, and A(s) = 𝐴1(s) = 𝐴22(s) = 𝐴3(s) = 𝐴 𝑁(s).
According to the Barkhausen criterion, the total phase difference should be
equal to a multiple of 2𝜋 and the magnitude of the loop function should be equal to one.
This implies that a single stage should be able to provide a phase shift of 2k𝜋/N at the
unity gain frequency, where k is an integer. Therefore, the oscillation criterion can be
alternatively written as:
𝐴(𝑗𝜔0) = 2ҟ𝜋 𝑁⁄ and (3.3)
|𝐴(𝑗𝜔0)|
𝑁
= 1 (3.4)

24
Figure 3.2: Ring oscillator linear model
for ring oscillators at the oscillation frequency. If the ring oscillator stages are replaced
with their linear equivalents, i.e. small-signal equivalents that consists of a negative
trans conductance and an RC load, the simple ring loop can be redrawn as given in
Figure 3.1. In this model, every stage has a phase shift of (𝜋 +𝜃) as shown on the figure,
𝜋 coming from the DC inversion and 𝜃 from the RC load delay. To satisfy the
oscillation criteria, the total phase shift around the loop must be equal to a multiple of
2π, with Nπ of this supplied by the odd number of inversions in the loop. The general
practice is to minimize the required phase shift to reduce the number of the required
stages and, therefore, the total phase shift of the RC delays should be equal to ±π. Now,
𝜃 can be written as:
𝜃 = ±
𝜋
𝑁
(3.5)
Next, using this phase relationship among the stages, oscillation frequency can be found
after a simple derivation. From the given linear model, the transfer function of a single
stage can be written as:
𝐴𝑗𝜔 = [
−𝑔 𝑚 𝑅
1+𝑅𝐶 𝑗𝜔
] (3.6)
At the oscillation frequency, phase of this transfer function is:
𝐴𝑗𝜔0
= −𝑡𝑎𝑛−1
(𝑅𝐶 𝜔0
) ± 𝜋 (3.7)
Note that, because of the phase criteria that was found above, we also have 𝐴𝑗𝜔0
=
−(𝜋 + 𝜃). Equating these two relations, we can get

25
𝑡𝑎𝑛−1
(𝑅𝐶 𝜔0
) = 𝜃 (3.8)
and finally, the oscillation frequency can be found as:
𝜔0 =
tan(𝜃)
𝑅𝐶
(3.9)
This reduces to √3 /RC for a three-stage ring and 1/RC for a four-stage one.
Phase requirement is automatically satisfied for different ring loops because of the
connections in the loop, if the structure oscillates. However, the gain requirement as
given in Equation should also be satisfied. By replacing |𝐴𝑗𝜔0
|with (𝑔 𝑚 𝑅)/
(√1 + (𝑅𝐶𝜔0)2)the gain requirement can be written as:
[
𝑔 𝑚 𝑅
√1+(𝑅𝐶 𝜔0)2
] 𝑁
=1 (3.10)
By substituting 𝑅𝐶 𝜔0
with 𝑡𝑎𝑛𝜃using the frequency relationship found above, this can
be reduced to
(𝑔 𝑚 𝑅) 𝑁
=
1
𝑐𝑜𝑠 𝑁 𝜃
(3.11)
Since gm, R, and cos° are positive identities as defined before, we can cancel the
𝑁 𝑡ℎ
exponents and simplify this argument as:
(𝑔 𝑚 𝑅) ≥
1
𝑐𝑜𝑠 𝑁 𝜃
, (3.12)
Remembering that the gain should at least be equal to one at the oscillation frequency.
Therefore, the gain requirement of a three-stage loop is 𝑔 𝑚R ≥2, whereas the
requirement is 𝑔 𝑚 𝑅 ≥ √2 for a four-stage one. This equation shows that it is easier to
satisfy the criteria for longer chains because each stage is required to have a smaller
gain at the oscillation frequency.
When single-pole amplifier stages are used in a regular oscillator loop, the mini- mum
required number of stages is three. According to the analysis provided in this section,
this is because a single-pole amplifier stage can provide only 𝜃 = 𝜋 2⁄ phase shift at an
infinite frequency. Designs employing only two stages utilizing multiple pole gain
stages have been published [17-19].

26
Figure 3.3: Current starved inverter
3.3 Single-Ended Ring oscillators
The simplest ring oscillator designs employ a single-ended architecture, which was
already shown in Figure 3.1. Single-ended structures are usually preferred over the
differential architectures whenever the simplicity is essential. They are also desirable
when power dissipation is the most important consideration since they include less
number of active elements that dissipate power.
The most widely used single-ended ring oscillator stage is a CMOS inverter that
consists of an NMOS transistor and a PMOS transistor. This design, however, does not
include any means to control the operation. A control method can be added in various
ways, such as by changing the strength of an inverter in the loop, by changing the loads,
or by varying 𝑉𝑑𝑑. Figure 3.3 shows an implementation where the strength of an
inverter is changed by adding two more transistors, M3 and M4, to the inverter
structure, which is called the current starved inverter. Figures 3.4 (a) and 3.4 (b)
illustrate how the load can be modified to tune the frequency of oscillation, and Figure
3.5 demonstrate how 𝑉𝑑𝑑 can be used to tune the frequency.

27
Figure 3.4: (a) Capacitive load control, (b) Resistive load control
Figure 3.5: Frequency tuning by control of 𝑽 𝒅𝒅
Note that load tuning is not widely used for single-ended ring oscillators because of
the difficulty in implementing controllable resistors and capacitors in CMOS
technologies. Although power supply control can be used for both single-ended and
differential ring oscillator architectures, use of a low power supply voltage results in
smaller output swings. This results in a reduction in the phase noise performance and

28
the circuits get more susceptible to supply and ground disturbances. Shift of DC levels
with the change of supply voltage is also undesirable.
Although this type of stage offers great simplicity, an output with digital voltage levels,
and fast operation, adding the electronic control transistors reduces some of the
desirable features of the inverter-based design. The single-ended construction makes it
susceptible to common mode problems such as power supply and substrate bounces. In
addition, the output does not provide a 50% duty cycle under practical conditions, and
it is more susceptible to process and temperature variations when compared to
oscillators incorporating standard current control techniques. This type of oscillator can
be useful either as a benchmark design for comparison [18-20] or for testing new
architectural techniques where it is preferred because of its simplicity[21].
3.4 Differential Ring oscillators
Single-ended ring oscillator structures are not widely used in state-of-the-art high-
frequency communications systems. Differential architectures tend to be preferred over
the single-ended designs because of their inherent advantages. This includes better
immunity to common-mode noise, improved spectral purity, and 50% duty cycle at the
output. Differential ring oscillators can be constructed with an even number of stages,
unlike their single-ended counterparts. The required extra phase shift (π) can be
obtained by reversing one of the connections in the architecture introducing a DC phase
inversion. Figure 3.6 shows a four-stage differential ring oscillator where the DC phase
inversion is between the fourth and the first stages.
Figure 3.6: 4-Stage differential ring oscillator
The most widely used differential ring oscillator stage is perhaps the differential pair
with active loads and a tail current supply. The differential pair is utilized frequently in

29
analog circuit designs, even in high-frequency digital networks employing current
switching techniques. It is, therefore, considered to be well studied in terms of noise
and small-signal transfer characteristics. Figure 3.7 shows the simplest differential pair
structure, with active loads biased in the saturation region. Note that, although the
frequency control appears to be through the input node 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙, general practice is to
use a current mirror and to control the stage using the mirrored current, as illustrated in
Figure 3.8.
Assuming full switching of the mirrored current by the differential pair, the
delay of the differential stage in Figure 3.8 can be written as:
𝑇𝐷 =
𝐶 𝐿 𝑉𝑝−𝑝
𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙
(3.13)
Where 𝑐 𝐿, is the total load capacitance at each output node, 𝑉𝑝−𝑝 is the voltage swing
at the output, and 𝐼𝑐𝑜𝑛𝑡𝑟𝑜𝑙 is the mirrored current. Therefore, the oscillation frequency
of an N stage ring oscillator employing this stage is:
𝑓𝑜𝑠𝑐 = (2 ∗ 𝑁 ∗
𝐶 𝐿 𝑉𝑝−𝑝
𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙
)−1
(3.14)
From this equation, one can see that the oscillation frequency of the oscillator can be
controlled linearly by varying the mirrored current. Note that this structure does not
offer any way to control the output DC voltage levels or the output amplitude.

30
Figure 3.7: Simple differential pair
Figure 3.8: Differential pair with symmetrical loads
As the control currents are varied, the DC levels of the output will fluctuate. This may
create a problem if the output signal is used to drive circuitry that is sensitive to the
input DC levels. In addition, an amplitude control option might be desirable to limit the
output signal amplitude. One improvement on the simple active load differential pair
structure is the use of symmetrical loads, as shown in Figure 3.9 [21]. Each load consists
of a PMOS transistor pair. One PMOS device is biased in the triode region with an

31
additional bias circuitry, while the other is a diode-connected transistor biased in the
saturation region. This load provides symmetrical characteristics and an amplitude
control option through 𝑉𝑏𝑎𝑖𝑠, which is used to change the resistance of the triode-region
transistors. This way, the output swing is kept between 𝑉𝑑𝑑 and 𝑉𝑏𝑎𝑖𝑠In addition, the
symmetrical load configuration makes it easier to achieve the necessary gain for
sustaining the oscillation since the transconductances (𝑔 𝑚) of the load transistors does
not directly depend on the control current. Note that the utilization of symmetrical
Figure 3.9: Differential pair with symmetrical loads & amplitude control
circuitry
loads may not be the best choice for a low-noise VCO since this configuration is more
susceptible to deterministic jitter because of device mismatches [22]. A more
complicated design that exhibits better amplitude and output DC level control is shown
in Figure 3.9. This is a differential pair with symmetric loads. Additional transistors,
M8 and M9, are utilized as a voltage limiter.𝑉𝑏𝑎𝑖𝑠Controls the lower limit of the output
voltage, while Vbias2 controls the upper limit of the output voltage such that the output
swing is between 𝑉𝑏𝑎𝑖𝑠2 + 𝑉𝑇𝑝and 𝑉𝑏𝑎𝑖𝑠one problem with this scheme is that the
additional active devices may decrease the maximum frequency and increase the phase
noise.

32
CHAPTER IV
CMOS RING OSCILLATOR WITH STACKING
TECHNIQUES
4.1 Stacking Techniques
CMOS technology feature size and threshold voltage have been scaling down for
decades for achieving high density and high performance. Because of this technology
trend, transistor leakage power has increased exponentially. As the feature size becomes
smaller, shorter channel lengths result in increased sub-threshold leakage current
through a transistor when it is off. Low threshold voltage also results in increased sub-
threshold leakage current because transistors cannot be turned off completely. For these
reasons, static power consumption, i.e., leakage power dissipation, has become a
significant portion of total power consumption for current and future silicon
technologies. There are several VLSI techniques to reduce leakage power. Each
technique provides an efficient way to reduce leakage power, but disadvantages of each
technique limit the application of each technique. We propose a new approach, thus
providing a new choice to low-leakage power VLSI designers.
For the most recent CMOS feature sizes (e.g., 90 nm and 65 nm), leakage power
dissipation has become an overriding concern for VLSI circuit designers. Leakage
power consumption of current CMOS technology is already a great challenge.
International Technology Roadmap for Semiconductors projects that leakage power
consumption may come to dominate total chip power consumption as the technology
feature size shrinks. This directly affects portable battery-operated devices such as
cellular phones and PDAs since they have long idle times. Several techniques used to
efficiently minimize this leakage power loss. Stack keeper is a leakage reduction
technique. Leakage is a serious problem particularly for CMOS circuits in nanoscale

33
technology. We propose a novel ultra-low leakage CMOS circuit structure which we
call “stack keeper.” Unlike many other previous approaches, stack keeper can retain
logic state during sleep mode while achieving ultra-low leakage power consumption.
We apply the stack keeper to generic logic circuits. Although the stack keeper incurs
some delay and area overhead, the stack keeper technique achieves the lowest leakage
power consumption among known state-saving leakage reduction techniques, thus,
providing circuit designers with new choices to handle the leakage power problem.
Power consumption is one of the top concerns of VLSI circuit design, for which CMOS
is the primary technology. Today’s focus on low power is not only because of the recent
growing demands of mobile applications. Even before the mobile era, power
consumption has been a fundamental problem. To solve the power dissipation problem,
many researchers have proposed different ideas from the device level to the
architectural level and above. However, there is no universal way to avoid tradeoffs
between power, delay, and area, and thus, designers are required to choose appropriate
techniques that satisfy application and product needs. Power consumption of CMOS
consists of dynamic and static components. Dynamic power is consumed when
transistors are switching and static power is consumed regardless of transistor
switching. Dynamic power consumption was previously (at 180nm technology and
above) the single largest concern for low-power chip designers since dynamic power
accounted for 90% or more of the total chip power. Therefore, many previously
proposed techniques, such as voltage and frequency scaling, focused on dynamic power
reduction. However, as the feature size shrinks, e.g., to 0.09 and 0.065 m, static power
has become a great challenge for current and future technologies. Based on the
International Technology Roadmap for Semiconductors (ITRS) [23-26].
4.2 Techniques for Leakage Power Reduction
Techniques for leakage power reduction can be grouped into two categories: state-
preserving techniques where circuit state is retained and state destructive techniques
where the current Boolean output value of the circuit might be lost. A state preserving
technique has an advantage over a state destructive technique in that with a state
preserving technique the circuitry can resume operation at a point much later in time
without having to somehow regenerate state. There are several VLSI techniques for

34
reducing leakage power. Each technique provides an efficient way to reduce leakage
power.
They are:
1. Sleep Method
2. Sleepy Stack Method
3. Dual Sleep Method
4. Dual Stack Approach Method
4.3 Proposed Approach
One of the main reasons causing the leakage power increase is the increase of sub-
threshold leakage power. When technology feature size scales down, supply voltage
and threshold voltage also scale down. Sub-threshold leakage power increases
exponentially as threshold voltage decreases. Furthermore, the structure of the short
channel device decreases the threshold voltage even lower. In addition to sub-threshold
leakage, another contributor to leakage power is gate-oxide leakage power due to the
tunneling current through the gate-oxide insulator. Since gate oxide thickness may
reduce as the channel length decreases, in sub 0.1m technology, gate-oxide leakage
power may be comparable to sub-threshold leakage power if not handled properly.
However, we assume other techniques will address gate-oxide leakage; for example,
high- dielectric gate insulators may provide a solution to reduce gate-leakage [27].
Therefore, this paper focuses on reducing sub-threshold leakage power consumption.
In this paper, we provide a new circuit structure named “stack keeper” as a remedy for
static power consumption. The stack keeper has a novel structure that uniquely
combines the advantages of two major prior approaches, the sleep transistor technique
and the forced stack technique. However, unlike the sleep transistor technique, the stack
keeper technique retains the original state; furthermore, unlike the forced stack
technique, the stack keeper technique can utilize high- to achieve up to two orders of
magnitude leakage power reduction compared to the forced stack. Unfortunately, the
stack keeper technique comes with delay and area overheads. Therefore, the stack
keeper technique provides new Pareto points to designers who require ultra-low leakage
power consumption and are willing to pay some area and delay cost. The main
contributions of this thesis are as follows: 1) introduction of a stack keeper structure

35
that can save leakage power up to two orders of magnitude for circuits that require
extremely low leakage power consumption and 2) analysis of example stack keeper
logic circuits in terms of various ways (transistor scaling, threshold voltage, and
transistor width) circuit design engineers can employ to adopt the stack keeper
technique as necessary. As technology scales down, the size of transistors has been
shrinking. The number of transistors on chip has thus increased to improve the
performance of circuits. The supply voltage, being one of the critical parameters, has
also been reduced accordingly to maintain the characteristics of an MOS device.
Therefore, in order to maintain the transistor switching speed, the threshold voltage is
also scaled down at the same rate as the supply voltage. [28-29]. As the leakage current
increases faster, it will become more and more proportional to the total power
dissipation.
Figure 4.1: Sleepy Stack Keeper

36
4.3.1 Sleepy Stack
The sleepy stack approach combines the sleep and stack approaches. The sleepy stack
technique divides existing transistors into two half size transistors like the stack
approach. Then sleep transistors are added in parallel to one of the divided transistors.
Figure 4.1 shows its structure. During sleep mode, sleep transistors are turned off and
stacked transistors suppress leakage current while saving state. Each sleep transistor,
placed in parallel to the one of the stacked transistors, reduces resistance of the path, so
delay is decreased during active mode. However, area penalty is a significant matter for
this approach since every transistor is replaced by three transistors and since additional
wires are added for S and S’, which are sleep signals.
Figure 4.2: Sleepy Stack

37
4.3.2 Stack Approach
Another technique for leakage power reduction is the stack approach, which forces a
stack effect by breaking down an existing transistor into two half size transistors [30].
Figure 4.2 shows its structure. When the two transistors are turned off together, induced
reverse bias between the two transistors results in subthreshold leakage current
reduction. However, divided transistors increase delay significantly and could limit the
usefulness of the approach.
Figure 4.3: Stack Method
In conventional CMOS inverter if input is given low as compared to threshold voltage,
then at the same time PMOS turns on and NMOS turns off. And if input is given high
at the gate terminal as compared to threshold voltage, then at the same time PMOS turns
off and NMOS turns on.

38
4.3.3 Sleep Transistor Approach
The most well-known traditional approach is the sleep approach Figure 4.4. In the sleep
approach, both (i) an additional “sleep” PMOS transistor is placed between VDD and
the pull-up network of a circuit and (ii) an additional “sleep” NMOS transistor is placed
between the pull-down network and GND. These sleep transistors turn off the circuit
by cutting off the power rails. By cutting off the power source, this technique can reduce
leakage power effectively. However, the technique results in destruction of state plus a
floating output voltage in sleep mode[31-32].
4.3.4 Sleepy Stack Approach
The sleepy stack approach combines the sleep and stack approaches Figure 4.5. The
sleepy stack technique divides existing transistors into two half size transistors like the
stack approach. Then sleep transistors are added in parallel to one of the divided
transistors. During sleep mode, sleep transistors are turned off and stacked transistors
suppress leakage current while saving state. Area penalty is a significant matter for this
approach since every transistor is replaced by three transistors.
4.3.5 Sleepy Keeper Approach
Sleepy keeper utilizes leakage feedback technique Figure 4.6. In this approach, a PMOS
transistor is placed in parallel to the sleep transistor (S) and a NMOS transistor is placed
in parallel to the sleep transistor (S'). The two transistors are driven by the output of the
inverter. During sleep mode, sleep transistors are turned off and one of the transistors
in parallel to the sleep transistors keep the connection with the appropriate power rail.

39
Figure 4.4 Sleep Approach Figure 4.5 Sleepy Stack
Figure 4.6: Sleepy Keeper

40
4.3.6 Dual Sleep Approach
Dual sleep approach Figure 4.7 uses the advantage of using the two-extra pull-up and
two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since
the dual sleep portion can be made common to all logic circuitry, less number of
transistors is needed to apply a certain logic circuit.
4.3.7 Dual Stack Approach
In dual stack approach Figure 4.8, 2 PMOS in the pulldown network and 2 NMOS in
the pull-up network are used. The advantage is that NMOS degrades the high logic level
while PMOS degrades the low logic level. Compared to previous approaches it requires
greater area. The delay is also increased.
Figure 4.7: Dual Sleep Figure 4.8: Dual Stack

41
CHAPTER V
SIMULATIONS AND RESULT
In this chapter, simulated the different Ring Oscillators using stacking technique and
compare with the conventional five stage ring oscillator. All the circuits are designed
on the PYXIS (MENTOR GRAPHICS) tool and the TINY CAD. All the circuits are
designed on 180nm channel length and the width vary according to trade of i.e.
𝑊𝑝=1μm, 𝑊𝑛=0.5μm and 𝑊𝑝=0.8μm, 𝑊𝑛=0.4μm.
Figure 5.1: 7 Stage Ring Oscillator

42
Table 5.1: Frequency and power consumption variation of 7 stage RO at
different voltage and channel width
Voltage
(V)
Frequency(GHz)
for
𝑊𝑝= 1μm
and
𝑊𝑛=0.5μm
Power(μW)
for 𝑊𝑝=1μm
and
𝑊𝑛=0.5μm
Frequency(GHz)
for
𝑊𝑝= 0.8μm
and
𝑊𝑛=0.4μm
Power(μW)
for
𝑊𝑝=0.8μm
and
𝑊𝑛= 0.4μm
1 0.951 6.016 0.994 5.383
1.2 1.409 44.625 1.470 38.778
1.4 1.845 162.888 1.932 138.166
1.6 2.238 375.282 2.347 314.942
1.8 2.582 681.827 2.719 569.880
2.0 2.879 1085 3.030 905.957
2.2 3.145 1590 3.314 1327
2.4 3.374 2200 3.570 1837
2.6 3.569 2919 3.787 2439
2.8 3.736 3747 3.973 3134

43
Figure 5.2: Comparison graph of Frequency 7 Stage RO at different channel
width and voltages.
Figure 5.3: Comparison graph of Power of 7 Stage RO at different channel width
and voltages.
0
1
2
3
4
5
6
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
FREQUENCY(GHZ)
VOLTAGE(V)
frequency (GHz) for Wp= 1μm and Wn=0.5μm
frequency (GHz) for Wp= 0.8μm and Wn=0.4μm
0
500
1000
1500
2000
2500
3000
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
POWER
VOLTAGE(V)
Power (μW) for Wp=1μm and
Wn=0.5 μm
Power (μW) for Wp=0.8μm and
Wn= 0.4 μm

44
Figure 5.4: Waveform of 7 stage Ring Oscillator

45
Figure 5.5: 5 stage Ring Oscillator
Table 5.2: Frequency and Power Consumption Variation of 5 Stage RO at
different width and Voltages
Voltage
(V)
frequency
(GHz) for 𝑊𝑝=
1μm and
𝑊𝑛=0.5μm
Power (μW)
for 𝑊𝑝=1μm
and
𝑊𝑛=0.5 μm
frequency
(GHz) for 𝑊𝑝=
0.8μm and
𝑊𝑛=0.4μm
Power (μW)
for 𝑊𝑝=0.8μm
and
𝑊𝑛= 0.4 μm
1 1.345 4.297 1.406 3.845
1.2 1.997 31.875 2.085 27.699
1.4 2.615 116.348 2.741 98.69
1.6 3.160 268.064 3.314 224.958
1.8 3.654 487.0199 3.841 407.060
2.0 4.056 775.278 4.273 647.112
2.2 4.423 1136 4.666 948.00
2.4 4.745 1571 5.019 1313
2.6 5.020 2085 5.321 1742
2.8 5.245 2676 5.579 2238

46
Figure 5.6: Comparison graph of Frequency of 5 Stage RO at different channel
width and voltage
Figure 5.7: Comparison graph of Power of 5 Stage RO at different channel width
and voltages.
0
1
2
3
4
5
6
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
FREQUENCY(GHZ)
VOLTAGE(V)
0
500
1000
1500
2000
2500
3000
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
POWER
VOLTAGE(V)
Wn=0.5 μm
Wn= 0.4 μm

47
Figure 5.8: Waveform of 5 stage Ring Oscillator

48
Figure 5.9: 5 Stage Stacked Ring Oscillator
Table 5.3: Frequency and Power Consumption Variation of 5 Stage Stacked RO
at different width and Voltages
Voltage
(V)
Frequency(GHz)
for
𝑊𝑝= 1μm
and
𝑊𝑛=0.5μm
Power(μW)
for 𝑊𝑝=1μm
and
𝑊𝑛=0.5μm
Frequency(GHz)
for
𝑊𝑝= 0.8μm
and
𝑊𝑛=0.4μm
Power(μW)
for
𝑊𝑝=0.8μm
and
𝑊𝑛= 0.4μm
1 0.395 1.830 0.463 1.392
1.2 0.608 13.116 0.713 8.961
1.4 0.805 49.750 0.951 31.298
1.6 0.988 121.792 1.169 73.522
1.8 1.152 232.860 1.382 138.054
2.0 1.304 385.253 1.572 226.77
2.2 1.435 581.220 1.746 341.49
2.4 1.541 822.900 1.904 483.90
2.6 1.643 1112 2.050 655.50
2.8 1.731 1455 2.181 857.78

49
Figure 5.10: Comparison graph of Frequency of 5 Stage Stacked RO at different
channel width and voltages.
Figure 5.11: Comparison graph of Power of 5 Stage Stacked RO at different channel
width and voltages.
0
1
2
3
4
5
6
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
FREQUENCY(GHZ)
VOLTAGE(V)
0
500
1000
1500
2000
2500
3000
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
POWER
VOLTAGE(V)
Wn=0.5 μm
Wn= 0.4 μm

50
Figure 5.12: Waveform of 5 Stage Stacked RO

51
Figure 5.13: 5 Stage Ring Oscillator Stacked with 3 stage Ring Oscillator
(cascade form of RO)
Table 5.4: Frequency and Power consumption variation of 5 stage Stacked with 3
stage RO at different width and voltages
Voltage
(V)
Frequency(GHz) for
𝑊𝑝= 1μm
and
𝑊𝑛=0.5μm
Power(μW)
for 𝑊𝑝=1μm
and
𝑊𝑛=0.5μm
Frequency(GHz) for
𝑊𝑝= 0.8μm
and
𝑊𝑛=0.4μm
Power(μW)
for
𝑊𝑝=0.8μm
and
𝑊𝑛= 0.4μm
1 0.652 2.678 0.795 2.213
1.2 1.865 16.943 1.952 10.542
1.4 2.562 98.235 2.623 70.365
1.6 2.856 156.854 2.956 120.36
1.8 3.056 245.562 3.230 198.325
2.0 3.256 654.514 3.365 421.362
2.2 3.562 862.365 3.614 602.215
2.4 3.754 1143 3.841 851.32
2.6 3.812 1523 3.901 932.256
2.8 3.856 2158 3.985 1265

52
Figure 5.14: Comparison graph of Frequency of Cascade RO at different
channel width and Voltages.
Figure 5.15: Comparison graph of Power of Cascade RO at different channel
width and Voltages.
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
FREQUENCY(GZ)
VOLTAGE(V)
Frequency(GHz) for
Wp= 1μm
and
Wn=0.5μm
Frequency(GHz) for
Wp= 0.8μm
and
Wn=0.4μm
0
500
1000
1500
2000
2500
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
POWER
VOLTAGE(V)
Power(μW) for Wp=1μm and
Wn=0.5μm
Power(μW) for Wp=0.8μm and
Wn= 0.4μm

53
Figure 5.16: Waveform of cascade RO

54
Figure 5.17: 5 Stage Sleepy Stacked Ring Oscillator.
Table 5.5: Frequency and Power Consumption Variation of 5 Stage Sleepy
Stacked RO at different width and Voltages
Voltage
(V)
Frequency(GHz)
for
𝑊𝑝= 1μm
and
𝑊𝑛=0.5μm
Power(μW)
for 𝑊𝑝=1μm
and
𝑊𝑛=0.5μm
Frequency(GHz)
for
𝑊𝑝= 0.8μm
and
𝑊𝑛=0.4μm
Power(μW)
for
𝑊𝑝=0.8μm
and
𝑊𝑛= 0.4μm
1 0.611 2.046 0.754 1.322
1.2 0.966 13.515 1.056 10.321
1.4 1.276 46.35 1.365 40.512
1.6 1.524 105.61 1.586 99.362
1.8 1.789 192.97 2.015 190.32
2.0 2.020 310.29 2.153 295.23
2.2 2.279 459.65 2.321 440.225
2.4 2.477 642.97 2.562 620.326
2.6 2.661 861.96 2.754 823.023
2.8 2.819 1118 3.012 995.362

55
Figure 5.18: Comparison graph of Frequency of 5 Stage Sleepy Stacked RO at
different channel width and Voltages.
Figure 5.19: Comparison graph of power of 5 Stage Sleepy Stacked RO at
different channel width and Voltages
0
0.2
0.4
0.6
0.8
1
1.2
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
FREQUENCY(GHZ)
VOLTAGE(V)
Frequency(GHz) for
Wp= 1μm
and
Wn=0.5μm
Frequency(GHz) for
Wp= 0.8μm
and
Wn=0.4μm
0
20
40
60
80
100
120
140
160
180
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
POWER
VOLTAGE(V)
Wn=0.5μm
Wn= 0.4μm

56
Figure 5.20: Waveform of 5 stage sleepy stacked RO

57
Figure 5.21: 5 Stage Dual Stacked RO
Table 5.6: Frequency and Power Consumption Variation of 5 Stage Dual
Stacked RO at different width and Voltages
Voltage
(V)
Frequency(GHz)
for
𝑊𝑝= 1μm
and
𝑊𝑛=0.5μm
Power(μW)
for
𝑊𝑝=1μm
and
𝑊𝑛=0.5μm
Frequency(GHz)
for
𝑊𝑝= 0.8μm
and
𝑊𝑛=0.4μm
Power(μW)
for
𝑊𝑝=0.8μm
and
𝑊𝑛= 0.4μm
1 0.0023 0.00569 0.0035 0.00432
1.2 0.0133 0.0265 0.0162 0.0165
1.4 0.0597 0.119 0.0703 0.0251
1.6 0.165 0.5078 0.180 0.459
1.8 0.325 2.0115 0.3603 1.126
2.0 0.465 7.107 0.5006 6.521
2.2 0.623 20.978 0.670 20.032
2.4 0.772 50.023 0.820 49.263
2.6 0.996 98.804 1.025 97.32
2.8 1.0049 169.47 1.125 160.36

58
Figure 5.22: Comparison graph of Frequency of 5 Stage Dual Stacked RO at
different channel width and voltages.
Figure 5.23: Comparison graph of Power of 5 Stage Dual Stacked RO at
different channel width and voltages.
0
0.2
0.4
0.6
0.8
1
1.2
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
FREQUENCY(GHZ)
VOLTAGE(V)
Frequency(GHz) for
Wp= 1μm
and
Wn=0.5μm
Frequency(GHz) for
Wp= 0.8μm
and
Wn=0.4μm
0
20
40
60
80
100
120
140
160
180
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
FREQUENCY
VOLTAGE(V)
Wn=0.5μm
Wn= 0.4μm

59
Figure 5.24: Waveform of 5 Stage Dual Stacked RO

60
Table 5.7: Comparison table of frequency of different RO for 𝑾 𝒑=1μm and
𝑾 𝒏=0.5μm
Volta
ge
(V)
Frequency(G
Hz) 5 Stage
RO for
𝑊𝑝= 1μm
and
𝑊𝑛=0.5μm
Frequency(G
Hz) 5 Stage
Stacked RO
for
𝑊𝑝= 1μm
and
𝑊𝑛=0.5μm
Frequency(G
Hz) 5 Stage
Cascade RO
for
𝑊𝑝= 1μm
and
𝑊𝑛=0.5μm
Frequency(G
Hz) 5 Stage
Sleepy
Stacked RO
for
𝑊𝑝= 1μm
and
𝑊𝑛=0.5μm
Frequency(G
Hz) 5 Stage
Dual
Stacked RO
for
𝑊𝑝= 1μm
and
𝑊𝑛=0.5μm
1 1.345 0.395 0.652 0.611 0.0023
1.2 1.997 0.608 1.865 0.966 0.0133
1.4 2.615 0.805 2.562 1.276 0.059
1.6 3.160 0.988 2.856 1.524 0.165
1.8 3.654 1.152 3.056 1.789 0.325
2.0 4.056 1.304 3.256 2.020 0.465
2.2 4.423 1.435 3.562 2.279 0.623
2.4 4.745 1.541 3.754 2.477 0.772
2.6 5.020 1.643 3.812 2.661 0.996
2.8 5.245 1.731 3.856 2.819 1.0049

61
Figure 5.25: Comparison graph of frequency of different RO for 𝑾 𝒑=1μm and
𝑾 𝒏=0.5μm
0
1
2
3
4
5
6
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
FREQUENCY(GHZ)
VOLTAGE(V)
Frequency(GHz) 5 Stage RO for
Wp= 1μm
and
Wn=0.5μm
Frequency(GHz) 5 Stage Stacked RO for
Wp= 1μm
and
Wn=0.5μm
Frequency(GHz) 5 Stage Cascade RO for
Wp= 1μm
and
Wn=0.5μm
Frequency(GHz) 5 Stage Sleepy Stacked RO for
Wp= 1μm
and
Wn=0.5μm
Frequency(GHz) 5 Stage Dual Stacked RO for
Wp= 1μm
and
Wn=0.5μm

62
Table 5.8: Comparison Table of Frequency of different RO for 𝑾 𝒑=0.8μm and
𝑾 𝒏=0.4μm
Volta
ge
(V)
Frequency(G
Hz) 5 Stage
RO for
𝑊𝑝= 0.8μm
and
𝑊𝑛=0.4μm
Frequency(G
Hz) 5 Stage
Stacked RO
for
𝑊𝑝= 0.8μm
and
𝑊𝑛=0.4μm
Frequency(G
Hz) 5 Stage
Cascade RO
for
𝑊𝑝= 0.8μm
and
𝑊𝑛=0.4μm
Frequency(G
Hz) 5 Stage
Sleepy
Stacked RO
for
𝑊𝑝= 0.8μm
and
𝑊𝑛=0.4μm
Frequency(G
Hz) 5 Stage
Dual
Stacked RO
for
𝑊𝑝= 0.8μm
and
𝑊𝑛=0.4μm
1 1.406 0.754 0.745 0.754 0.0035
1.2 2.085 1.056 1.974 1.056 0.0162
1.4 2.741 1.365 2.654 1.365 0.0703
1.6 3.314 1.586 2.954 1.586 0.180
1.8 3.841 2.015 3.125 2.015 0.3603
2.0 4.273 2.153 3.351 2.153 0.5006
2.2 4.666 2.321 3.641 2.321 0.670
2.4 5.019 2.562 3.841 2.562 0.820
2.6 5.321 2.754 3.901 2.754 1.025
2.8 5.579 3.012 3.985 3.012 1.125

63
Figure 5.26: Comparison Graph of frequency for 𝑾 𝒑 = 𝟎. 𝟖𝝁𝒎 and 𝑾 𝒏 =
𝟎. 𝟒𝝁𝒎
0
1
2
3
4
5
6
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
FREQUENCY(GHZ)
VOLTAGE(V)
Frequency(GHz) 5 Stage RO for
Wp= 0.8μm
and
Wn=0.4μm
Frequency(GHz) 5 Stage Stacked RO for
Wp= 0.8μm
and
Wn=0.4μm
Frequency(GHz) 5 Stage Cascade RO for
Wp= 0.8μm
and
Wn=0.4μm
Frequency(GHz) 5 Stage Sleepy Stacked RO for
Wp= 0.8μm
and
Wn=0.4μm
Frequency(GHz) 5 Stage Dual Stacked RO for
Wp= 0.8μm
and
Wn=0.4μm

64
Table 5.9: Comparison Table of Power of different RO for 𝑾 𝒑=1μm and
𝑾 𝒏 = 0.5μm
Voltage
(V)
Power(μW)5
Stage RO for
𝑊𝑝= 1μW
and
𝑊𝑛=0.5μW
Power(μW)5
Stage
Stacked RO
for
𝑊𝑝=1μW
and
𝑊𝑛=0.5μW
Power(μW)
5 Stage
Cascade RO
for
𝑊𝑝=1μW
and
𝑊𝑛=0.5μW
Power(μW))
5 Stage
Sleepy
Stacked RO
for
𝑊𝑝=1μW
and
𝑊𝑛=0.5μW
Power(μW)
5 Stage
Dual
Stacked RO
for
𝑊𝑝= 1μW
and
𝑊𝑛=0.5μW
1 4.297 1.830 2.678 2.046 0.00569
1.2 31.875 13.116 16.943 13.515 0.0265
1.4 116.348 49.750 98.235 46.35 0.119
1.6 268.064 121.792 156.854 105.61 0.5078
1.8 487.0199 232.860 245.562 192.97 2.0115
2.0 775.278 385.253 654.514 310.29 7.107
2.2 1136 581.220 862.365 459.65 20.978
2.4 1571 822.900 1143 642.97 50.023
2.6 2085 1112 1523 861.96 98.804
2.8 2676 1455 2158 1118 169.47

65
Figure 5.27: Comparison graph of power of different RO for 𝑾 𝒑=1μm and
𝑾 𝒏= 0.5μm
0
500
1000
1500
2000
2500
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
POWER
VOLTAGE(V)
Power(µW) 5 Stage RO for
Wp= 0.8μm
and
Wn=0.4μm
Power(µW) 5 Stage Stacked RO for
Wp= 0.8μm
and
Wn=0.4μm
Power(µW) 5 Stage Cascade RO for
Wp= 0.8μm
and
Wn=0.4μm
Power(µW) 5 Stage Sleepy Stacked RO for
Wp= 0.8μm
and
Wn=0.4μm
Power(µW) 5 Stage Dual Stacked RO for
Wp=0.8μm
and
Wn=0.4μm

66
Table 5.10: Comparison Table of Power of different RO for 𝑾 𝒑=0.8μm and
𝑾 𝒏 = 0.4μm
Voltage
(V)
Power(μW)5
Stage RO for
𝑊𝑝= .8μW
and
𝑊𝑛=0.4μW
Power(μW)5
Stage Stacked
RO for
𝑊𝑝=0.8μW
and
𝑊𝑛=0.4μW
Power(μW)
5 Stage
Cascade RO
for
𝑊𝑝=0.8μW
and
𝑊𝑛=0.4μW
Power(μW))
5 Stage
Sleepy
Stacked RO
for
𝑊𝑝=0.8μW
and
𝑊𝑛=0.4μW
Power(μW)
5 Stage Dual
Stacked RO
for
𝑊𝑝= 0.8μW
and
𝑊𝑛=0.4μW
1 3.845 1.392 2.213 1.322 0.00432
1.2 27.699 8.961 10.542 10.321 0.0165
1.4 98.69 31.298 70.365 40.512 0.0251
1.6 224.958 73.522 120.36 99.362 0.459
1.8 407.060 138.054 198.325 190.32 1.126
2.0 647.112 226.77 421.362 295.23 6.521
2.2 948.00 341.49 602.215 440.225 20.032
2.4 1313 483.90 851.32 620.326 49.263
2.6 1742 655.50 932.256 823.023 97.32
2.8 2238 857.78 1265 995.362 160.36

67
Figure 5.28: Comparison Graph of Power of different RO for 𝑾 𝒑=0.8μm and
𝑾 𝒏= 0.4μm
0
500
1000
1500
2000
2500
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
POWER
VOLTAGE(V)
Power(µW) 5 Stage RO for
Wp= 0.8μm
and
Wn=0.4μm
Power(µW) 5 Stage Stacked RO for
Wp= 0.8μm
and
Wn=0.4μm
Power(µW) 5 Stage Cascade RO for
Wp= 0.8μm
and
Wn=0.4μm
Power(µW) 5 Stage Sleepy Stacked RO for
Wp= 0.8μm
and
Wn=0.4μm
Power(µW) 5 Stage Dual Stacked RO for
Wp=0.8μm
and
Wn=0.4μm

68
CHAPTER VI
CONCLUSION AND FUTURE SCOPE
Ring oscillators are basic building blocks of complex integrated circuits. They are
mainly used as clock generating circuits. Many different types of ring oscillators are
presented in literature. They differ in respect to architectural, realization of inverters
stages, number of inverter stages, etc. In this thesis, we have considered realization of
ring oscillator based on four different types of single-ended inverters. The simulation
was performed using PYXIS (MENTOR GRAPHICS) Tool and library model for
180nm CMOS technology.
Extensive studies have been carried out on the characteristics of ring oscillators
and its potential applications in the field of electronic communications. The voltage
tuning property of ring oscillator has been studied experimentally and a few
applications based on its tuning characteristics in a PLL-based system have been
proposed which may be proved to be useful in practice. The constant phase differences
among outputs at different nodes of the ring oscillator are examined and a few important
applications using multiphase signals have been reported here. All the applications
mentioned in this dissertation have been verified by hardware experiments using
commercially available discrete circuit components.
Now-a-days ring oscillators are widely used in phase locked loops because of
its number of merits over sinusoidal oscillators or relaxation oscillators. In chapter 3,
the voltage tuning characteristics of a variable length ring oscillator has been explored.
The operating frequency range of an RO depends on the number of inverters used in
the ring structure. The oscillation frequency of an RO does not vary linearly with tuning
voltage. Experimental results reveal that the change of frequency is more for lower
values of tuning voltage than that for large values of tuning voltage. In other words, the
voltage sensitivity decreases for higher values of control voltage and this is true for all
values of ring length. The effects of using this ring oscillator as a voltage controlled
oscillator in a PLL based system such as FM demodulator and divider based frequency
synthesizer have also been examined here. Depending on the field of application, the
properties of PLLs should have to be properly adjusted to get optimum performance of

69
the system. In the FM demodulator application of a PLL, it has been observed that the
total harmonic distortion decreases when the VCO sensitivity is kept constant with
tuning voltage. This has been done by choosing the operating range of the ring VCO
depending on the carrier frequency of the FM signal. But in the frequency synthesizer
application of a PLL, the voltage sensitivity of the VCO should have to be adjusted
proportionally with the magnitude of the synthesized frequency to have a constant
switching speed of the synthesizer as well as a uniform spectral characteristic of the
output signal over the whole operating range of frequency. Experimentally it is
observed that the synthesized signal has lower sideband power and lower floor noise
power when the VCO sensitivity is a linear function of its oscillation frequency but
spectral purity reduces when the VCO sensitivity does not increase linearly with its
oscillation frequency.

70
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