This document discusses the static behavior and robustness of the CMOS inverter. It covers key topics such as: 1) The voltage transfer characteristics (VTC) curve and operation regions of the inverter. 2) How to calculate the switching threshold (VM) of the inverter based on transistor parameters. 3) How to determine the noise margins of the inverter using the voltage transfer characteristics and gain. 4) Equations for calculating the input logic levels (VIL and VIH) that define the noise margins. 5) How channel length modulation affects the voltage gain of the inverter.

1. Evaluating the Robustness of the
CMOS Inverter: Static Behavior
Dr. Varun Kumar
Dr. Varun Kumar (IIIT Surat) IIIT Surat-Lecture-7 1 / 10

2. Outlines
1 Voltage Transfer Characteristics
2 Switching Threshold
3 Noise Margin
4 Gain Calculation
Dr. Varun Kumar (IIIT Surat) IIIT Surat-Lecture-7 2 / 10

3. Voltage Transfer Characteristics
Figure: VTC of static CMOS inverter (VDD = 2.5 V). For each operation region,
the modes of the transistors are annotated off, resistive, or saturated.
Dr. Varun Kumar (IIIT Surat) IIIT Surat-Lecture-7 3 / 10

4. CMOS Inverter-Switching Threshold
⇒ The switching threshold, VM, a voltage at which Vin = Vout.
⇒ In VTC curve (Vin vs Vout ∼ VGS vs VDS ).
⇒ Both PMOS and NMOS are always saturated, since VDS = VGS.
⇒ We solve VM considering high supply voltage, so that the devices can
be assumed to be velocity-saturated (or VDsat < VM − VT ).
⇒ Saturation velocity: It is the maximum velocity a charge carrier in a
semiconductor, generally an electron.
⇒ We ignore the channel length modulation effects and IDSn = −IDSp
knVDSATn
VM −VTn −
VDSATn
2
+kpVDSATn
VM −VTp −VDD −
VDSATp
2
= 0
Solving for VM
VM =
VTn + VDSATn
2
+ r
VTp + VDD +
VDSATp
2
1 + r
with r =
kpVDSATp
knVDSATn
=
vsatpWp
vsatnWn
when Coxp = Coxn
Dr. Varun Kumar (IIIT Surat) IIIT Surat-Lecture-7 4 / 10

5. Continued–
⇒ For large values of VDD (compared to VT , VDSAT ), we have
VM ≈
rVDD
1 + r
⇒ For r = 1, VM = VDD/2
⇒ From above relation, i.e IDSn = −IDSp, we can express
(W /L)p
(W /L)n
=
k0
nVDSATn(VM − VTn − VDSATn/2)
k0
pVDSATp(VDD − VM + VTp + VDSATp/2)
Dr. Varun Kumar (IIIT Surat) IIIT Surat-Lecture-7 5 / 10

6. CMOS Inverter - Noise Margin
⇒ Noise Margin: The allowable noise voltage on the input gate so that
output couldn’t be affected.
⇒ VIH and VIL are the operational points of the inverter where dVout
dVin
=-1
⇒ A simpler approach is to use a piecewise linear approximation for the
VTC.
⇒ The crossover with the VOH and the VOL lines is used to define VIH
and VIL points. The error introduced is small and well
Dr. Varun Kumar (IIIT Surat) IIIT Surat-Lecture-7 6 / 10

7. Continued–
⇒ VIH − VIL = −VOH −VOL
g = −VDD
g → g = −dVout
dVin
⇒ VIH = VM − VM
g and VIL = VM + VDD −VM
g
⇒ NMH = VDD − VIH and NML = VIL
⇒ High gain in the transition region is very desirable.
⇒ For an infinite gain (g → ∞), the noise margins is simplified as
NMH = VOH − VM and NML = VM − VOL
⇒ Let both PMOS and NMOS are velocity-saturated.
Calculation of VIL
⇒ When VIL = Vin, NMOS is in saturation and PMOS is in linear. Let
dVout
dVin
= −1 and IDSn = −IDSp
⇒ kn
2 (VGSn − VTn)2 =
kp
2 (2(VGSp − VTp)VDSp − V 2
DSp)
Dr. Varun Kumar (IIIT Surat) IIIT Surat-Lecture-7 7 / 10

8. Calculation of VIL and VIH
⇒ We know that VGSp = Vin − VDD and VDSp = VDD − Vout. Hence
kn
2
(Vin − VTn)2
=
kp
2
2(Vin − VDD − VTp)(VDD − Vout) − (VDD − Vout)2
⇒ Taking derivative wrt Vin in both side and keeping, Vin = VIL and
dVout
dVin
= −1
VIL =
2Vout + VTp − VDD + KRVTn
1 + KR
where KR =
Kn
Kp
Calculation of VIH → NMOS is in linear and PMOS in saturation
kp
2
(VGSp − VTp)2
=
kn
2
2(VGSn − VDD − VTn)VDSn − V 2
DSn
kp
2
(Vin − VDD − VTp)2
=
kn
2
2(Vin − VDD − VTn)Vout − V 2
out
Taking derivative wrt Vin on both side
Dr. Varun Kumar (IIIT Surat) IIIT Surat-Lecture-7 8 / 10

9. Continued–
VIH =
VDD + VTp + KR(2Vout + VTn)
1 + KR
Impact of device variations on static CMOS inverter VTC
Dr. Varun Kumar (IIIT Surat) IIIT Surat-Lecture-7 9 / 10

10. Voltage Gain-CMOS Inverter
⇒ Considering channel-length modulation factor, the gain can now be
derived by differentiating the current equation.
k0
nVDSATn
Vin − VTn −
VDSATn
2
(1 + λnVout)+
k0
pVDSATp
Vin − VDD − VT −
VDSATp
2
(1 + λpVout − λpVDD) = 0
⇒ Differentiation and solving for dVout
dVin
yields
dVout
dVin
=
knVDSATn
1 + λnVout
+ kpVDSATp
1 + λpVout − λpVDD
λnknVDSATn
Vin − VTn −
VDSATn
2
+ λpkpVDSATp
Vin − VDD − VTp −
VDSATp
2
⇒ Ignoring some second-order terms, and setting Vin = VM results in the gain
expression,
g = −
1
ID (VM )
knVDSATn + kpVDSATp
λn − λp
≈ −
1 + r
(VM − VTn − VDSATn/2)(λn − λp)
where ID(VM ) is the current flowing through CMOS inverter at Vin = VM
Dr. Varun Kumar (IIIT Surat) IIIT Surat-Lecture-7 10 / 10