1. MADHURI N MURTHY
630, unit 113, Park View Drive, Santa Clara, CA –95054
+1-213-839-0657 | mnmurthy@usc.edu | https://www.linkedin.com/in/madhuri-murthy-400517106
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OBJECTIVE
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EDUCATION
COURSEWORK
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TECHNICAL
SKILLS
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EXPERIENCE
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PROJECTS
Seeking full time opportunities (Spring2017) in Digital Design, VLSI Design, Post & Pre Silicon Validation, ASIC & Physical Design
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UNIVERSITY OF SOUTHERN CALIFORNIA, Los Angeles, CA August 2015 –December2016
Masters of Science, Electrical Engineering
EE-477: MOS VLSI Circuit Design EE-577A: VLSI System Design EE-577B: VLSI System Design EE-537: Modern Solid StateDevices
EE-457: Computer System Organization EE-533: Network Processor Design and Programming EE-542: Internet andCloud Computing
RNS INSTITUTE OF TECHNOLOGY, Bangalore, India August 2011–May 2015
Bachelor of Engineering, Electronics and Communication Engineering
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Programming Languages: Python, C, Perl, Verilog, VHDL, AssemblyLevel (8051)
Tools: Cadence (Virtuoso, ADE, Spectre), Xilinx ISE, Modelsim, Matlab. Hspice, Eagle, Labview
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INTEL CORPORATION, Santa Clara, California May 2016 –November 2016
Component Debug Engineer
Working on the evaluation, development and debug of test methods (DFX). Develop and debug scripts (Jython, Perl) to convert
design validation vectors and drive I/O debug. Timing analysis and Critical Path Debug on silicon chips. Post silicon validation.
SNOWOFFICE, Austria July 2015
Developed a check-in and billing system for skiing equipment rentals using RFID technology with an Atmega Micro-controller.
Python, PHP, MySQl. Coding.
GE Health-care, Bangalore November2014-March 2015
Implemented a circuit design to vary the static resistance in a high voltage tank circuit of an X-ray machine, so the system can
independently combat errors to obtain a desirable RC response. Used a MSP430 Microcontroller with I2C communication in a low
power design.
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Physical Design of a General Purpose Microprocessor Spring 2016
Fully custom 16 bit 5 stage RISC processor in Cadence Virtuoso (Schematic and Layout). Data gating & Clock Gating implemented for
power optimization. Simulations and verifications using back end Perl scripting including burst mode operations. Low
Area*Delay*Power optimization implemented on all individual components.
1024 bit 6T SRAM Design Spring 2016
16-bit work access 1024 bit 6T SRAM implemented in Cadence Virtuoso (Schematic and Layout). Simulations and functionality
verifications using back end Perl scripting including burst mode operations.
Mini -Network Intrusion Detection system Spring 2016
The detection system was simulated using the Xilinx ISE tool. Implemented on Virtex –II pro NetFPGA using deterlab. Pattern
matching principles applied to incomingnetwork packets. A drop FIFO implemented in Verilog stores the packets and drops the ones
that match with a pre-defined set.
Designand Implementation of a Dual ThreadedNetwork Processor with Hardware Accelerators Spring 2016
Designeda 5-stage pipelineddata-pathwithinterconvertible memory using Verilog RTL. Simulated using Xilinx ISE tool andimplementedon Virtex
– II Pro NetFPGA using deterlab. Applicationwas detection and prevention of distributeddenial of service attacks in the network processor using
content based analysis on network packets.
Designof a General Purpose MIPS 5-stage pipeline in RTL Fall2015
Implemented a 5-stage 32bit MIPS processor using structural and RTL coding in Verilog. Forwarding units and HazardDetection Unit implemented
to take care of dependencies in early and late branch implementations.
Designof IndustryStandard Digital Phase Locked Loop Fall2015
Implemented a Digital-PLL in Cadence Virtuoso, running at 800MHz, consisting of Phase-frequency detector, Charge pump a voltage controlled
oscillator. Optimized design to get minimum Area Power product and Lock time. Implemented and tested both Schematic and Layout.
MapReduce based Music Recomm endation System using Amazon AWS Fall2015
Implementeda cloud applicationfor music recommendationbased on collaborative filtering using EC2, EMR and CloudWatch in AWS. Measured
performance from scale-out, scale-up and data-size variation techniques.