Course: BEng (Hons) in Electrical and Electronic Engineering

1. EEEC6420307
Digital Circuits and SystemDesign
Faculty of Engineering and Computer Technology
Laboratory Manual
Lecturer: Ravandran Muttiah BEng (Hons) MSc MIET
Year/Semester: Year 1 / Semester 2
Academic Session: 2021/2022
The information in this documentis important and should be noted by all students undertaking the
Bachelor of Engineering (Honours) in Electrical and Electronic Engineering
Approved by Coordinator: Endorsed By Dean:
------------------------------------------ __________________

2. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 1
Mini Project 1 - 2-to-4 DecoderWith Enable Input E And 4-to-2 Line
Priority Encoder
Decoder
An 𝑛 − to − 2𝑛
decoder is a multiple-output combinational logic network with 𝑛 input
lines and 2𝑛
output signals, as illustrated in figure 1. For each possible input condition,
one and only one output signal will be at logic 1. Therefore, we may consider the 𝑛 −
to − 2𝑛
decoder as imply a minterm generator, with each output corresponding to exactly
one min-term. Decoders are important tools in the logic designer’s repertoire. They are
used for such things as interrogating memory in order to select a particular word from the
many that are available, code conversion (for example, binary to decimal), and routing of
data.
Figure 1: 𝑛 − to − 2𝑛
decoder module.
Decoder Circuit Structures
The logic circuit of a 2-bit parallel decoder is shown in figure 2. In general, this decoder
is very simple, but also expensive. As can be seen from the figure, an input combination
or vector of 𝐵𝐴 = 00 selects the 𝑚0 output line, 𝐵𝐴 = 01 selects the 𝑚1 output line, and
so on.
𝑚0 = 𝐵
̅𝐴̅
𝑚1 = 𝐵
̅𝐴
𝑚2 = 𝐵𝐴̅
𝑚3 = 𝐵𝐴 (1)
The AND gate realisations of the 𝑛 − to − 2𝑛
decoder shown in figure 2 there is only a
single level of logic and that one 𝑛 − input AND gate is required for each of the 2𝑛
output lines. However, a problem is soon encountered in this configuration as 𝑛 becomes
𝑥0
𝑥𝑛−1
𝑦0
𝑦1
𝑦2𝑛
−1
⋮ ⋮
LSB
MSB
𝑛 − to − 2𝑛
Decoder
𝑥1

3. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 2
large because the number of inputs to the AND gates (the fan-in) exceeds practical limits
(five or six). Then two-input AND gates are used to combine these signals to form the 2𝑛
output lines for the total decoder network.
Figure 2: Two-bit parallel decoder circuit structure (active-high outputs).
Enable Control Inputs
Decoders often include one or more enable inputs, as shown in figure 3, which can be
used to either inhibit (disable) the designated function or allow (enable) it to be
performed. The decoding function of a decoder is inhibited by forcing all its outputs to
the inactive state. For example, output 𝑦0 of the 2 − to − 4 decoder in figure 3 is given
by 𝑦0 = 𝑥̅1𝑥̅0𝐸 = 𝑚0𝐸. In general,
𝑦𝑘 = 𝑚𝑘𝐸 (2)
When 𝐸 = 0, all outputs are forced to 0, whereas for 𝐸 = 1, each output 𝑦𝑘 is equal to
𝑚𝑘.
Figure 3: 2 − to − 4 decoder with enable input 𝐸.
𝑚0
LSB 𝐴
MSB 𝐵
𝑚1
𝑚2
𝑚3
𝑦0
𝑦1
𝑦2
𝑦3
𝑋0
𝑋1
𝐸
𝑦0
𝑦1
𝑦2
𝑦3
𝑥0
𝑥1
𝑥2

4. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 3
Encoders
An encoder is a combinational logic module that assigns a unique output code (a binary
number) for each input signal applied to the device; as such, it is the opposite of a
decoder. If an encoder module has 𝑛 inputs, the number of outputs 𝑠 must satisfy the
expression,
2𝑠
≥ 𝑛 (3)
or
𝑠 ≥ log2 𝑛
Encoder Circuit Structures - Encoders with Mutually Exclusive Inputs
Consider first the case in which the inputs are mutually exclusive; that is, one (and only
one) of the input lines is active at any particular instant in time; two or more input lines
are never simultaneously active. In this case the input combinations that never occur may
be used as don’t-care conditions. The design of an encoder for four input lines if one and
only one is active at any moment in time is shown in figure 4.
Figure 4: 4 − to − 2 line encoder.
𝑋0
𝑋3
𝐴0
𝑋1
𝑋2
𝐴1
4 − to − 2
Encoder

5. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 4
Table 1: Truth table
Priority Encoders
Another type of encoder is the priority encoder. The priority encoder allows multiple
input lines to be active and sends out the binary value of the subscript of the input line
with highest priority. To simplify the design, the highest priority is assigned to the
highest subscript, the next highest priority to the second highest subscript, and so on.
Consider the priority encoder of figure 5. The input lines are encoded,
𝐴1 𝐴0
𝑋0 → 0 0
𝑋1 → 0 1
𝑋2 → 1 0
𝑋3 → 1 1
If no input line is active, the priority encoder sends out (𝐴1𝐴0) = (00). If a single line is
active, the encoder sends out the binary value of the subscript of the active line. If more
than one input is active, the encoder sends out the binary value of the largest subscript of
the active lines. Table 2 displays the truth table for the encoder. Note that the two
additional output lines indicate that no input line is active (𝐸𝑂 = 1) and one or more
inputs are active (𝐺𝑆 = 1). Figure 6 present the logic diagram of the function, which
reduces to,
𝑋3 𝑋2 𝑋1 𝑋0 𝐴1 𝐴0
0 0 0 0 𝑑 𝑑
0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 𝑑 𝑑
0 1 0 0 1 0
0 1 0 1 𝑑 𝑑
0 1 1 0 𝑑 𝑑
0 1 1 1 𝑑 𝑑
1 0 0 0 1 1
1 0 0 1 𝑑 𝑑
1 0 1 0 𝑑 𝑑
1 0 1 1 𝑑 𝑑
1 1 0 0 𝑑 𝑑
1 1 0 1 𝑑 𝑑
1 1 1 0 𝑑 𝑑
1 1 1 1 𝑑 𝑑
Outputs
Inputs

6. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 5
𝐴1 = 𝑋2 + 𝑋3
𝐴0 = 𝑋3 + 𝑋1𝑋
̅2
and
𝐸𝑂 = 𝐺𝑆
̅̅̅̅ = 𝑋3 + 𝑋2 + 𝑋1 + 𝑋0
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Figure 5: Functional diagram of 4 − to − 2 line priority encoder.
Table 2: Truth table
𝑋0
𝑋3
𝐴0
𝑋1
𝑋2
𝐸𝑂
4 − to − 2
Priority
Encoder
𝐴1
𝐺𝑆
𝑋3 𝑋2 𝑋1 𝑋0 𝐴1 𝐴0 𝐺𝑆 𝐸𝑂
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 1 1 0
0 0 1 1 1 1 1 0
0 1 0 0 1 0 1 0
0 1 0 1 1 0 1 0
0 1 1 0 1 0 1 0
0 1 1 1 1 0 1 0
1 0 0 0 1 1 1 0
1 0 0 1 1 1 1 0
1 0 1 0 1 1 1 0
1 0 1 1 1 1 1 0
1 1 0 0 1 1 1 0
1 1 0 1 1 1 1 0
1 1 1 0 1 1 1 0
1 1 1 1 1 1 1 0
Inputs Outputs

7. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 6
The two output functions 𝐴1 and 𝐴0 are independent of 𝑋0. Note that the priority encoder
can realise the truth table of table 1.
Figure 6: Logic diagram of 4 − to − 2 line priority encoder.
Objectives
The objective of this experimental project is to become acquainted with the design of
decoder and an encoder. Demonstrate your ability to design and construct the decoder
and encoder, and to view the function of the inputs and outputs respectively.
Specification
Design a 2 − to − 4 decoder with enable input 𝐸, and a 4 − to − 2 line priority encoder.
Report
Write a laboratory report on this project:
(1) Explain in detail about the theory of 2 − to − 4 decoder with enable input 𝐸, and
the 4 − to − 2 line priority encoder.
(2) Discuss the method of productions and fabrications of decoder and encoder, and
comment on the test results.
(3) Prepare slides for presentation and demonstration of this project.
𝐴0
𝐴1
𝐸0
𝐸𝑆
𝑋1
𝑋
̅2
𝑋3
𝑋0
𝑋2